# PXI-7931 # 4x8 2-Wire Matrix Module User’s Manual Manual Rev.: Rev. 1.1 Date: February 8, 2020 Part Number: 50-17009-1010 # Copyright © 2004, 2020 ADLINK Technology Inc. All Rights Reserved.
Revision History.
1.0009-07-2004Initial release
1.108-02-2020Remove Star Trigger Out functionality
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# Table of Contents How to Use This Manual... # Chapter 1 Introduction ....... 1.1 Features... 1.2 Applications ....... 2 1.3 Specifications.... 2 1.4 Software Support .... 3 # Chapter 2 Installation ....... 2.1 Contents.... 5 2.2 Unpacking ....... .5 2.3 Mechanical Drawing...... .6 2.4 Installing the switch module into a PXI Platform ............. .6 # Chapter 3 Signal Connection........ 3.1 PXI-7931 Topology ........ C 3.2 PXI-7931 Pin assignment & Description ...... ..10 3.3 TB-6231 Terminal Board.. ..11 # Chapter 4 Operation Theorem ....... ... 21 4.1 Hardware Block Diagram .... ..21 4.2 Operation Mode ... ..22 4.3 Handshaking ..... ..22 4.4 Trigger Bus .... ..28 4.5 Auxiliary Digital I/O ... .29 4.6 Hot-Swap .... ..30 4.7 Emergency Shutdown... ..30 4.8 Watchdog Timer.... ..31 # Warranty Policy.......... ....33 # How to Use This Manual This User Manual is designed to assist users in the installation of the ADLINK PXI-7931, 4x8 2-Wire Matrix PXI Switch module. # Chapter 1 Introduction Gives an outline and overview of ADLINK switch modules’ features, specifications, and applications. # Chapter 2 Installation Describes how to install a switch module into a PXI chassis. For software library and utilities installation, please refer to the Software Users’ Guide. # Chapter 3 Signal Connection Shows the pin assignments and terminal board connection of the switch module. # Chapter 4 Operation Theorem Describes function blocks on ADLINK switch modules and operation instructions. # 1 # Introduction ADLINK PXI-7931 is a matrix module with 32 cross-point 2-wire relays (DPDT, 2 Form C). The default configuration of the PXI-7931 is a 4-group 2x4 2-wire matrix. With the termination board, TB-6231, users can flexibly choose one of the configurations: one 4x8, two 4x4, one 2x16, two 2x8, and four 2x4. Any contact of the PXI-7931 can connect to other contacts at the same bank, individually, or in combination. The PXI-7931 matrix module simplifies wiring and makes it easy to change the internal connection path. The contact position of the relays can be changed either by direct software commands or by following the instructions previously stored in the on-board scan list. The scan list advances upon the trigger from external measurement devices, such as a DMM. The scan list can also advance when the scan-delay timer expires. PXI trigger functions are supported and software programmable. Multiple modules can be synchronized without additional field wiring. # 1.1 Features • PXI specifications Rev. 2.0 compliant 3U Eurocard form factor, CompactPCI compliant (PICMG 2.0 R3.0) • PICMG 2.1 R2.0 CompactPCI Hot-Swap specifications compliant 32 DPDT (2 Form C) non-latching relays • Contact rating • 2A switching, 2A carrying • 220VDC, 125VAC • 200 operations per second • 1k-sample scanlist for deterministic scanning Provides handshaking signals to trigger external instruments Programmable emergency shutdown function and Watchdog timer for safety critical applications Eight auxiliary 3.3 V/TTL digital inputs/outputs with 5V tolerance • Supports PXI backplane triggers to synchronize multiple modules • Fully software programmable # 1.2 Applications • Industrial ON/OFF control External high power relay driving and signal switching • Laboratory automation Industrial automation Switch contact status sensing Limit switch monitoring Cooperating with other modules such as A/D and D/A peripherals to implement a data acquisition and control system # 1.3 Specifications # Relay Output • Number of cross-points: 32 (2-wire) Relay type: DPDT (2 Form C), non-latching Switching capacity: • Max. switching current: 2A • Max. switching voltage: 220VDC, 125VAC • Max. switching power: 60VA, 60W • Failure rate: 10µA, 10mVDC • Contact resistance: 100mΩ max. Relay set/reset time • Operate time: 4ms max. • Release time: 4ms max. • Bounce time: 1ms max. • Expected life: • Mechanical life: ${ 1 0 } ^ { 8 }$ operations min. Electrical life: ${ 1 0 } ^ { 5 }$ operations min. (2A @ 30VDC, resistive load) • Data transfer: Programmed I/O # Auxiliary Digital I/O • Numbers of channel: 8 inputs/outputs • Compatibility: 3.3 V/TTL (5V tolerant) • Data transfers: programmed I/O # Handshaking Signals • Programmable polarity Logic level: 3.3 V/TTL (5V tolerant) Trigger In source: AUX1, PXI trigger bus, PXI star trigger in • Scanner Advanced destination: AUX0, PXI trigger bus # 2 • Introduction # Safety functions • Emergency shutdown • Logic level: 3.3 V/TTL (5V tolerant) • Active with logic low (for AUX2/SHDNn pin) Emergency shutdown sources: AUX2/SHDNn, PXI star trigger input, PXI trigger bus Watchdog timer • Base clock available: 10MHz, fixed Counter width: 32-bit Watchdog Timer Overflow sources: Onboard 32-bitwatchdog timer, PXI star trigger input, PXI trigger bus # General Specifications • I/O Connector: 62-pin D-sub male • Operating temperature: 0 to $5 5 ^ { \circ } \mathsf { C }$ Storage temperature: -20 to $7 0 \textdegree$ • Humidity: 5 to 95% non-condensing • Power requirements (when all relays are activated simultaneously)
+5V+3.3V
1A400mA
Dimensions (not including connectors) • 160 mm x 100 mm # 1.4 Software Support ADLINK's ADL-SWITCH driver package is for Microsoft Windows operating systems, including Windows 98/ME/NT/2000/XP. The driver package also provides utilities to test your switch module, as well as programming samples and source codes in Microsoft Visual Basic and Visual C/C++. For other operating systems, please contact ADLINK for more information. This page intentionally left blank. # # Installation This chapter describes the installation process for the ADLINK switch module. Please read the contents of the package and the disassembling information carefully as they are important in the implementation of the ADLINK switch module. # 2.1 Contents The package consists of the following items in addition to the User Manual: • PXI-7931, 4x8 2-Wire Matrix PXI Switch module • This User Guide • ADLINK Software CD • ADL-Switch User’s Guide If any of these items are missing or broken, please do not hesitate to contact ADLINK or the dealer from whom the product was purchased. Keep the shipping materials and carton for future storage or shipping. # 2.2 Unpacking ADLINK switch module contains sensitive electronic components that can be easily damaged by static electricity. The switch module should be operated on a grounded anti-static mat. It is strongly recommended that the operator wears an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the box for any obvious damage. Check the unit to ensure there are no shipping and handling damages that may have occurred before proceeding. After opening, remove the switch module and place it only on a grounded antistatic surface component side up. Note: Do not apply power to the module if it has been damaged. # 2.3 Mechanical Drawing ![Technical line drawing of a mechanical assembly with no visible text or symbols](.pxi-7931-50-17009-1010-11/9a320958e3862decb9b98a98c4bd297d0109606e3a488ee92f4d29f4056a696a.jpg) Figure 1: ADLINK Switch Module ADLINK switch module is packaged in a Eurocard form factor compliant with PXI Specifications measuring 160 mm in length and 100 mm in height (not including connectors). A 62-pin connector is located at the front panel for wiring purposes and the J1/J2 IEC connectors in the rear are used to link the chassis backplane. With its modular, rugged, and high shock resistant mechanical features, the switch module functions exceptionally well in any harsh environment application. # 2.4 Installing the switch module into a PXI Platform To insert the ADLINK PXI switch module, align the module’s edge with the card guide in the PXI chassis. Slide the switch module into the chassis, until resistance is felt from the PXI connector. Push the ejector upwards and fully insert the switch module into the chassis. Once inserted, a “click” can be heard from the ejector latch. Tighten the screws on the front panel. ![Pin & Sockets\nConnectors\nCard Guide\nCard Guide\nFront\nPanel](.pxi-7931-50-17009-1010-11/444c83bd47210d06cc85443b047eeb21a6f11fafc6bde118bf767e511ce50edc.jpg) Figure 2: Installing the switch module into a PXI platform This page intentionally left blank. # # Signal Connection # 3.1 PXI-7931 Topology Relays on the PXI-7931 are configured into a 4-group 2x4 2-wire matrix. Users can switch on/off to connect or disconnect any number of rows to any number of columns in the same bank. This configuration can let user simultaneous connects one or more input signals to one or more devices. All signal paths on PXI-7931 are inherently break-before-make. The TB-6231 is a 2-wire terminal board; each path has two ways (i.e. R0 is indicated as R0+ and R0-). ![The diagram illustrates a data flow from left to right involving the following labeled blocks and connections:\n\n**Left Section:**\n* A large block labeled **TB-6231**.\n* To its left is a vertical list of text:\n * **B0C0+ ~ B0C3+**\n * **B0R0+ ~ B0R1+**\n * **B0R0- ~ B0R1-**\n * **B0C0- ~ B0C3-**\n * **B1C0+ ~ B1C3+**\n * **B1R0+ ~ B1R1+**\n * **B1R0- ~ B1R1-**\n * **B1C0- ~ B1C3-**\n * **B2C0+ ~ B2C3+**\n * **B2R0+ ~ B2R1+**\n * **B2R0- ~ B2R1-**\n * **B2C0- ~ B2C3-**\n * **B3C0+ ~ B3C3+**\n * **B3R0+ ~ B3R1+**\n * **B3R0- ~ B3R1-**\n * **B3C0- ~ B3C3-**\n\n**Middle Section:**\nThis section consists of four stacked blocks, each containing **2 x 4 Matrix** and a bank label. Connections from the TB-6231 block lead into each, labeled as follows:\n* **Bank 0**: Connected via **2 rows (+)**, **4 columns (+)**, **4 columns (-)**, and **2 rows (-)**.\n* **Bank 1**: Connected via **2 rows (+)**, **4 columns (+)**, **4 columns (-)**, and **2 rows (-)**.\n* **Bank 2**: Connected via **2 rows (+)**, **4 columns (+)**, **4 columns (-)**, and **2 rows (-)**.\n* **Bank 3**: Connected via **2 rows (+)**, **4 columns (+)**, **4 columns (-)**, and **2 rows (-)**.\n\n**Right Section:**\n* To the right of each bank block is a connection labeled **8 control line**.\n* These four lines feed into a larger area labeled **PXI-7931** at the top right.\n* From this area, a single connection labeled **32 control line** leads to the far right block labeled **FPGA**.](.pxi-7931-50-17009-1010-11/ccc408fee914becd856163e4c55c6b4f469da5ab1d3f9830ddea4d474c087803.jpg) Figure 3: 2-wire paths # 3.2 PXI-7931 Pin assignment & Description
22. C8+
43. C0+23. C8-1. R0+
44. C0-24. C9+2. R0-
45. C1+25. C9-3. R1+
46. C1-26. C10+4. R1-
47. C2+27. C10-5. R2+
48. C2-28. C11+6. R2-
49. C3+29. C11-7. R3+
50. C3-30. C12+8. R3-
51. C4+31. C12-9. R4+
52. C4-32. C13+10. R4-
53. C5+33. C13-11. R5+
54. C5-34. C14+12. R5-
55. C6+35. C14-13. R6+
56. C6-36. C15+14. R6-
57. C7+37. C15-15. R7+
58. C7-38. NC16. R7-
59. NC39. NC17. NC
60. AUX340. AUX418. AUX2/SHDNn
61. AUX641. +5V out19. AUX5
62. AUX742. AUX1/TRG_IN20. GND
21. AUX0/S_ADV
Table 1: Pin Assignment
Signal NameTypeDescription
C0+ to C15+C0- to C15-Input/OutputColumns: signals are connected to the switch module
R0+ to R7+R0- to R7-Input/OutputRows: signals are connected to the switch module
AUX[7..0]Input/OutputProgrammable Digital I/O with tri-state control.AUX[2..0] are dual function pins used for triggering, refer to chapter 4 for details.
TRG_INInputTrigger input for handshaking operation
S_ADVOutputScanner Advanced trigger output for handshaking operation
SHDNnInputActive-low Emergency Shutdown trigger
+5V outOutputUnregulated +5V DC Source, maximum 100mA current loading
GNDOutputGround
NCNot ConnectedUnused pin
Table 2: Pin Description # 3.3 TB-6231 Terminal Board # Configurations The TB-6231 is a screw terminal board with D-sub 62-pin female connector. The terminal board can attach to PXI-7931 directly, or through ADLINK’s custom-made high-capacity 62-pin D-sub cable. Users can use the TB-6231 terminal board to make various matrix configurations. The TB-6231’s default configuration is a 4-group 2x4 matrix in 2-wire. If other matrix configurations are preferred, users can refer the table below to short the relative pads. ![2X4X4\n2X8X2\n2X16X1\n4X4X2\n4X8X1](.pxi-7931-50-17009-1010-11/64d361de6c2f6e7dd6a8527bc1e3e251d8d266e9c08ef558702067927859e909.jpg) For example, to use a 2x4 matrix, do not short any pads. To use 2x16 matrix, short the last 12 pads at the lower-right corner of the table. # 2x4 Matrix This configuration has four independent 2x4 matrices, Bank0 to Bank3, each with two rows and four columns. The following diagram illustrates the PXI-7931 with the TB-6231. ![The flowchart depicts a data flow from left to right involving signal processing blocks.\n\n**Labeled Blocks:**\n* **TB-6231**: A vertical rectangular block on the left.\n* **2 x 4 Matrix**: Four identical blocks stacked vertically. Each contains a smaller label inside.\n * **Bank 0**: Inside the top '2 x 4 Matrix'.\n * **Bank 1**: Inside the second '2 x 4 Matrix'.\n * **Bank 2**: Inside the third '2 x 4 Matrix'.\n * **Bank 3**: Inside the fourth '2 x 4 Matrix'.\n* **PXI-7931**: A label positioned at the top of the central section containing the matrices.\n* **FPGA**: A vertical rectangular block on the far right.\n\n**Connections and Text Labels:**\n* **Inputs (Far Left):** A column of text labels connects to the left side of the **TB-6231** block:\n * B0C0~B0C3-\n * B0R0~B0R1+\n * B0R0~B0R1-\n * B0C0~B0C3-\n * B1C0~B1C3+\n * B1R0~B1R1+\n * B1R0~B1R1-\n * B1C0~B1C3-\n * B2C0~B2C3+\n * B2R0~B2R1+\n * B2R0~B2R1-\n * B2C0~B2C3-\n * B3C0~B3C3+\n * B3R0~B3R1+\n * B3R0~B3R1-\n * B3C0~B3C3-\n* **TB-6231 to Matrix Blocks:** Lines extend from the right side of **TB-6231** to the left side of each **2 x 4 Matrix** block. Each connection group is labeled with four lines of text:\n * 2 rows (+)\n * 4 columns (+)\n * 4 columns (-)\n * 2 rows (-)\n (This pattern repeats for Bank 0, Bank 1, Bank 2, and Bank 3).\n* **Matrix Blocks to Control Lines:** Each **2 x 4 Matrix** block has an output line extending to the right, labeled **8 control line**.\n* **Control Lines to FPGA:** The four **8 control line** connections merge into a single vertical line labeled **32 controlline**, which connects to the left side of the **FPGA** block.](.pxi-7931-50-17009-1010-11/4d288c9c2ff79629b93eea7f034d12558ae8621bf7f1d55db586e958040501a0.jpg) Figure 4: 2x4 Matrix (I) In this configuration, the TB-6231 would not have any shorted pads.
2X4X4
2X8X2■■■■■■■■
2X16X1■■■■■■■■■■■■
4X4X2■■■■■■■■■■■■■■■■
4X8X1■■■■■■■■■■■■■■■■■■■■■■■
The grid below shows the names used for software configuration with corresponding traces to the TB-6231. ![The image displays four identical rectangular diagrams stacked vertically, labeled 'Bank 0' through 'Bank 3'. Each diagram features a 2x4 grid of smaller boxes containing coordinate pairs, surrounded by external connection labels.\n\n**Bank 0**\n* **Top Labels:** C0, C1, C2, C3 (connected to the top row of boxes)\n* **Left Labels:** R0, R1 (connected to the left side of the top and bottom rows respectively)\n* **Grid Top Row:** (0,0), (0,1), (0,2), (0,3)\n* **Grid Bottom Row:** (1,0), (1,1), (1,2), (1,3)\n* **Label:** Bank 0\n\n**Bank 1**\n* **Top Labels:** C4, C5, C6, C7\n* **Left Labels:** R2, R3\n* **Grid Top Row:** (0,0), (0,1), (0,2), (0,3)\n* **Grid Bottom Row:** (1,0), (1,1), (1,2), (1,3)\n* **Label:** Bank 1\n\n**Bank 2**\n* **Top Labels:** C8, C9, C10, C11\n* **Left Labels:** R4, R5\n* **Grid Top Row:** (0,0), (0,1), (0,2), (0,3)\n* **Grid Bottom Row:** (1,0), (1,1), (1,2), (1,3)\n* **Label:** Bank 2\n\n**Bank 3**\n* **Top Labels:** C12, C13, C14, C15\n* **Left Labels:** R6, R7\n* **Grid Top Row:** (0,0), (0,1), (0,2), (0,3)\n* **Grid Bottom Row:** (1,0), (1,1), (1,2), (1,3)\n* **Label:** Bank 3](.pxi-7931-50-17009-1010-11/e77652f02662842be830807a976b573d396668093550662873e81563931c7317.jpg) Figure 5: 2x4 Matrix (II) # 2x8 Matrix This configuration has two independent 2x8 matrices ranging from Bank0 to Bank1, each has two rows and eight columns. The following diagram illustrates the PXI-7931 with the TB-6231 to produce relative paths. ![**Labeled Blocks:**\n* **TB-6231**: A large vertical rectangular block on the left.\n* **PXI-7931**: A label at the top center.\n* **Bank 0, Bank 1, Bank 2, Bank 3**: Four rectangular blocks stacked vertically in the center. Each contains the text '2 x 4 Matrix'.\n* **FPGA**: A tall vertical rectangular block on the far right.\n\n**Text Labels and Connections:**\n* **TB-6231 Contents**: The block contains the following labels: 'BOC0+ ~ BOC7+', 'BOR0+ ~ BOR1+', 'BOR0- ~ BOR1-', 'BOC0- ~ BOC7-', 'B1C0+ ~ B1C7+', 'B1R0+ ~ B1R1+', 'B1R0- ~ B1R1-', 'B1C0- ~ B1C7-'.\n* **Signal Connections (TB-6231 to Matrix Banks)**: A series of text labels describes the connections between the TB-6231 block and the Matrix Banks, reading top-to-bottom: '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)', '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)', '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)', '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)'.\n* **Control Connections (Matrix Banks to FPGA)**: Each Matrix Bank (Bank 0, Bank 1, Bank 2, Bank 3) has a connection labeled '8 control line'. These four lines merge into a single line labeled '32 control line' connecting to the FPGA.](.pxi-7931-50-17009-1010-11/d8821a320ee7be13d344bd31f455a8f43d88f231fc7aa072b2622bca86d85c24.jpg) Figure 6: 2x8 Matrix (I) To use a 2x8 matrix, short the following TB-6231 pads. ![2X4X4\n2X8X2\n2X16X1\n4X4X2\n4X8X1](.pxi-7931-50-17009-1010-11/0a2f09a4939411586e2daf9e1fa775e1ef756cce9f2fceac668abbeb425c7d36.jpg) The grid below shows the names used for software configuration with corresponding traces to the TB-6231 ![The diagram shows a structure labeled **Bank 0** at the bottom, containing two rows of smaller blocks.\n\n**Blocks:**\n* **Top Row:** '(0, 0)', '(0, 1)', '(0, 2)', '(0, 3)', '(0, 4)', '(0, 5)', '(0, 6)', '(0, 7)'\n* **Bottom Row:** '(1, 0)', '(1, 1)', '(1, 2)', '(1, 3)', '(1, 4)', '(1, 5)', '(1, 6)', '(1, 7)'\n\n**Connections:**\n* **Top Inputs:**\n * **C0** connects to '(0, 0)'\n * **C1** connects to '(0, 1)'\n * **C2** connects to '(0, 2)'\n * **C3** connects to '(0, 3)'\n * **C4** connects to '(0, 4)'\n * **C5** connects to '(0, 5)'\n * **C6** connects to '(0, 6)'\n * **C7** connects to '(0, 7)'\n* **Left Inputs:**\n * **R0, R2** connects to '(0, 0)'\n * **R1, R3** connects to '(1, 0)'\n* **Internal Vertical Connections:** Each block in the top row connects to the corresponding block in the bottom row directly below it (e.g., '(0, 0)' connects to '(1, 0)').\n* **Internal Horizontal Connections:** Blocks are connected sequentially from left to right in each row (e.g., '(0, 0)' connects to '(0, 1)').](.pxi-7931-50-17009-1010-11/fce4b536cb623ae2a20375e66ac08c97058a58539afd0f3f3df724db9ad214a6.jpg) ![Based on the provided image, here is the description of the flowchart/block diagram:\n\n**Labeled Blocks and Container:**\nThe diagram features a large rectangular container labeled **Bank 1** at the bottom. Inside this container are two rows of blocks:\n* **Top Row:** (0, 0), (0, 1), (0, 2), (0, 3), (0, 4), (0, 5), (0, 6), (0, 7)\n* **Bottom Row:** (1, 0), (1, 1), (1, 2), (1, 3), (1, 4), (1, 5), (1, 6), (1, 7)\n\n**External Connections (Inputs/Outputs):**\n* **C8** connects vertically to block **(0, 0)**\n* **C9** connects vertically to block **(0, 1)**\n* **C10** connects vertically to block **(0, 2)**\n* **C11** connects vertically to block **(0, 3)**\n* **C12** connects vertically to block **(0, 4)**\n* **C13** connects vertically to block **(0, 5)**\n* **C14** connects vertically to block **(0, 6)**\n* **C15** connects vertically to block **(0, 7)**\n* **R4, R6** connects horizontally to the left side of block **(0, 0)**\n* **R5, R7** connects horizontally to the left side of block **(1, 0)**\n\n**Internal Connections:**\n* **Horizontal:** Blocks in the top row are connected sequentially from left to right (e.g., (0, 0) connects to (0, 1), (0, 1) to (0, 2), etc., up to (0, 7)). Blocks in the bottom row are connected sequentially from left to right (e.g., (1, 0) connects to (1, 1), (1, 1) to (1, 2), etc., up to (1, 7)).\n* **Vertical:** Each block in the top row is connected vertically to the block directly below it in the bottom row (e.g., (0, 0) connects to (1, 0), (0, 1) to (1, 1), etc., up to (0, 7) connecting to (1, 7)).](.pxi-7931-50-17009-1010-11/60c70d59722ccace4988e2ef6018cda2c9289bff07e86ee9747d547c70122874.jpg) Figure 7: 2x8 Matrix (II) # 2x16 Matrix This configuration has one independent 2x16 matrix with two rows and 16 columns. The following diagram illustrates the PXI-7931 with the TB-6231 to produce relative paths ![This diagram illustrates a signal routing architecture involving three main sections:\n\n**Labeled Blocks:**\n* **TB-6231:** A vertical block on the far left.\n* **Signal Labels:** Text to the left of TB-6231 lists ranges: 'B0C0+ ~ B0C15+', 'B0R0 ~ B0R1+', 'B0R0 ~ B0R1-', and 'B0C0 ~ B0C15-'.\n* **PXI-7931:** A label at the top center indicating the system module.\n* **Matrix/Bank Groups:** Four identical groups stacked vertically. Each contains a box labeled '**2 x 4 Matrix**' and a box below it labeled '**Bank 0**', '**Bank 1**', '**Bank 2**', or '**Bank 3**'.\n* **Input Labels:** To the left of each Matrix/Bank group are connection labels: '**2 rows (+)**', '**4 columns (+)**', '**4 columns (-)**', and '**2 rows (-)**'.\n* **FPGA:** A vertical block on the far right.\n\n**Connections:**\n* **TB-6231 to Matrix/Banks:** Lines connect the TB-6231 block to the four Matrix/Bank groups, labeled with the row/column indicators listed above.\n* **Matrix/Banks to Control Line:** Each Bank group has an output labeled '**8 control line**'.\n* **Control Line to FPGA:** The four '8 control line' outputs merge into a single thick vertical line labeled '**32 control line**,' which connects to the **FPGA** block.](.pxi-7931-50-17009-1010-11/5d79d76ddb9522ad006357138bb89f4243944661608cda2d4f891eb9e912d915.jpg) Figure 8: 2x16 Matrix (I) To use a 2x16 matrix, short the following eight TB-6231 pads. ![2X4X4\n2X8X2\n2X16X1\n4X4X2\n4X8X1](.pxi-7931-50-17009-1010-11/2ae83917b3970cf3eb4ff9dcc3e067adfb57abe08cfc5a4f0ca989f0c1ede300.jpg) The grid below shows the names used for software configuration with corresponding traces to the TB-6231 ![The diagram depicts a grid structure enclosed in a large bracket labeled **Bank 0** at the bottom right. It features two rows of rectangular blocks arranged in 16 columns.\n\n**Labeled Blocks:**\n* **Top Row:** Blocks labeled sequentially from left to right: **{0, 0}**, **{0, 1}**, **{0, 2}**, **{0, 3}**, **{0, 4}**, **{0, 5}**, **{0, 6}**, **{0, 7}**, **{0, 8}**, **{0, 9}**, **{0, 10}**, **{0, 11}**, **{0, 12}**, **{0, 13}**, **{0, 14}**, **{0, 15}**.\n* **Bottom Row:** Blocks labeled sequentially from left to right: **{1, 0}**, **{1, 1}**, **{1, 2}**, **{1, 3}**, **{1, 4}**, **{1, 5}**, **{1, 6}**, **{1, 7}**, **{1, 8}**, **{1, 9}**, **{1, 10}**, **{1, 11}**, **{1, 12}**, **{1, 13}**, **{1, 14}**, **{1, 15}**.\n\n**Connections and Labels:**\n* **Column Inputs:** Vertical lines labeled **C0** through **C15** across the top connect downwards into the corresponding blocks in the top row (e.g., C0 connects to {0, 0}).\n* **Row Labels:** To the left of the top row is the text **R0, R2, R4, R6**. To the left of the bottom row is the text **R1, R3, R5, R7**.\n* **Horizontal Connections:** Horizontal lines connect adjacent blocks within each row sequentially (e.g., {0, 0} connects to {0, 1}, and {1, 0} connects to {1, 1}).\n* **Vertical Connections:** Vertical lines connect each block in the top row directly to the corresponding block in the bottom row (e.g., {0, 0} connects to {1, 0}).](.pxi-7931-50-17009-1010-11/9ac9aa83c52dd764502bcadebe89f1bdcd1741803b421b90b9d805e751658433.jpg) Figure 9: 2x16 Matrix (II) # 4x4 Matrix This configuration has two independent 4x4 matrices ranging from Bank0 to Bank1, each with four rows and four columns. The following diagram illustrates the PXI-7931 with the TB-6231 to produce relative paths ![This block diagram illustrates a signal routing and control structure involving input labels, a terminal block, matrix banks, and an FPGA.\n\n**Labeled Blocks:**\n* **TB-6231**: A tall vertical rectangular block on the left.\n* **Input Labels (Left)**: Two groups of text labels are positioned to the left of TB-6231.\n * Top group: 'B0C0+ ~ B0C3+', 'B0R0+ ~ B0R3+', 'B0R0- ~ B0R3-', 'B0C0- ~ B0C3-'.\n * Bottom group: 'B1C0+ ~ B1C3+', 'B1R0+ ~ B1R3+', 'B1R0- ~ B1R3-', 'B1C0- ~ B1C3-'.\n* **Matrix Banks**: Four stacked rectangular blocks labeled '2 x 4 Matrix' with sub-labels 'Bank 0', 'Bank 1', 'Bank 2', and 'Bank 3'.\n* **PXI-7931**: A label at the top right, likely indicating the module housing the banks.\n* **FPGA**: A tall vertical rectangular block on the far right.\n\n**Connections:**\n* **TB-6231 to Banks**: Lines extend from TB-6231 to each of the four banks. Each connection set is labeled with the following text (repeated for each bank):\n * '2 rows (+)'\n * '4 columns (+)'\n * '4 columns (-)'\n * '2 rows (-)'\n* **Banks to FPGA**:\n * From each bank ('Bank 0' through 'Bank 3'), a line extends to the right labeled '8 control line'.\n * These four lines merge into a single vertical line labeled '32 control line' which connects to the 'FPGA' block.](.pxi-7931-50-17009-1010-11/08a32cba237ebc8a0aa92be4cd039f87618c4a5f00df482f536b2cab7b9a7182.jpg) Figure 10: 4x4 Matrix (I) To use a 2x16 matrix, short the following 16 TB-6231 pads. ![2X4X4\n2X8X2\n2X16X1\n4X4X2\n4X8X1](.pxi-7931-50-17009-1010-11/5f425758871a00d41cd3eb48bdea77d1031be61e9a8bc77c6906318a52918dde.jpg) The grid below shows the names used for software configuration with corresponding traces to the TB-6231 ![This diagram depicts two distinct processing arrays, labeled **Bank 0** and **Bank 1**, arranged vertically. Each bank contains a 4x4 grid of interconnected blocks.\n\n**Bank 0 (Top Section)**\n* **External Labels:**\n * Top inputs: **C0, C8**, **C1, C9**, **C2, C10**, **C3, C11**\n * Left inputs: **R0**, **R1**, **R4**, **R5**\n* **Labeled Blocks (Grid):**\n * Row 1: **(0, 0)**, **(0, 1)**, **(0, 2)**, **(0, 3)**\n * Row 2: **(1, 0)**, **(1, 1)**, **(1, 2)**, **(1, 3)**\n * Row 3: **(2, 0)**, **(2, 1)**, **(2, 2)**, **(2, 3)**\n * Row 4: **(3, 0)**, **(3, 1)**, **(3, 2)**, **(3, 3)**\n* **Connections:**\n * Vertical lines connect top labels to the first row blocks: **C0, C8** to **(0, 0)**, **C1, C9** to **(0, 1)**, **C2, C10** to **(0, 2)**, and **C3, C11** to **(0, 3)**.\n * Horizontal lines connect left labels to the first column blocks: **R0** to **(0, 0)**, **R1** to **(1, 0)**, **R4** to **(2, 0)**, and **R5** to **(3, 0)**.\n * Internal mesh connections link adjacent blocks horizontally and vertically (e.g., **(0, 0)** connects to **(0, 1)** and **(1, 0)**).\n * A label at the bottom reads **Bank 0**.\n\n**Bank 1 (Bottom Section)**\n* **External Labels:**\n * Top inputs: **C4, C12**, **C5, C13**, **C6, C14**, **C7, C15**\n * Left inputs: **R2**, **R3**, **R6**, **R7**\n* **Labeled Blocks (Grid):**\n * Row 1: **(0, 0)**, **(0, 1)**, **(0, 2)**, **(0, 3)**\n * Row 2: **(1, 0)**, **(1, 1)**, **(1, 2)**, **(1, 3)**\n * Row 3: **(2, 0)**, **(2, 1)**, **(2, 2)**, **(2, 3)**\n * Row 4: **(3, 0)**, **(3, 1)**, **(3, 2)**, **(3, 3)**\n* **Connections:**\n * Vertical lines connect top labels to the first row blocks: **C4, C12** to **(0, 0)**, **C5, C13** to **(0, 1)**, **C6, C14** to **(0, 2)**, and **C7, C15** to **(0, 3)**.\n * Horizontal lines connect left labels to the first column blocks: **R2** to **(0, 0)**, **R3** to **(1, 0)**, **R6** to **(2, 0)**, and **R7** to **(3, 0)**.\n * Internal mesh connections link adjacent blocks horizontally and vertically, identical to Bank 0.\n * A label at the bottom reads **Bank 1**.](.pxi-7931-50-17009-1010-11/99fbf860bb8068ab08ef454ad8916e5abe97d388006a6a119fb5fb89d5298b55.jpg) Figure 11: 4x4 Matrix (II) # 4x8 Matrix This configuration has one 4x8 matrix, Bank0, with four rows and eight columns. The following diagram illustrates the PXI-7931 with the TB-6231 to produce relative paths ![This block diagram illustrates a signal routing path from left to right involving multiple blocks and connections:\n\n**Leftmost Column:**\nFour input labels are stacked vertically:\n* 'BOC0+ ~ BOC7+'\n* 'BOR0+ ~ BOR3+'\n* 'BOR0- ~ BOR3-'\n* 'BOC0- ~ BOC7-'\n\n**Second Column:**\nA large vertical rectangle labeled **'TB-6231'**.\n\n**Third Column (Processing Banks):**\nFour distinct sections, each containing signal labels, a matrix block, and a control line output:\n\n1. **Bank 0 Section:**\n * Signal labels: '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)'\n * Connected to a block containing '2 x 4 Matrix' and 'Bank 0'.\n * Output: '8 control line'\n\n2. **Bank 1 Section:**\n * Signal labels: '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)'\n * Connected to a block containing '2 x 4 Matrix' and 'Bank 1'.\n * Output: '8 control line'\n\n3. **Bank 2 Section:**\n * Signal labels: '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)'\n * Connected to a block containing '2 x 4 Matrix' and 'Bank 2'.\n * Output: '8 control line'\n\n4. **Bank 3 Section:**\n * Signal labels: '2 rows (+)', '4 columns (+)', '4 columns (-)', '2 rows (-)'\n * Connected to a block containing '2 x 4 Matrix' and 'Bank 3'.\n * Output: '8 control line'\n\n**Top Right Label:**\nThe text **'PXI-7931'** appears at the top right.\n\n**Rightmost Column (FPGA):**\n* The four '8 control line' outputs merge into a single vertical line labeled **'32 control line'**.\n* This line connects to a tall vertical rectangle labeled **'FPGA'**.](.pxi-7931-50-17009-1010-11/a663eb513cb6587a7bf81f38a0636ba4ee16198ca0431b761a3be774179e0809.jpg) Figure 12: 4x8 Matrix (I) To use a 2x16 matrix, short the following 24 TB-6231 pads. ![2X4X4\n2X8X2\n2X16X1\n4X4X2\n4X8X1](.pxi-7931-50-17009-1010-11/45fd9042005e6778607896a8d3ca4ac0799b91a7a95fe0585ae532d0b9f4f54c.jpg) The grid below shows the names used for software configuration with corresponding traces to the TB-6231 ![The diagram displays a grid of blocks labeled 'Bank 0' at the bottom.\n\n**Labeled Blocks:**\nThe grid consists of 4 rows and 8 columns of square blocks containing coordinate pairs:\n* **Row 1:** (0, 0), (0, 1), (0, 2), (0, 3), (0, 4), (0, 5), (0, 6), (0, 7)\n* **Row 2:** (1, 0), (1, 1), (1, 2), (1, 3), (1, 4), (1, 5), (1, 6), (1, 7)\n* **Row 3:** (2, 0), (2, 1), (2, 2), (2, 3), (2, 4), (2, 5), (2, 6), (2, 7)\n* **Row 4:** (3, 0), (3, 1), (3, 2), (3, 3), (3, 4), (3, 5), (3, 6), (3, 7)\n\n**External Labels:**\n* **Top (Column Inputs):** C0, C8, C1, C9, C2, C10, C3, C11, C4, C12, C5, C13, C6, C14, C7, C15\n* **Left (Row Inputs):** R0, R2, R1, R3, R4, R6, R5, R7\n\n**Connections:**\n* **Horizontal:** Blocks within each row are connected sequentially from left to right (e.g., (0, 0) connects to (0, 1), continuing to (0, 7)). This pattern repeats for all four rows.\n* **Vertical:** Blocks within each column are connected sequentially from top to bottom (e.g., (0, 0) connects to (1, 0), which connects to (2, 0), and finally to (3, 0)). This pattern repeats for all eight columns.\n* **Input Connections:**\n * **Left Labels:** Connect to the leftmost block of their respective row:\n * R0, R2 connects to (0, 0)\n * R1, R3 connects to (1, 0)\n * R4, R6 connects to (2, 0)\n * R5, R7 connects to (3, 0)\n * **Top Labels:** Connect to the topmost block of their respective column:\n * C0, C8 connects to (0, 0)\n * C1, C9 connects to (0, 1)\n * C2, C10 connects to (0, 2)\n * C3, C11 connects to (0, 3)\n * C4, C12 connects to (0, 4)\n * C5, C13 connects to (0, 5)\n * C6, C14 connects to (0, 6)\n * C7, C15 connects to (0, 7)](.pxi-7931-50-17009-1010-11/cb49987ab1bf42e7c902ef779bf3a84cbac628a0e2f2268d21535dc575df7115.jpg) Figure 13: 4x8 Matrix (II) # 4 # Operation Theorem # 4.1 Hardware Block Diagram The ADLINK PXI Switch Module features an onboard FPGA for relay switching control, trigger control, scanlist storage and sequencing. The PXI triggering and synchronization functions, such as Star Trigger and Trigger Bus are also supported. In addition to the Trigger In and Scanner Advanced signals for external instruments handshaking, the switch module provides eight channels of programmable digital I/O interface to facilitate general purpose control applications. To make full use of the flexible trigger and signaling system on the PXI platform, the switch module has a built-in signal routing matrix that can exchange signals between front panel digital I/O, Star Trigger, and Trigger Bus. ![Based on the provided block diagram, here is an accurate and concise description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n* Front Connector\n* Relay\n* Scan Memory\n* Relay Control\n* Timing Control\n* Signal Routing Matrix\n* Trigger Control\n* DIO\n* Scan-Advance\n* Trigger-in\n* PXI Interface\n* Star Trigger In\n* PXI Trigger Bus\n* PXI Connector\n\n**Connections:**\n* **Front Connector**: Has bidirectional (double-arrow) connections with **Relay**, **DIO**, and **Scan-Advance**. It has a unidirectional connection (arrow pointing right) to **Trigger-in**.\n* **Relay**: Has a bidirectional connection with **Relay Control**.\n* **Scan Memory**: Has a bidirectional connection with **Relay Control**.\n* **Relay Control**: Has a bidirectional connection with **PXI Interface**.\n* **DIO**: Has a bidirectional connection with **Signal Routing Matrix**.\n* **Scan-Advance**: Has a bidirectional connection with **Signal Routing Matrix**.\n* **Signal Routing Matrix**: Has a bidirectional connection with **Star Trigger In**.\n* **Trigger-in**: Has a unidirectional connection (arrow pointing right) with **Trigger Control**.\n* **Trigger Control**: Has a bidirectional connection with **PXI Trigger Bus**.\n* **PXI Interface**: Has a bidirectional connection with **PXI Connector**.\n* **Star Trigger In**: Has a bidirectional connection with **PXI Connector**.\n* **PXI Trigger Bus**: Has a bidirectional connection with **PXI Connector**.\n\n**Structural Note:**\nThe blocks **Relay Control**, **Timing Control**, **Signal Routing Matrix**, and **Trigger Control** are stacked vertically within a single large central rectangle. **Timing Control** is listed but has no external connections shown in the diagram.](.pxi-7931-50-17009-1010-11/64a293e587ecd84976d9da3f54158d63efe7067cffa6c56c5da93e77fad446cc.jpg) Figure 14: Hardware Block Diagram # 4.2 Operation Mode The ADLINK PXI Switch Module provides two relay operation modes to accommodate different application requirements. # Direct-update The Switch Module updates the relay pattern immediately upon receiving a software command. This mode provides a straightforward control over switch module with minimal hardware intervention. If relay contact bouncing is of a concern, users would need to insert software delay. ADLINK recommends the debounce time to be at least 5ms on the PXI-7931. # Auto-scan The ADLINK PXI switch module features onboard memory to store user specified scanlist of up to 1024-entry. In each scanlist entry, users can specify relay pattern, pattern advancing delay time and criterion. The switch module can set status bit or generate local interrupt to inform user’s program whether the pattern has been debounced and advanced to the next scanlist entry. Users can also specify one-time or cyclic scanning of scanlist entries. This operating mode supports trigger signals for instrument handshaking. For more information on handshaking signals, please refer to section 4.3. # 4.3 Handshaking In the Auto-scan mode, ADLINK PXI switch module accepts Trigger In and generates Scanner Advanced signal to synchronize relay switching and measurements with PXI instruments or external measurement devices. # Trigger In The Trigger In signal from PXI instruments or external measurement devices instruct the ADLINK PXI switch module to update the relay pattern according to the one specified in the scanlist entry. Users may specify wait-for-trigger instruction in a scanlist entry, to have the switch module wait for the Trigger In before relay pattern is updated. The polarity of Trigger In can be set to either rising-edge or falling-edge active. For more information on scanlist configuration, please refer to the software programming users’ guide. Figure 15 illustrates the available signal sources for the Trigger In signal. Signal names in the solid-line box represent the external (physical) signal on connectors, and signals in the dotted-line box represents switch module’s internal signal. ![This block diagram illustrates a selection logic circuit (resembling a multiplexer) with five inputs and one output:\n\n**Inputs:**\n* **Software Trigger**\n* **TRG_IN**\n* **Trigger Bus (7...0)**\n* **AUX(7...0)**\n* **Star Trigger In**\n\n**Connections:**\nAll five input labels are connected via lines to the wide input side of a central trapezoidal block. A single line exits the narrow output side of this central block and connects to the final output.\n\n**Output:**\n* **Trigger In Signal**](.pxi-7931-50-17009-1010-11/40e14c4b138263a998622902a245d854b2b8efb607a4f5995e880fc73c5f57ef.jpg) Figure 15: Available signal sources for Trigger In # Scanner Advanced After updating the relay pattern, the switch module starts its debounce timer and waits for the relay contacts to settle. When the debounce time elapses, the switch module will generate a Scanner Advanced signal to notify the PXI instruments or external measurement devices that the relay contacts have settled, and ready to take a new measurement. The waveform, polarity and pulse width of Scanner Advanced signal can also be software programmed. For more information on scanlist configuration, please refer to the software programming users’ guide. Figure 16 illustrates the available signal destinations for the Scanner Advanced signal. Signal names in the solid-line boxes represent the external (physical) signal on connectors, while signals in the dotted-line boxes represent switch module’s internal signal. ![The diagram depicts a signal distribution path flowing from left to right.\n\n**Labeled Blocks:**\n* **Input:** A dashed rectangular block on the far left labeled 'Scanner Adv. Signal'.\n* **Central Component:** An unlabeled vertical rectangular block in the center.\n* **Outputs:** Three stacked rectangular blocks on the right side labeled:\n * 'S_ADV' (top)\n * 'Trigger Bus (7...0)' (middle)\n * 'AUX (7...0)' (bottom)\n\n**Connections:**\n* A single horizontal line connects the 'Scanner Adv. Signal' block to the left side of the central vertical block.\n* Three horizontal lines extend from the right side of the central block, connecting individually to the left side of each of the three output blocks in sequence (top to S_ADV, middle to Trigger Bus, bottom to AUX).](.pxi-7931-50-17009-1010-11/b2c251676b8a878e81794fddd159d2418bd815b59af19b57b665dd0fa90c543e.jpg) Figure 16: Available signal destinations for Scanner Advanced # Handshaking protocol Figures 17 and 18 depict the relationship between Trigger In, Scanner Advanced, and relay pattern in handshaking mode. In Figure 17 the Scanner Advanced is set to pulsating mode. ![This is a timing diagram illustrating the relationship between three signals over time. It consists of three horizontal tracks aligned by vertical dotted lines:\n\n**1. Trigger In Track (Top)**\n* **Label:** 'Trigger In'\n* **Visuals:** A square wave signal with pulses.\n* **Labels & Connections:**\n * **\$T_S\$**: Horizontal double arrows indicating the duration (width) of the Trigger In pulses.\n * **\$T_{A1}\$**, **\$T_{A2}\$**, and **\$T_A\$** (with a subscript **3**): Horizontal double arrows indicating the time delay between the start of a 'Trigger In' pulse and the corresponding 'Scanner Advanced' pulse.\n * Double slash marks (//) indicate skipped time intervals.\n\n**2. Scanner Advanced Track (Middle)**\n* **Label:** 'Scanner Advanced'\n* **Visuals:** Square pulses that appear later in the timeline than the 'Trigger In' pulses.\n* **Connections:** The rising edge of each 'Scanner Advanced' pulse aligns vertically with the transition of the 'Relay status' from one state to the next.\n* Double slash marks (//) indicate skipped time.\n\n**3. Relay status Track (Bottom)**\n* **Label:** 'Relay status'\n* **Visuals:** A sequence of rectangular blocks representing state changes.\n* **Labels:**\n * **'#0'**\n * **'Pattern #1'**\n * **'Pattern #2'**\n * **'Pattern #3'**\n * **'#4'**\n* **Connections:** The blocks are connected by 'X' shaped transitions.\n* **Label:** **'Operation start'** is located at the bottom left, indicating the beginning of the sequence under '#0'.](.pxi-7931-50-17009-1010-11/171d1716cc2141e3f7b0a1e8be58c358db2ec97a776fdbb119377e83d50864ee.jpg) Figure 17: Handshaking operation (Scanner Advanced set in pulsating mode) ![Based on the provided image, here is an accurate and concise description of the timing diagram:\n\n**Labels and Blocks:**\n* **Top Trace:** Labeled **'Trigger In'**, showing a series of rectangular pulses.\n* **Middle Trace:** Labeled **'Scanner Advanced'**, showing a digital signal transitioning between high and low states.\n* **Bottom Trace:** Labeled **'Relay Status'**, showing a sequence of states: **'#0'**, **'Pattern #1'**, **'Pattern #2'**, **'Pattern #3'**, and **'#4'**.\n* **Timeline Label:** **'Operation Start'** is located at the bottom left.\n\n**Connections and Relationships:**\n* **Trigger In Annotations:**\n * The pulses are separated by gaps indicated by double slashes (**//**).\n * Three specific pulses are annotated with timing:\n * The first pulse has a width labeled **\$T_S\$** and a duration from 'Operation Start' labeled **\$T_{A1}\$**.\n * The second pulse has a width labeled **\$T_S\$** and a duration from 'Operation Start' labeled **\$T_{A2}\$**.\n * The third pulse has a width labeled **\$T_S\$** and a duration from 'Operation Start' labeled **\$T_A\$**.\n* **Signal Alignment:** Vertical dotted lines align events across the traces:\n * The rising edge of the **'Scanner Advanced'** signal aligns with the falling edge of the first **'Trigger In'** pulse.\n * The falling edge of the **'Scanner Advanced'** signal aligns with the falling edge of the second **'Trigger In'** pulse.\n * The second rising edge of the **'Scanner Advanced'** signal aligns with the falling edge of the third **'Trigger In'** pulse.\n* **Relay Status Transitions:**\n * The status changes from **'#0'** to **'Pattern #1'** when **'Scanner Advanced'** goes high.\n * It changes to **'Pattern #2'** when **'Scanner Advanced'** goes low.\n * It changes to **'Pattern #3'** when **'Scanner Advanced'** goes high again.\n * It changes to **'#4'** when **'Scanner Advanced'** goes low again.](.pxi-7931-50-17009-1010-11/0b9c60e8521939a1e2547ded51eef4d546ff430a9062d13483552bab3c6b09fc.jpg) Figure 18: Handshaking operation (Scanner Advanced set in toggling mode) Once the operation starts and has received a Trigger In signal, the switch module updates the relay pattern to that specified in the first entry of scanlist. TS is the default debounce time for a switch module, i.e. 5ms for PXI-7931. TAn is the user specified scan delay time in the scanlist entry, indicating the time between the relay being debounced and the exact moment that a measurement device takes a new measurement. The actual delay time would be the greater of the two times, to guarantee that measurement devices take measurements after the signal path is fully settled, and the relays switch as close as possible to their maximum operating speed. As the scan delay time elapses, the switch module generates Scanner Advanced signal to inform the measurement device to take a new measurement. After the measurement completes, the measurement device will generate another Trigger In signal to have the switch module update the relay pattern to that specified in the second entry of scanlist. The handshaking process will continue, until it reaches the end of the scanlist (if one-time scanning mode is selected), or when a software scan-abort command is received. # Connecting, Trigger and Synchronize with External DMM In this example, Agilent® 33401A 6-1/2 Digital Multimeter (DMM) is used to demonstrate signal connection for handshaking operation. The DMM provides two terminals on the rear panel for the handshaking operation process, Trig In and VM Comp. The Trig In connects to the Scanner Advanced output on switch module, while the VM Comp to Trigger In. If the terminal board is used, wire Trig In to TRG\_IN on terminal board, and the VM Comp to S\_ADV. Follow the instructions below to ensure the handshake functions properly: 1. Configure ADLINK PXI switch module’s Trigger In to rising-edge triggered, Scanner Advanced output in active-low pulsating mode with pulse width of at least 2us. 2. Configure the DMM to wait for external Trig In before a measurement, and generate VM Comp after a measurement. Arm the DMM to wait for the first trigger. 3. Setup the scanlist and auto-scan mode. The first entry in the scanlist should be set disable wait for the Trigger In, but enable Scanner Advanced output. Succeeding entries should enable both Trigger In and Scanner Advanced output. Download the’ scanlist to the switch module afterward. 4. Start auto-scan by sending scan start command to the switch module. ![**Blocks:**\n* ADLINK PXI Switch module\n* Agilent 33401A 6-1/2 DMM\n\n**Connections:**\n* **Trigger Input (TRG_IN)** connects to the left internal node of the ADLINK PXI Switch module.\n* **Scanner Advanced Output (S_ADV)** connects to the right internal node of the ADLINK PXI Switch module.\n* **Wiring** connects the left internal node of the ADLINK PXI Switch module to the top internal node of the Agilent 33401A 6-1/2 DMM.\n* **Wiring** connects the right internal node of the ADLINK PXI Switch module to the bottom internal node of the Agilent 33401A 6-1/2 DMM.\n* **External Trigger Input (Trig In)** connects to the top internal node of the Agilent 33401A 6-1/2 DMM.\n* **Measurement Complete (VM Comp)** connects to the bottom internal node of the Agilent 33401A 6-1/2 DMM.](.pxi-7931-50-17009-1010-11/1b02800fcc3a745e79fa1309de6dee23d4cb3eaa1d42f2dca9ebadd3277b65c6.jpg) Figure 19: Signal Connection between Switch Module and Agilent DMM For more information on scanlist configuration, scan mode setup, start, and stop functions of the auto-scanning process, please refer to the software programming users’ guide. # 4.4 Trigger Bus PXI specification defines eight bused-lines across slots in a segment. Users can route various trigger signal to synchronize multiple PXI instruments, and/or simplify field wiring across multiple ADLINK Switch Modules. On ADLINK Switch Modules, the trigger bus driver is disconnected from PXI trigger bus before users’ configuration. Figure 20 illustrates the available signal destinations for Trigger Bus[7..0]. Signal names in the solid-line boxes represent the external (physical) signals on connectors while signals in the dotted-line boxes represent the switch module’s internal signal. ![This diagram depicts a logic block (represented as a tall, vertical trapezoid) that aggregates multiple input signals into a single output bus.\n\n**Inputs:**\nOn the left side, the following labels connect to the left face of the central trapezoid:\n* **Software Trigger** (connected via a dashed line)\n* **Trigger In Signal** (connected via a solid line)\n* **Scanner Adv. Signal** (connected via a dashed line)\n* **AUX (3...2)** (connected via a solid line)\n* **Star Trigger In** (connected via a solid line)\n* **WDT Overflow** (connected via a dashed line)\n* **SHDNn** (connected via a solid line)\n\n**Output:**\nA single solid line extends from the right side of the central trapezoid to a block labeled **Trigger Bus(7..0)**.](.pxi-7931-50-17009-1010-11/dfd11c8d13c9b4541b59c2761b24274f6717ead584aee51c7e6fc84f6ced1943.jpg) Figure 20: Available signal sources for Trigger Bus[7..0] # 4.5 Auxiliary Digital I/O The eight auxiliary digital I/O lines on ADLINK Switch Modules provide versatility to users’ control applications. Each digital I/O line can be input, output or tri-stated. When in output mode, users can still read back the actual logiclevel on the I/O line. All digital lines are pulled-up to 5V with 10k ohm input resistance. Note that AUX[2..0] are dual function pins, driving these pins while enabling handshaking or emergency shutdown functions, may falsely trigger the Switch Module or external instruments. ![Based on the provided image, here is the accurate and concise description of the blocks and connections:\n\n**Labeled Blocks:**\n* **DO** (Hexagonal shape)\n* **DI** (Hexagonal shape)\n* **Tri-state Control** (Text label)\n* **Bus-Switch and Protection Circuit** (Shaded rectangular box)\n* **10kΩ** (Rectangular box)\n* **5VDC** (Text label)\n* **AUX Pin** (Hexagonal shape)\n\n**Connections:**\n* **DO** connects to the left side of a triangular buffer symbol.\n* **Tri-state Control** connects to the top vertex of the triangular buffer symbol.\n* The right side of the triangular buffer symbol connects to the left side of the **Bus-Switch and Protection Circuit**.\n* A wire labeled **Feedback from output** originates from **DI**, runs right and up, and connects to the line exiting the right side of the triangular buffer (just before the Bus-Switch).\n* The right side of the **Bus-Switch and Protection Circuit** connects to the left side of **AUX Pin**.\n* A vertical line connects the top of the **Bus-Switch and Protection Circuit** to the bottom of the **10kΩ** resistor.\n* The top of the **10kΩ** resistor connects to **5VDC**.\n* The bottom of the **10kΩ** resistor connects to the horizontal line between the **Bus-Switch and Protection Circuit** and **AUX Pin**.](.pxi-7931-50-17009-1010-11/952ee838c9c314f1f2ff721785b05cb9d60a00f0dd9f33bfcef47dd5527b7064.jpg) Figure 22: Auxiliary Digital I/O Function Block # 4.6 Hot-Swap The Switch Module can be hot-swapped during hardware failure in noninterruptible or high-availability systems where system shutdown is not an option. PXI-7931 incorporates an onboard hot-swap control mechanism. However the extent of the hot-swap functionality support depends on the operating system and the PXI platform. Microsoft Embedded $\mathsf { X P } ^ { \circledast }$ supports the native hot-swap function. The operating system automatically releases system resources when a switch module is extracted and recognizes the new device. To remove a switch module, first release the screws on the front panel then push down the red latch on the ejector. When the blue LED turns on, the Switch module is ready to be removed by fully pushing down the ejector. To insert another switch module, align the module’s edge with the card guide in the PXI chassis. Slide the switch module into the chassis, until there is resistance from the PXI connector. Push the ejector up and fully insert the switch module into the chassis, a click should be heard from the ejector latch. The blue LED on the front panel of the switch module will switch off when it is ready for operation. Tighten the screws on the front panel. Note: Microsoft Windows $2 0 0 0 ^ { \circledast }$ does not natively support hot-swap however, PXI-7931 can be hot-swapped by manual control via an additional hot-swap driver. For the hot-swap driver on Windows 2000 and other operating systems such as Linux, VxWorks, etc., please contact ADLINK for more information. # 4.7 Emergency Shutdown In safety-critical applications, users can enable the emergency shutdown function on PXI Switch Module, to manually set the relay pattern to preset state. To access this function, users must first configure the emergency shutdown function by windows API. Generally the trigger source is on the front panel and connected to a push button, which pulls the SHDNn pin to logic-low when activated. When multiple PXI Switch modules are installed in a PXI chassis, the trigger source can be routed through the PXI Trigger Bus and eliminate field wiring across multiple devices. Figure 23 illustrates available trigger sources for emergency shutdown. Signal names in the solid-line boxes represent the external (physical) signal on connectors and signals in the dotted-line boxes represent the switch module’s internal signal. ![The diagram depicts a logic flow with three distinct sections:\n\n1. **Inputs (Left):** A rectangular area contains three stacked labels:\n * 'AUX2/SHDNn'\n * 'Trigger Bus'\n * 'Star Trigger In'\n Lines extend from each label to the right. Notably, the line from 'AUX2/SHDNn' passes through a small circle (a buffer or inverter symbol) before entering the next stage.\n\n2. **Processing Block (Center):** The three lines converge into a vertical trapezoidal block.\n\n3. **Output (Right):** A single line exits the right side of the trapezoidal block and connects to a dashed rectangular block labeled 'Shutdown Trigger'.](.pxi-7931-50-17009-1010-11/60040ee3309771bdacb77762c477bd077973c1efdbb1b5147b9b169d30255b00.jpg) Figure 23: Available trigger sources for emergency shutdown The default relay pattern for emergency shutdown is All-Off on PXI-7931; users can change the pattern by Windows API. Upon receiving the emergency shutdown trigger, the Switch Module enters shutdown mode, and the relay pattern is switched to the preset state. If the Switch Module is in Auto-scan mode, the updating process would be stopped immediately; in Direct Update mode where the switch module will not accept any further update instructions. To leave emergency shutdown mode, users must call adlSwitch\_Recovery in Windows API. The relay pattern would stay the same as they would in the emergency shutdown mode, and the scanlist (if set) being rewound to the first entry. Note the auxiliary digital I/O function pin AUX2 shares the SHDNn pin; driving AUX2 to logic-low while the emergency shutdown function is enabled. It will falsely trigger the Switch Module to enter shutdown mode. This function is disabled by default. For more information, please refer to the software programming users’ guide. # 4.8 Watchdog Timer In safety-critical applications, users can enable the watchdog timer function on PXI Switch Module to automatically set the relay pattern to preset state, in case the operating system or PXI controller crashes. To access this function, users must first configure the watchdog timer overflow trigger source by windows API. Generally the trigger source would come from the onboard 32-bit watchdog timer. When multiple ADLINK PXI Switch modules are installed in a PXI chassis, the trigger source can be routed through the PXI Trigger Bus and eliminate redundant watchdog timer setting on multiple devices. Figure 24 illustrates the available trigger sources for watchdog timer overflow. Signal names in the solid-line boxes represent the external (physical) signal on connectors and signals in the dotted-line boxes represent the switch module’s internal signal. ![The flowchart displays a central processing block connected to inputs on the left and an output on the right.\n\n**Labeled Blocks:**\n* **Int. WDTimer**: Located at the top left. It is a rectangular block with a dashed outline on its top and right side.\n* **Trigger Bus**: Located in the middle left. It is a rectangular block with a solid outline.\n* **Star Trigger In**: Located at the bottom left. It is a rectangular block with a solid outline.\n* **WDT Overflow**: Located on the far right. It is a block with a dashed outline shaped like an arrow pointing to the right.\n\n**Connections:**\n* Three horizontal lines connect the three left blocks (**Int. WDTimer**, **Trigger Bus**, and **Star Trigger In**) to the left side of a central, unlabeled trapezoidal block. The connection from the top block (**Int. WDTimer**) appears to be part of its dashed outline, while the others are solid lines.\n* A single horizontal line connects the right side of the central trapezoidal block to the left side of the **WDT Overflow** block.](.pxi-7931-50-17009-1010-11/3daebb2520780737774960f2b0ed036017a7a5a35906507dd26e27727038c906.jpg) Figure 24:.Available trigger sources for watchdog timer overflow The watchdog timer overflow interval can be programmed through Windows API. After enabling the watchdog timer, users must periodically reset the timer by software command. If the timer is not being reset within the specified interval, the switch module will generate an overflow signal and set the relay pattern to the one specified by users. This function is disabled by default. For more information, please refer to the software programming users’ guide. # Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully: 1. Before using ADLINK’s products please read the user manual and follow the instructions exactly. 2. When sending in damaged products for repair, please attach an RMA application form. 3. All ADLINK products come with a two-year guarantee, repaired free of charge. The warranty period starts from the product’s shipment date from ADLINK’s factory. Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers’ warranty. End users requiring maintenance services should contact their local dealers. Local warranty conditions will depend on local dealers. 4. This warranty will not cover repair costs due to: a. Damage caused by not following instructions. b. Damage caused by carelessness on the users’ part during product transportation. c. Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. d. Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals. e. Damage caused by leakage of battery fluid. f. Damage from improper repair by unauthorized technicians. g. Products with altered and/or damaged serial numbers. h. Other categories not protected under our guarantees. 5. Customers are responsible for shipping costs to transport damaged products to our company or sales office. 6. To ensure the speed and quality of product repair, please download a RMA application form from our company website: www.adlinktech.com. Damaged products with attached RMA forms receive priority. For further questions, please contact our FAE staff. ADLINK: service@adlinktech.com [🔗 Link to the original document](.pxi-7931-50-17009-1010-11/pxi-7931-50-17009-1010-11.pdf)