# PXI-9820

2-CH, 65MS/s, 14-Bit Digitizer with SDRAM

User's Guide

©Copyright 2004 ADLINK Technology Inc.

All Rights Reserved.

Manual Rev. 1.00 : September 21, 2004

Part No: 50-17015-100

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

PXI is registered trademarks of PXI Systems Alliance. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK TECHNOLOGY INC. If you need any help or service, please contact us.

<table><tr><td colspan="4">ADLINK TECHNOLOGY INC.</td></tr><tr><td>Web Site</td><td colspan="3">http://www.adlinktech.com</td></tr><tr><td>Sales &amp; Service</td><td colspan="3">Service@adlinktech.com</td></tr><tr><td>TEL</td><td>+886-2-82265877</td><td>FAX</td><td>+886-2-82265717</td></tr><tr><td>Address</td><td colspan="3">9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan</td></tr></table>

Please email or FAX your detailed information for prompt, satisfactory, and consistent service.

<table><tr><td colspan="4">Detailed Company Information</td></tr><tr><td>Company/Organization</td><td colspan="3"></td></tr><tr><td>Contact Person</td><td colspan="3"></td></tr><tr><td>E-mail Address</td><td colspan="3"></td></tr><tr><td>Address</td><td colspan="3"></td></tr><tr><td>Country</td><td colspan="3"></td></tr><tr><td>TEL</td><td></td><td>FAX</td><td></td></tr><tr><td>Web Site</td><td colspan="3"></td></tr><tr><td colspan="4">Questions</td></tr><tr><td>Product Model</td><td colspan="3"></td></tr><tr><td>Environment</td><td colspan="3">OS:Computer Brand:M/B: CPU:Chipset: BIOS:Video Card:NIC:Other:</td></tr><tr><td>Detail Description</td><td colspan="3"></td></tr><tr><td>Suggestions for ADLINK</td><td colspan="3"></td></tr></table>

# Table of Contents

# Chapter 1 Introduction ..........

1.1 Features . .2
1.2 Applications . .2
1.3 Functional Block Diagram . .3
1.4 Specifications ... .. 6

# Chapter 2 Installation ......... ...... 11

2.1 Contents of Package .... ... 11
2.2 Unpacking.. ..12
2.3 Mechanical Drawing ..... .13
2.4 Analog Input Impedance Setting . .14
2.5 Installation .. .15
2.6 Software Support.. .. 17

# Chapter 3 Operation Theory .......... ..... 19

3.1 Block Diagram .... ..19
3.2 Analog Input Signal Source Control .. ..20
3.3 A/D Sampling rate and Timebase Control.. .. 20
3.4 Trigger Sources.. .. 24
3.5 Trigger Modes ... ..27
3.6 Trigger Signals Exporting .. ..31
3.7 Data Transfers.. . 32
3.8 AI Data Format .. .. 33
3.9 Synchronizing Multiple Devices... .. 33
3.10 Auto-calibration .38

# Warranty Policy............. ..... 39

# How to Use This Guide

This user’s guide is designed to help users understand and operate the PXI-9820. It is divided into three chapters:

# Chapter 1 Introduction

Gives an overview of product features, applications, specifications and a functional block diagram.

# Chapter 2 Installation

Describes how to install the PXI-9820.

# Chapter 3 Operation Theory

Describes how to operate the PXI-9820, including the control and setting of signal, timebase, and trigger sources; trigger modes; data transfers; synchronizing multiple modules; and auto-calibration.

![1](.pxi-9820-manual-4/7ab2ae8ef99aeabc189840f255f82f79479fbfc3ac204c3389f6ecf9c883bd15.jpg)

# Introduction

The ADLINK PXI-9820 is a 65MS/s, high-resolution PXI digitizer with deep SODIMM SDRAM memory that features flexible input configurations, including programmable input ranges and user-selectable input impedance. With deep onboard acquisition memory, the PXI-9820 is not limited by the PCI’s 132MB/s bandwidth, and can record waveforms for extended periods of time. The PXI-9820 is ideal for high-speed waveform capturing such as radar, ultrasound, software radio, and other signal digitizing applications needing large amounts of memory for data storage. PXI-9820 uses the PXI trigger bus to send and receive trigger and timebase signals to and from other devices. In additional, the PXI-9820 can phase-lock the reference clock from the PXI backplane or from an external connector for better synchronization capabilities.

This chapter gives an overview of the PXI-9820 high speed digitizer, and covers the following topics:

Features

Applications

Functional Block Diagram

Specifications

# 1.1 Features

• PXI specifications Rev. 2.1 compliant
• 3U Eurocard form factor, CompactPCI compliant (PICMG 2.0 R3.0)
• 14-bit A/D resolution
• Up to 60MS/s sampling rate per channel with internal timebase
• Up to 65MS/s sampling rate per channel with external timebase
Up to 130MS/s sampling rate using “ping pong” mode for single-channel acquisition
• 2-CH simultaneous-sampled single-ended analog inputs
• Programmable input ranges of ±1V and ±5V
• User-selectable input impedance of 50Ω or high input impedance
• >30MHz -3dB bandwidth
• Up to 512MB on-board SODIMM SDRAM
• 2-CH synchronous digital inputs
• Scatter-gather DMA data transfers
• Analog and digital triggering
• Fully auto calibration
• Multiple modules synchronization through PXI trigger bus
• On-board phase-lock loop circuit

# 1.2 Applications

• Software Radio / Wireless Communication
• Radar / Sonar / Lidar
• Ultrasound
• Imaging
• Military / Laboratory / Research

# 1.3 Functional Block Diagram

The following topics overview the PXI-9820 main features as shown in the functional block diagram below.

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   External Digital Trigger and Clock Input\n*   Clock Generation\n*   PXI Trigger Bus\n*   AI0 Analog Circuitry\n*   AD Converter (appears twice)\n*   AI1 Analog Circuitry\n*   FPGA Logic\n*   PCI Controller\n*   SD RAM\n\n**Connections:**\n*   **AI0 Analog Circuitry** connects to the top **AD Converter** (arrow pointing right).\n*   **AI1 Analog Circuitry** connects to the bottom **AD Converter** (arrow pointing right).\n*   **External Digital Trigger and Clock Input** connects via an arrow pointing right, which then leads down into **FPGA Logic**.\n*   **Clock Generation** connects via an arrow pointing down into **FPGA Logic**.\n*   **PXI Trigger Bus** connects via an arrow pointing left (towards Clock Generation) and arrows pointing down into **FPGA Logic**.\n*   The top **AD Converter** connects via an arrow pointing down and then right into **FPGA Logic**.\n*   The bottom **AD Converter** connects via an arrow pointing right into **FPGA Logic**.\n*   **PCI Controller** connects via an arrow pointing up and right into **FPGA Logic**.\n*   **FPGA Logic** is connected bidirectionally to **SD RAM** (indicated by a double-headed arrow).](.pxi-9820-manual-4/2f689c4956d8dc8c502772ef376b2e673cc2d4d06f7ee5fb20fa59df41ba2f83.jpg)

Figure 1.1 PXI-9820 Functional Block Diagram

# 1.3.1 Analog Input

The PXI-9820 features two analog input channels. Signal bandwidth of each channel exceeds 30MHz, satisfying the Nyquist sampling theory. The input ranges are programmable as either ±5V or ±1V. The 14-bit A/D resolution makes the PXI-9820 ideal both for time-domain and frequency-domain applications.

# 1.3.2 Acquisition System

The PXI-9820 uses a pair of 65MS/s, 14-bit pipeline ADCs to digitize input signals. It provides an internal 60MHz timebase for data acquisition. The maximum real-time sampling rate is 60MS/s with internal timebase and up to 65MS/s with external timebase. By using the “ping pong” mode, the sampling rate is up to 120MS/s with internal timebase or 130MS/s with external timebase.

# 1.3.3 Acquisition Memory

The PXI-9820 supports SODIMM SDRAM ranging from 128MB to 512MB. Digitized data is stored in the on-board SDRAM before being transferred to host memory. The PXI-9820 uses scatter-gather bus mastering DMA to move data to the host memory. If the data throughput from the PXI-9820 is less than the available PCI bandwidth, the PXI-9820 will bypass the

SDRAM and use the on-board 3k-sample FIFO to achieve real-time transfer directly to the host memory.

# 1.3.4 Triggering

The PXI-9820 features flexible triggering functions, such as analog and digital triggering. The analog trigger features programmable trigger thresholds on rising or falling edges of both input channels. The 5V/TTL digital trigger comes from the external SMB connector, PXI trigger bus or PXI\_STAR for synchronizing multiple devices.

Post-trigger, pre-trigger, delay-trigger and middle-trigger modes are available to acquire data around the trigger event. The PXI-9820 also features repeated trigger acquisition to acquire data in multiple segments coming with successive trigger events at extremely short rearming intervals.

![Based on the provided diagram, here is the accurate description of the labeled blocks and connections:\n\n**Top Section (Waveforms)**\n*   **Left:** A waveform labeled **'Analog'** is shown. Above it, a left-pointing arrow is labeled **'+trigger'** and a right-pointing arrow is labeled **'-trigger'**.\n*   **Right:** A square wave labeled **'Digital'** is shown. Above it, a left-pointing arrow is labeled **'+trigger'** and a right-pointing arrow is labeled **'-trigger'**.\n\n**Middle Section**\n*   A label **'Trigger Event'** is followed by a blue arrow pointing to the right. A vertical line extends downward from this arrow through the timeline below.\n\n**Bottom Section (Timeline Bars)**\nFour rows of horizontal bars illustrate different trigger modes relative to the vertical trigger line:\n*   **Delay-Trigger:** A bar starts after the vertical line. It consists of a dashed segment labeled **'M'** followed by a solid segment labeled **'N'**.\n*   **Pre-Trigger:** A solid bar segment labeled **'N'** is positioned entirely to the left of the vertical line.\n*   **Middle-Trigger:** A bar spans across the vertical line. It has a segment labeled **'M'** to the left and a segment labeled **'N'** to the right.\n*   **Post-Trigger:** A solid bar segment labeled **'N'** is positioned entirely to the right of the vertical line.](.pxi-9820-manual-4/47838bb726f38818b9853fa44ade21f8d38b1d5503529c46f8afe32e27cff009.jpg)

Figure 1.2 PXI-9820 Trigger Modes

# 1.3.5 Multiple-Instrument Synchronization

To achieve multiple-instrument synchronization, PXI-9820 routes timing and trigger signals between one or more PXI-9820 devices by the PXI trigger bus. Users can assign timebase or trigger signals to a specific PXI trigger bus[0:7] via software, providing better flexibility for multiple devices synchronization. The PXI-9820 also adopts PXI\_STAR signal for better synchronization performance. Both trigger signals and timebase clock can be transferred to 13 peripheral slots through the PXI\_STAR signal on slot 2.

The reference clock is used in the PXI-9820 phase-lock loop (PLL) circuit to synchronize the timebase clock to the reference. The PXI-9820 can accept a reference clock the CLK IN on the front panel as well as from PXI\_CLK10. The reference clock should be a fixed and stable 10MHz clock.

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Blocks:**\n*   **PLL** (Orange square)\n*   **MUX** (Tall orange rectangle)\n*   **CLK IN** (Small orange switch symbol)\n\n**Connections:**\n*   **PXI 10 MHz Reference Clock** connects to **PLL**.\n*   **External 10 MHz** connects to **PLL**.\n*   **External Clock Input** connects to **MUX**.\n*   **PLL** connects to **MUX**.\n*   **Trigger Bus** connects to **MUX**.\n*   **Star Trigger** connects to **MUX**.\n*   **MUX** outputs to **Timebase**.](.pxi-9820-manual-4/c29981c7576e4ba1e0c4a358fead4fbb9dc401e9556565fd8cf3b5e69f248339.jpg)

Figure 1.3 PXI-9820 Timebase Control

# 1.3.6 Synchronous Digital Input

The PXI-9820 features two high-speed digital input lines. User can clock in digital data synchronous to the analog input timebase clock. Viewing analog and digital correlated operations is effortless.

![Based on the provided flowchart, here is the description of the labeled blocks and connections:\n\n**Labeled Blocks:**\n*   **ADC**\n*   **16-bit Register**\n\n**Connections (Data Flow):**\n*   **Digital Input:** A line labeled **'Digital'** and **'SDI (1-bit)'** enters the top of the **16-bit Register**.\n*   **Analog Input:** A line labeled **'Analog'** enters the **ADC** block.\n*   **ADC Output to Register:** Two lines originate from the **ADC** and enter the bottom of the **16-bit Register**:\n    *   One line is labeled **'Out-of-range Indicator (1-bit)'**.\n    *   One line is labeled **'Converted Data (14-bit)'**.\n*   **Register Output:** A line labeled **'Mixed Data'** exits the right side of the **16-bit Register**.](.pxi-9820-manual-4/b669a94aa52d14c9262a05879f5dfc575263a7c7979945eb5779f22e09f189f8.jpg)

Figure 1.4 PXI-9820 Synchronous Digital Inputs

# 1.3.7 Auto Calibration

The auto-calibration function of the PXI-9820 is performed with trim DACs to calibrate offset and gain errors of the analog input channels. Once the calibration process is complete, the calibration constant will be stored in EEPROM. These values are loaded and used as needed by the board. Because all the calibration is conducted automatically by software commands, users do not have to adjust trimpots to calibrate the boards.

![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Labeled Blocks and Components:**\n*   **Square Switch Block:** A square box containing three orange dots connected in a 'Y' shape.\n*   **Voltage Reference Rectangle:** A light orange rectangular block located below the switch block.\n*   **PGA Triangle:** A triangle pointing to the right, labeled 'PGA' above it.\n*   **Trim ADC Trapezoid:** A trapezoidal arrow shape pointing to the right, labeled 'Trim ADC' below it.\n*   **Yellow Output Block:** A yellow square containing a white triangle pointing right.\n\n**Text Labels:**\n*   'AI CH'\n*   'PGA'\n*   'Voltage Reference'\n*   'Trim ADC'\n\n**Connections:**\n*   **AI CH to Switch:** A horizontal line connects the text 'AI CH' to the left side of the square switch block.\n*   **Switch to PGA:** A horizontal line connects the right side of the square switch block to the left side of the 'PGA' triangle.\n*   **Switch to Voltage Reference:** A vertical line connects the bottom of the square switch block to the top of the 'Voltage Reference' rectangle.\n*   **Voltage Reference to Trim ADC:** A horizontal line connects the right side of the 'Voltage Reference' rectangle to the left side of the 'Trim ADC' trapezoid.\n*   **Trim ADC to PGA:** A vertical arrow points upward from the top of the 'Trim ADC' trapezoid to the bottom of the 'PGA' triangle.\n*   **PGA to Output:** A horizontal line connects the right side of the 'PGA' triangle to the left side of the yellow output block.](.pxi-9820-manual-4/3250d6e7b9af3d12402d7632d22349a55371a4cff2235a422aff0cef087b8b3b.jpg)

Figure 1.5 PXI-9820 Auto Calibration

# 1.4 Specifications

# Analog Input

• Number of channels: 2 simultaneous-sampled single-ended
• Resolution: 14 bits
• Max sampling rate:
60MS/s per channel with internal timebase 65MS/s per channel with external timebase 120MS/s using “ping pong” mode on CH0 with internal timebase 130MS/s using “ping pong” mode on CH0 with external timebase
• On-board memory size:
SODIMM SDRAM: 128MB standard, up to 512MB FIFO buffer: 3056 samples
• Bandwidth (-3 dB): 30MHz minimum, 42MHz typical
• Passband flatness (typical, referenced at 250 kHz):
±0.4dB, DC to 15 MHz ±1dB, 15 to 25 MHz
• Input signal ranges:
±5V, ±1V (software programmable)
• Input coupling: DC
• Overvoltage protection:

<table><tr><td>Range</td><td>Overvoltage protection</td></tr><tr><td>±5V</td><td>±14V</td></tr><tr><td>±1V</td><td>±5V</td></tr></table>

• Input impedance:

50Ω (default), 1.5MΩ (soldering selectable)

• System Noise: (typical)

<table><tr><td>Range</td><td>Noise (LSBrms)</td></tr><tr><td>±5V</td><td>1.21</td></tr><tr><td>±1V</td><td>1.68</td></tr></table>

• Crosstalk: &lt; - 80dB, DC to 1MHz
• Total Harmonic Distortion (THD)\*: -75 dB
• Signal-to-noise ratio (SNR)\*:

&lt;table&gt;<tr><td>Range</td><td>SNR (dB)</td></tr><tr><td>±5V</td><td>69</td></tr><tr><td>±1V</td><td>63.5</td></tr></table>

• Spurious-free dynamic range (SFDR)\*: 76.9dB

\*Measured using 200kHz sine wave input with amplitude of 95% of full scale at 60MS/s

# Synchronous Digital Input

• Number of channels: 2
• Compatibility: 5V/TTL
• Digital logic levels

Input high voltage: 0V to 0.8V

Input low voltage: 2.0V to 5V

• Maximum input overload: -0.5V to +7V
• Hysteresis voltage: 0.7V minimum

# Timebase System

• Sources:

\- Internal, on-board 60MHz:

Internal sample clock frequency: 60 MHz / n, 1≦ n ≦224-1

Timebase accuracy: ±25 ppm

Jitter: &lt; 6ps

\- External, CLK IN sine wave:

Connector: front panel SMB connector (CLK IN)

Impedance: 50Ω

Coupling: AC

Input amplitude: 1Vpp to 2Vpp

Overvoltage protection: 2.5Vpp

Frequency range:

Ping-pong mode: 25MHz - 65MHz

Others: 500kHz - 65MHz

# - External, PXI Trigger Bus[0:7]:

Source selection: from one of PXI Trigger bus[0:7], software selectable

Compatibility: 5V/TTL

Maximum input overload: -0.5V to +5.5V

Frequency range:

Ping-pong mode: 25MHz - 65MHz

Others: 500kHz - 65MHz

# - External, PXI\_STAR

Source selection: software selectable

Compatibility: 5V/TTL

Maximum input overload: -0.5V to +7.0V

Frequency range:

Ping-pong mode: 25MHz - 65MHz

Others: 500kHz - 65MHz

# • Timebase clock exporting

Destinations: PXI\_STAR[0:12], PXI Trigger Bus[0:7]

# PLL Reference Clock

Sources: PXI 10MHz reference (backplane, PXI\_CLK10), external 10MHz reference (front panel SMB, CLK IN)
• Frequency requirement: 10MHz ± 50ppm

# - External 10MHz reference

Connector: front panel SMB connector (CLK IN)

Impedance: 50Ω

Coupling: AC

Input amplitude: 1Vpp to 2Vpp

Overvoltage protection: 2.5Vpp

# - PXI 10MHz

Connector: from PXI backplane

Compatibility: 5V/TTL

Maximum input overload: -0.5V to +5.5V

# Triggering

Sources: software, analog trigger, external digital trigger (TRG IO), PXI\_STAR, PXI Trigger Bus[0:7]

# - Analog triggering

Sources: CH0 and CH1

Slope: rising/falling

Coupling: DC

Trigger sensitivity: 256 steps in full-scale voltage range

Hysteresis: 1.5% of the full range

Offset error: 1.25% of the full range

# - Digital triggering

Connectors: front panel SMB connector (TRG IO)

Slope: rising/falling

Compatibility: 5V/TTL

Minimum pulse width: 10ns

# - PXI\_STAR

Slope: rising/falling

Compatibility: 5V/TTL

Minimum pulse width: 10ns

# - PXI Trigger Bus[0:7]

Source: software selectable from one of PXI trigger bus[0:7]

Compatibility: 5V/TTL

Minimum pulse width: 10ns

• Modes: pre-trigger, middle-trigger, post-trigger, delay-trigger
• Repeated trigger rearming interval: 2 cycles of timebase
• Pre-trigger depth: 128MB to 512MB, depending on memory size
• Post-trigger depth: 128MB to 512MB, depending on memory size
• Trigger Exporting

Destinations: Front panel SMB connector (TRG IO), PXI Star Trigger[0:12], PXI Trigger Bus[0:7]

# Calibration

• Recommended warm-up time: 15 minutes
• On-board calibration reference:

Level: 5.000V

Temperature coefficient: ±2ppm/°C

Long-term stability: 6ppm/1000Hr

# General Specifications

• Dimensions: (not including connectors)

Single 3U PXI module, 100mm by 160mm

• I/O connector:

BNC x 2 for analog inputs(CH0 & CH1)

SMB x 4 for external timebase (CLK IN), external digital trigger

(TRG IO) and synchronous digital input 0 & 1(SDI0, SDI1)

• PCI signaling environment:

Supports a 32-bit 3.3V or 5V PCI bus

# • Operating environment:

Ambient temperature: 0 to 50°C

Relative humidity: 5% to 95% non-condensing

# • Storage environment :

Ambient temperature: -20 to 80°C

Relative humidity: 5% to 95% non-condensing

# • Power requirement: (typical)

&lt;table&gt;<tr><td>Power Rail</td><td>Current (mA)</td></tr><tr><td>5V</td><td>900</td></tr><tr><td>12V</td><td>305</td></tr><tr><td>3.3V</td><td>360 (with 128MB onboard SDRAM memory)500 (with 512MB onboard SDRAM memory)</td></tr></table>

# 2

# Installation

This chapter describes how to install the PXI-9820. Please read the contents of the package and unpacking information carefully before you install the module.

# 2.1 Contents of Package

Check the shipping carton for any visible damage. If the shipping carton and contents are damaged, notify the dealer for a replacement. Retain the shipping carton and packing materials for inspection by the dealer. Remember to obtain authorization before returning any products to ADLINK.

Check the following in the package. If there is any missing item, contact your dealer:

This User’s Guide
Software Installation Guide
• ADLINK All-In-One CD

PXI-9820 2CH, 65MS/s, 14-Bit Digitizer with SDRAM

# 2.2 Unpacking

Your PXI-9820 module contains electro-static sensitive components that can be easily be damaged by static electricity.

Therefore, the module should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

After opening the shipping carton, extract the module and place it only on a grounded anti-static surface with component side up.

Again, inspect the module for damage. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

Note: DO NOT APPLY POWER TO THE MODULE IF IT HAS BEEN DAMAGED.

# 2.3 Mechanical Drawing

![CLK IN\nTRG IO\nSDI0\nSDI1\nCH0\nCH1\nSO-DIMM](.pxi-9820-manual-4/39c6938e939215d48dd73ad81f3571becf1d8b3b8c7c548423cbda8365e1a6b3.jpg)

Figure 2.1 PXI-9820 Mechanical Drawing

The ADLINK PXI-9820 module is packaged in a Eurocard form factor compliant with PXI Specifications measuring 160mm in length and 100mm in height (not including connectors). The connector types and functions are described as follows.

CLK IN: The SMB connector is a 50Ω, AC-coupled external timebase input or external 10MHz reference clock input.

TRG IO: The SMB connector is for external digital trigger input or output.

SDI0: The SMB connector is for synchronous digital input channel 0.

SDI1: The SMB connector is for synchronous digital input channel 1.

CH0: The BNC connector is for attaching the analog input signal to measure on channel 0.

CH1: The BNC connector is for attaching the analog input signal to measure on channel1.

SO-DIMM: The SO-DIMM connector is for plugging the 144-pin SDRAM SODIMM.

# 2.4 Analog Input Impedance Setting

CH0 and CH1 input impedance can be set to 50Ω or 1.5MΩ by soldering gap switches J6 and J7 on the backside of the PXI-9820. The location of J6, J7 and the corresponded input impedance setting are shown in Fig. 2.2 and Table 2.1. The default setting is 50Ω input impedance.

<table><tr><td>J6</td><td>CH0 Input Impedance</td></tr><tr><td>Open</td><td>High (1.5MΩ)</td></tr><tr><td>Close(Default)</td><td>Low (50Ω)</td></tr></table>

<table><tr><td>J7</td><td>CH1 Input Impedance</td></tr><tr><td>Open</td><td>High (1.5MΩ)</td></tr><tr><td>Close(Default)</td><td>Low (50Ω)</td></tr></table>

Table 2.1: Location of solder switches
![Technical line drawing of a mechanical assembly with no visible text or symbols](.pxi-9820-manual-4/1aa0347bf5f480f0079fe561596f36afe59849fbb9dc8fe57d318a054cf8ff98.jpg)

Figure 2.2: Location of solder switches

# NOTE:

If the high input impedance 1.5MΩ is selected, the output impedance of the signal sources should be kept low to avoid of the offset voltage caused by the input bias current, which is 2μA min. and 25μA max.

# 2.5 Installation

Windows will find the new PXI-9820 module automatically. If this is the first time the PXI-9820 is running on your Windows system, please refer to the following step-by-step installation procedures.

# 2.5.1 Software Installation

For Windows 98/2000/XP users:

1. Insert the ADLINK ALL-In-One CD. Under X:\Software\WD-DASK\W98nt2k\DISK1, you will find SETUP.EXE (X is the drive letter of your CDROM).
2. Execute SETUP.EXE and follow the installation shield to complete WD-DASK installation.
3. When you complete the software installation, turn off your system and follow the hardware installation guide to insert PXI-9820 into your system.

# 2.5.2 Hardware Installation/Removal Procedures

The PXI connectors are rigid and require careful handling when inserted and removed. Improper handling of modules can easily damage the backplane. To insert the ADLINK PXI-9820 module into a PXI chassis, please follow the procedures below.

1. Turn off your system
2. Align the module’s edge with the card guide in the PXI chassis.
3. Slide the module into the chassis, until resistance is felt from the PXI connector.
4. Push the ejector upwards and fully insert the module into the chassis
5. Once inserted, a “click” can be heard from the ejector latch.
6. Tighten the screw on the front panel.
7. Power on

To remove the module, reverse steps 2 through 6 above.

# 2.5.3 Installation check

When you complete both software and hardware installations, you can check the list in device manager to confirm whether PXI-9820 is working properly. In the device manager, look for a device named “PCI9820 Device” under Nu-DAQ Boards. If it is found, installation was successful.

![Device Manager\nAction View\nDAQSTREAMING\nComputer\nDisk drives\nDisplay adapters\nFloppy disk controllers\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nNetwork adapters\nNuDAQ Boards\nPCI9820 Device\nPorts (COM & LPT)\nSCSI and RAID controllers\nSound, video and game controllers\nStorage volumes\nSystem devices\nUniversal Serial Bus controllers](.pxi-9820-manual-4/79ff371091b6bb42a162719d647b0d1ae4614fa9db6c10990e759803015c215c.jpg)

# 2.6 Software Support

ADLINK provides versatile software drivers and packages for users’ differing approaches to building up a system. ADLINK not only provides programming libraries such as DLLs for most Windows based systems, but also drivers for other software packages such as LabVIEW® .

All software options are included in the ADLINK All-In-One CD. Non-free software drivers are protected with licensing codes. Without the software code, you can install and run the evaluation version for two hours for trial/demonstration purposes. Please contact ADLINK dealers to purchase the formal license.

# 2.6.1 Programming Library

For customers who are writing their own programs, we provide function libraries for many different operating systems, including:

WD-DASK: Includes device drivers and DLLs for Windows 98, Windows NT, and Windows 2000. DLL is a binary compatible across Windows 98, Windows NT, and Windows 2000. All applications developed with WD-DASK are compatible across Windows 98, Windows NT, and Windows 2000. The developing environment can be VB, VC++, Delphi, BC5, or any Windows programming language that allows calls to a DLL. The function reference manual of WD-DASK are in the All-In-One CD (\Manual\_PDF\Software\WD-DASK).

WD-DASK/X: Includes device drivers and shared libraries for Linux. The developing environment can be Gnu C/C++ or any programming language that allows linking to a shared library. The function reference manual of WD-DASK/X are in the All-In-One CD (\Manual\_PDF\Software\WD-DASK).

# 2.6.2 DAQ-LVIEW PnP: LabVIEW® Driver

DAQ-LVIEW PnP contains the VIs, which are used to interface with National Instrument’s LabVIEW® software package. DAQ-LVIEW PnP supports Windows 98/NT/2000. The LabVIEW® driver is shipped free with the device. Users can install and use them without a license. For detailed information about DAQ-LVIEW PnP, please refer to the user’s guide and function reference manual in the All-In-One CD (\Manual\_PDF\Software\DAQ-LVIEW PnP).

# 2.6.3 WD-OCX: ActiveX Controls

We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use WD-OCX ActiveX control component libraries for developing applications. WD-OCX is designed for Windows 98/NT/2000. For more detailed information about WD-OCX, please refer to the function reference manual in the All-In-One CD (\Manual\_PDF\Software\WD-OCX)

In addition, ADLINK supplies ActiveX control software DAQBench.

DAQBench is a collection of ActiveX controls for measurement or automation applications. With DAQBench, users can easily develop custom interfaces to display data, analyze acquired data or data received from other sources, or integrate with popular applications or other data sources. For more detailed information about DAQBench, please refer to the All-In-One CD (\Manual\_PDF\Software\DAQBench)

Users can obtain a 4-hour evaluation version of DAQBench for free from the All-In-One CD. Please contact ADLINK or an ADLINK dealer to purchase the software license.

![3](.pxi-9820-manual-4/d51c6261f5054f6749a0063d4d3f2a73806615a4725c42729a7c01148396adea.jpg)

# Operation Theory

The operation theory of the PXI-9820 is described in this chapter, including the control and setting of signal sources, timebase sources, trigger sources, trigger modes, data transfers, synchronizing multiple modules, and auto-calibration.

# 3.1 Block Diagram

![**Labeled Blocks:**\n*   **CLK IN**\n*   **TRG IO**\n*   **SDI0**\n*   **SDI1**\n*   **CH0**\n*   **50 ohm**\n*   **On-board Precision Reference**\n*   **Calibration DAC**\n*   **AI0 Analog Circuit**\n*   **14-bit 65Ms/s ADC**\n*   **AI1 Analog Circuit**\n*   **Analog Trigger Circuitry**\n*   **Phase-Lock Loop Circuitry**\n*   **Timebase Clock Circuitry**\n*   **SDRAM** (128MB, 512MB)\n*   **PXI_CLK10**\n*   **PLL Control**\n*   **SDRAM Controller**\n*   **Timebase Control**\n*   **Trigger Control**\n*   **PXI-9820 Local Bus Controller**\n*   **PXI Star Trigger**\n*   **Analog Input Control**\n*   **Local Bus Control**\n*   **PXI Trigger Bus Router**\n*   **PCI Controller**\n*   **PXI Star(0-12) / PXI Star**\n*   **PXI Trigger Bus**\n*   **PCI/PXI Interface**\n\n**Connections:**\n*   **CLK IN** connects to **Phase-Lock Loop Circuitry**.\n*   **TRG IO** connects to **Analog Trigger Circuitry**.\n*   **SDI0** and **SDI1** connect to **Timebase Clock Circuitry**.\n*   **CH0** connects to **50 ohm** and **AI0 Analog Circuit**.\n*   **On-board Precision Reference** connects to two **Calibration DAC** blocks.\n*   The two **Calibration DAC** blocks connect to **AI0 Analog Circuit**, **AI1 Analog Circuit**, and **Analog Trigger Circuitry**.\n*   **AI0 Analog Circuit** connects to a **14-bit 65Ms/s ADC**.\n*   **AI1 Analog Circuit** connects to a **14-bit 65Ms/s ADC**.\n*   Both **14-bit 65Ms/s ADC** blocks connect to **Trigger Control** and **Analog Input Control**.\n*   **Analog Trigger Circuitry** connects to **Trigger Control**.\n*   **Phase-Lock Loop Circuitry** connects to **Timebase Clock Circuitry**.\n*   **Timebase Clock Circuitry** connects to **PXI_CLK10** and **Timebase Control**.\n*   **SDRAM** (128MB, 512MB) connects to **SDRAM Controller**.\n*   **PLL Control** connects to **SDRAM Controller**.\n*   **Timebase Control** connects to **PXI Star Trigger**.\n*   **Trigger Control** connects to **PXI-9820 Local Bus Controller**.\n*   **PXI-9820 Local Bus Controller** connects to **Local Bus Control**.\n*   **PXI Star Trigger** connects to **PXI Trigger Bus Router**.\n*   **Analog Input Control** connects to **Local Bus Control**.\n*   **Local Bus Control** connects to **PXI Trigger Bus Router** and **PCI Controller**.\n*   **PCI Controller** connects to **PXI Star(0-12) / PXI Star**.\n*   **PXI Star Trigger** connects to **PXI Star(0-12) / PXI Star**.\n*   **PXI Trigger Bus Router** connects to **PXI Trigger Bus**.\n*   **PXI Star(0-12) / PXI Star** connects to **PXI Trigger Bus**.\n*   **PXI Trigger Bus** connects to **PCI/PXI Interface**.](.pxi-9820-manual-4/807c367a68fd5ef59a680c8bd764b63f86c32229abb3626679968f5a77630f5f.jpg)

Figure 3.1 PXI-9820 Block Diagram

# 3.2 Analog Input Signal Source Control

# Number of Channels

The PXI-9820 provides two simultaneously sampled analog input channels in SE (single ended) connection. Each channel can be enabled individually.

# Signal Range and Input impedance

The available signal input ranges are ±5V or ±1V, which can be set by software. All signals are DC-coupled. The input impedance for high-speed applications should also be considered. The selectable input impedance values are 50Ω and 1.5MΩ. Please refer to section 2.4 for setting impedance.

# 3.3 A/D Sampling rate and Timebase Control

The PXI-9820 supports six timebase sources for analog input conversion:

• Internal 60MHz (Internal VCXO free run mode)
• Internal 60MHz (timebase clock locked to PXI\_CLK10)
• Internal 60MHz (timebase clock locked to external reference 10MHz)
• External sine wave
• PXI Trigger Bus[0:7]
• PXI\_STAR

The following diagram shows the timebase clock architecture of the PXI-9820.

![The flowchart illustrates a clock and trigger routing system, likely for a PXI-based instrument.\n\n**Labeled Blocks:**\n*   **PXI Interface** (top left, double arrow)\n*   **PXI_CLK10**\n*   **Ext. Ref. CLK**\n*   **Ref. Clock Mux**\n*   **Ref. 10MHz**\n*   **Mux**\n*   **CLK IN SMB Connector**\n*   **PLL Circuitry** (dashed box containing)\n    *   **Internal TrimDAC**\n    *   **PLL Synthesizer**\n    *   **VCXO Source Mux**\n    *   **VCXO**\n*   **PLL 60MHz**\n*   **Ext. Timebase**\n*   **Timebase Clock Mux**\n*   **PXI Trigger Bus(0:7)** (bottom left)\n*   **PXI_STAR** (bottom left)\n*   **Routing Matrix**\n*   **To ADC**\n*   **PXI Interface** (bottom right, double arrow)\n\n**Connections:**\n1.  **Clock Selection:** The top-left **PXI Interface** provides **PXI_CLK10** and **Ext. Ref. CLK**, both feeding into the **Ref. Clock Mux**. Additionally, the **Mux** (which takes input from the **CLK IN SMB Connector**) feeds into the **Ref. Clock Mux**.\n2.  **PLL Synthesis:** The output of the **Ref. Clock Mux** is labeled **Ref. 10MHz** and connects to the **PLL Synthesizer** inside the **PLL Circuitry** block.\n3.  **PLL Internal Loop:** Inside the **PLL Circuitry** block, the **PLL Synthesizer** and **Internal TrimDAC** connect to the **VCXO Source Mux**. The **VCXO Source Mux** connects to the **VCXO**, which loops back to the **PLL Synthesizer**.\n4.  **Timebase Generation:** The **PLL Circuitry** outputs **PLL 60MHz** and **Ext. Timebase**, which connect to the **Timebase Clock Mux**.\n5.  **Trigger Routing:** The bottom-left **PXI Interface** provides **PXI Trigger Bus(0:7)** and **PXI_STAR**, which also connect to the **Timebase Clock Mux**.\n6.  **Outputs:** The **Timebase Clock Mux** has two outputs: one labeled **To ADC** and another connecting to the **Routing Matrix**.\n7.  **Final Routing:** The **Routing Matrix** outputs **PXI_STAR** and **PXI Trigger Bus(0:7)**, which connect to the bottom-right **PXI Interface**.](.pxi-9820-manual-4/3b0a054ec82194a5d9fb2f48eff1dca05ba09b645906390b49bda192574fda40.jpg)

Figure 3.2 PXI-9820 Timebase Clock Architecture

Once choosing the timebase source, users can set a 24-bit counter to divide the timebase to get the needed sampling rate. The following formula determines the ADC sampling frequency:

# Sampling Rate = Timebase Frequency / ADC Clock Divisor

where the ADC Clock Divisor = 1,2,3,4,5… 224-1(maximum)

# 3.3.1 Internal Timebase Clock Source

The PXI-9820 has an onboard Voltage Control Crystal Oscillator (VCXO) running at 60MHz. When selects internal timebase clock, you can have free-run mode (none phase-locked) or PLL mode. In free-run mode, the 60MHz timebase clock is coming from the VCXO which is controlled by an internal trim DAC. In PLL mode, the onboard 60MHz timebase phase locked to the reference 10MHz clock. The reference 10MHz clock comes from PXI backplane (PXI\_CLK10) or front panel SMB connector (CLK IN).

# 3.3.2 External Timebase Clock Source

When users need a specific timebase in some applications that the onboard 60MHz timebase is not achievable, a timebase clock from an external device can replace onboard timebase clock. In addition, external timebases also provides a method to synchronize PXI-9820 to other measurement modules by distributing/receiving a common clock to/from multiple modules. The PXI-9820 can receive an external timebase clock from the front panel connector (CLK IN), PXI Star trigger or one of the PXI Trigger bus line.

Users can supply the timebase from external SMB connector CLK IN, which should be a sine wave signal. This signal is AC coupled with 50Ω input impedance and the valid input level is from 1 to 2 volts peak-to -peak. Note that the external clock must be continuous for correct ADC operation because of the pipeline architecture of the ADC.

PXI-9820 can receive the timebase clock via one of the trigger bus lines by software selection. The eight PXI trigger bus lines (PXI\_TRIG[0:7]) provide intermodule synchronization and communication. Note that this function is only available when the PXI-9820 is in a PXI system. It’s not supported when PXI-9820 is in a CompactPCI system.

When PXI-9820 is plugged into a generic peripheral slot, it can receive timebase clock from PXI\_STAR. The PXI\_STAR signal comes from star trigger controller are matched in propagation delay within 1ns and the delay from star trigger slot to a peripheral slot is less than 5ns. According to these hardware features, PXI-9820 can achieve very good synchronization performance when using PXI\_STAR as timebase clock source. Note that this function is only available when the PXI-9820 is in a PXI system. It’s not supported when PXI-9820 is in a CompactPCI system.

# 3.3.3 PLL Reference Clock Source

The PXI-9820 equipped with a phase-locked loop circuit to synchronize the timebase clock to reference clock. The PXI-9820 can receive a reference clock from the front panel connector (CLK IN) as well as from PXI\_CLK10. The reference clock from front panel connector should be a stable 10MHz clock. The input of CLK IN is AC coupled with 50Ω input impedance and the valid input level is from 1 to 2 volts peak-to -peak. Note that the reference clock must be continuous for correct PLL operation. Once the reference clock disconnected, the timebase clock will still exist but not phase lock to reference clock anymore. When using external timebase clock, it’s not valid to lock to reference clock.

# 3.3.4 Timebase Clock Exporting

The PXI-9820 can export timebase clock to the following two destinations: PXI\_STAR or one of PXI Trigger bus lines. When PXI-9820 plugged into star trigger controller slot of the PXI backplane, it can export timebase clock to the other 13 generic peripheral slots. The PXI-9820 can also export timebase clock onto one of the eight PXI trigger bus lines. By software programming, user can pick up a trigger line to transmit timebase clock. These two features are very useful when synchronize to multiple measurement modules.

# 3.3.5 Timebase 50% duty cycle restore function

Because the on-board sample-and-hold circuit is in hold mode when the timebase is high and in track mode when timebase is low, the PXI-9820 can get the best dynamic response performance for high-frequency analog inputs when the timebase has a 50% duty cycle. However, it is often difficult to maintain a 50% duty cycle; especially when driving the timebase with a single-ended or sinewave input. To ease the constraint of providing an accurate 50% timebase, the PXI-9820 has an optional duty cycle restore function to restore the timebase duty cycle to 50%, independent of the clock input duty cycle. Low jitter on the rising edge (sampling edge) of the timebase is preserved while the falling edge is interpolated.

It may be desirable to disable the duty cycle restore function when users use the external timebase input whose frequency is varied. Once the timebase frequency is changed, over 100 clock cycles may be required for the duty cycle restore circuit to settle to the new speed. Duty cycle restore function is software programmable when configuring your PXI-9820.

# 3.3.6 130MS/s Sampling using Ping-Pong Mode

The PXI-9820 uses two A/D converters, each running at 60MS/s, to provide a dual-channel simultaneous real-time sampling rate of 60MS/s. (65MS/s with external timebase)

For the single-channel acquisition, the two ADCs can be clocked in a “ping-pong” mode to achieve up to 120MS/s sampling (130MS/s with external timebase). Figure 3.3 illustrates the operation. Note that only CH0 can be applied to ping-pong mode. The onboard auto-calibration circuitry allows the two channels to be matched in order to reduce the image signal.

![The diagram illustrates a signal processing system with the following labeled blocks and connections:\n\n**Labeled Blocks:**\n*   **CH0 Input**\n*   **CH1 Input**\n*   **Amplifier circuitry** (appears twice, represented by triangle symbols)\n*   **ADC** (appears twice, represented by square blocks)\n*   **Timebase with 180 degree phase difference** (text label)\n\n**Connections:**\n*   **CH0 Input** connects to a node. From this node, one line goes right to the top **Amplifier circuitry**. Another line goes down vertically.\n*   **CH1 Input** connects to a switch terminal.\n*   A switch connects the bottom **Amplifier circuitry** input to either the vertical line from **CH0 Input** or the **CH1 Input** line.\n*   The top **Amplifier circuitry** connects to the top **ADC** block.\n*   The bottom **Amplifier circuitry** connects to the bottom **ADC** block.\n*   Both **ADC** blocks contain the label **clk** inside (near the bottom right) and output a line to a waveform.\n*   The top waveform is a square wave.\n*   The bottom waveform is an inverted square wave.\n*   The text **Timebase with 180 degree phase difference** is positioned above the waveforms with an arrow pointing to both waveforms.](.pxi-9820-manual-4/10c0c345662fa7a2135854366a0202fb56d76267d78d8c9199fe616f80b7d1db.jpg)

Figure 3.3 “Ping-pong” mode operations

# 3.3.7 Synchronous Digital Input

The PXI-9820 contains two synchronous digital input channels, SDI0 and SDI1. These two digital input lines can be sampled synchronously with timebase clock for mixed signal applications. Thus the data transfer can up to 60Mbit/s when using internal 60MHz timebase clock. These two digital input lines are combined with analog input channels, respectively. Please refer to Figure 3.4 for the data format of ADC and SDI. When the analog input channel of PXI-9820 is configured as “ping-pong” mode, only SDI0 is enabled.

![Based on the provided image, here is the accurate description of the flowchart/block diagram:\n\n**Labeled Blocks and Components:**\n*   **SDI** (labeled above a square wave)\n*   **Digital Input Buffer** (labeled above a buffer gate)\n*   **D Flip-Flop** (labeled above a flip-flop symbol; pins labeled **D**, **Q**, **CLK**)\n*   **Analog Input** (labeled above a sine wave)\n*   **Amplifier Circuitry** (labeled below an amplifier gate)\n*   **ADC** (labeled above a box; pins labeled **Data**, **CLK**)\n*   **Timebase** (labeled next to a square wave)\n*   **Register Block** (far right box containing fields **SDI**, **OTR**, **ADC Data**)\n*   **Bit 15**, **Bit 14**, **Bit 13**, **Bit 0** (labels above the Register Block)\n\n**Connections:**\n1.  **SDI** connects to the **Digital Input Buffer**.\n2.  The output of the **Digital Input Buffer** connects to the **D** input of the **D Flip-Flop**.\n3.  The **Q** output of the **D Flip-Flop** connects to the **SDI** field (Bit 15) of the Register Block.\n4.  The **CLK** input of the **D Flip-Flop** connects to the **CLK** input of the **ADC**.\n5.  **Analog Input** connects to the **Amplifier Circuitry**.\n6.  The output of the **Amplifier Circuitry** connects to the **ADC**.\n7.  The **Data** output of the **ADC** connects to the **ADC Data** field of the Register Block.\n8.  The **Timebase** signal connects to the **CLK** input of the **ADC** (which is also connected to the D Flip-Flop clock line).](.pxi-9820-manual-4/114dc4d5026ecbca2f632de5a085c9ac9771a3b8626c8923fd1c3226cdb20a2f.jpg)

Figure 3.4 Synchronous digital input operations

# 3.4 Trigger Sources

In addition to the internal software trigger, the PXI-9820 also supports external analog triggers, external digital triggers, PXI\_STAR triggers and PXI Trigger Bus[0:7]. Users can configure the trigger source by software. Refer to Figure 3.5 for PXI-9820 trigger architecture.

![Based on the provided flowchart, here is the description of the labeled blocks and their connections:\n\n**Inputs and Source Mux (Left Side)**\n*   **Software Trigger** and **Digital Trigger** connect to the **Trigger Source Mux**. The **Digital Trigger** originates from a **TRG I/O SMB Connector**.\n*   **Analog CH0** and **Analog CH1** connect to the **Analog TRG Circuit**. The output of this circuit, labeled **Analog Trigger**, connects to the **Trigger Source Mux**.\n*   From the **PXI Interface**, **PXI_STAR** and **PXI Trigger Bus(0:7)** connect to the **Trigger Source Mux**.\n\n**Processing and Decision (Center)**\n*   The **Trigger Source Mux** connects to the **Trigger Decision** block.\n*   The **Trigger Decision** block has an output labeled **To Internal Circuit**.\n*   The **Trigger Decision** block also outputs signals labeled **SSI_TRIG1**, **SSI_TRIG2**, and **SSI_START_OP** into the **Trigger Output Mux**.\n\n**Outputs (Right Side)**\n*   The **Trigger Output Mux** connects to a **TRG I/O SMB Connector**.\n*   The **Trigger Output Mux** outputs **PXI_STAR** and **PXI Trigger Bus(0:7)** to the **PXI Interface**.](.pxi-9820-manual-4/ca1b7390966e23b378e2eb789fb29d9a3f1d8cf27d62786ca68b09bb61b3b105.jpg)

Figure 3.5 PXI-9820 Trigger Architecture

# 3.4.1 Software Trigger

This trigger mode does not need any external trigger source. The trigger asserts right after executing specified function calls to begin the operation.

# 3.4.2 External Analog Trigger

Users can choose either CH0 or CH1 as the trigger signal while using external analog trigger source. The trigger level can be set by software with 8-bit resolution. Please refer to Table 3.1 for the ideal transfer characteristic.

<table><tr><td>Trigger Level digital setting</td><td>Trigger voltage (±5V range)</td><td>Trigger voltage (±1V range)</td></tr><tr><td>0xFF</td><td>4.96V</td><td>0.992V</td></tr><tr><td>0xFE</td><td>4.92V</td><td>0.984V</td></tr><tr><td>---</td><td>---</td><td>---</td></tr><tr><td>0x81</td><td>0.04V</td><td>0.008V</td></tr><tr><td>0x80</td><td>0</td><td>0</td></tr><tr><td>0x7F</td><td>-0.04V</td><td>-0.008V</td></tr><tr><td>---</td><td>---</td><td>---</td></tr><tr><td>0x01</td><td>-4.96V</td><td>-0.992V</td></tr></table>

Table 3.1 Analog trigger ideal transfer characteristic

The trigger conditions for analog triggers are illustrated in Figure 3.6 and described as follows:

• Positive-slope trigger - The trigger event occurs when the trigger signal (analog input signal) changes from a voltage that is lower than the specified trigger level to a voltage that is higher than the specified trigger level.
• Negative-slope trigger - The trigger event occurs when the trigger signal (analog input signal) changes from a voltage that is higher then the specified trigger level to a voltage that is lower than the specified trigger level.

![| Trigger level | Event occurrence |\n| ------------- | ---------------- |\n| Low           | Positive slope    |\n| High          | Negative slope    |](.pxi-9820-manual-4/a6c37fab467dd115b581be5ac5d1df9b06337e107ea8160d7f8c4888a9570300.jpg)

Figure 3.6 Analog trigger conditions

# 3.4.3 External Digital Trigger

An external digital trigger occurs when a TTL rising edge or a falling edge is detected at the SMB connector TRG IO on the front panel, as illustrated in Figure 3.7. The trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL-compatible, and the minimum pulse width is 10ns.

![Based on the image provided, here is the accurate description of the flowchart-like diagram:\n\n**Left Diagram**\n*   **Label:** 'Positive-edge Trigger event occurs'\n*   **Visual Connection:** An upward-pointing arrow is placed on the rising edge of a square wave line.\n\n**Right Diagram**\n*   **Label:** 'Negative-edge Trigger event occurs'\n*   **Visual Connection:** A downward-pointing arrow is placed on the falling edge of a square wave line.\n\nThere are no connections between the left and right diagrams; they are presented as separate examples side-by-side.](.pxi-9820-manual-4/8bb95bcc8bd585bc9638c541bd080b80a2959beb2fea5796a9b0258476e09687.jpg)

Figure 3.7 External digital trigger input

# 3.4.4 PXI\_STAR Trigger

When users select PXI\_STAR as trigger source, the PXI-9820 can accept a TTL-compatible digital signal as a trigger signal. The trigger occurs when a rising edge or falling edge is detected at PXI\_STAR. User can use software to configure the trigger polarity. The minimum pulse width requirement of this digital trigger signal is 10ns.

# 3.4.5 Triggers from PXI Trigger Bus[0:7]

The PXI-9820 utilizes PXI Trigger Bus[0:7] as System Synchronization Interface (SSI). Using the interconnected bus provided by PXI Trigger Bus, user can easily synchronize multiple modules. When configured as input, the PXI-9820 can accept three different SSI signals, SSI\_TRIG1, SSI\_TRIG2 and SSI\_START\_OP (for more detail about these signals, please refer to section 3.9). Each signal can be routed from one of the PXI Trigger Bus[0:7] by software programming.

# 3.5 Trigger Modes

The PXI-9820 provides 5 trigger sources (internal software trigger, external analog trigger, external digital trigger, PXI\_Star trigger, and PXI Trigger Bus[0:7] signals). Users must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source (For example, a rising edge on the external digital trigger input).

There are 4 trigger modes (pre-trigger, post-trigger, middle-trigger, and delay-trigger) working with the 5 trigger sources to initiate different data acquisition timing when a trigger event occurs. They are described as follows.

# 3.5.1 Post-trigger Acquisition

Use post-trigger acquisition when you want to collect data after the trigger event, as illustrated in Figure 3.8.

![This diagram illustrates a timeline sequence.\n\n**Labeled Blocks/Elements:**\n*   **Time:** A horizontal blue line with an arrow pointing right at the far right end.\n*   **Operation start:** Text above a vertical blue arrow pointing down at the timeline.\n*   **Trigger event:** Text above a vertical blue arrow pointing down at the timeline.\n*   **Acquisition stop:** Text above a vertical blue arrow pointing down at the timeline.\n\n**Connections:**\n*   A horizontal black arrow points from the 'Trigger event' location toward the 'Acquisition stop' location.\n*   The text 'Acquired & stored data with the speci-fied amount' is positioned above this horizontal arrow.](.pxi-9820-manual-4/1ae1846bfa6f725a268fb30f394295b585994ea18158df1d55d126c4806c5117.jpg)

Figure 3.8 Post trigger

# 3.5.2 Pre-trigger Acquisition

Use pre-trigger acquisition to collect data before the trigger event. The acquisition starts once specified function calls are executed to begin the pre-trigger operation, and it stops when the trigger event occurs.

If the trigger event occurs after the specified amount of data has been acquired, the system only stores the data before the trigger event with the specified amount, as illustrated in Figure 3.9.

![Based on the provided image, here is an accurate and concise description:\n\n**Labeled Blocks and Elements:**\n*   **Time:** A horizontal blue line at the bottom.\n*   **Operation start:** Label above a vertical blue line dropping onto the time axis.\n*   **Trigger event:** Label above a vertical blue line dropping onto the time axis.\n*   **Acquired data:** Text label above a double-headed horizontal arrow.\n*   **Acquired & stored data with the speci fied amount:** Text label (split across three lines) above a shorter double-headed horizontal arrow.\n*   There is also a vertical dashed line on the time axis.\n\n**Connections:**\n*   A double-headed arrow labeled **'Acquired data'** spans the entire duration, with its left arrowhead pointing to the **'Operation start'** line and its right arrowhead pointing to the **'Trigger event'** line.\n*   A second double-headed arrow labeled **'Acquired & stored data with the speci fied amount'** spans a shorter duration. Its right arrowhead points to the **'Trigger event'** line, and its left arrowhead points to the vertical dashed line.](.pxi-9820-manual-4/aa98058d4255bc99e9f729c7320f7d4655048c4bb0983b7927e563095e82a5e4.jpg)

Figure 3.9 Pre trigger (the trigger event occurs after the specified amount of data has been acquired)

However, if the trigger event occurs before the specified amount of data has been acquired, the system can either stop the acquisition immediately (which implies the stored data will be less then the amount you specified) or ignore the trigger signal until the specified amount of data has been acquired (which assures the user can get the specified amount of data). These can be set by software and are illustrated in Figure 3.10 and Figure 3.11.

![Based on the provided image, here is an accurate and concise description of the flowchart/block diagram:\n\n**Main Axis**\nA blue horizontal line extends across the diagram, pointing to the right, and is labeled 'Time' at the far right end.\n\n**Top Section**\nTwo vertical blue arrows point downward onto the timeline:\n*   The left arrow is labeled '**Operation start**'.\n*   The right arrow is labeled '**Trigger event**'.\n\nBetween these two vertical arrows, centered above the timeline, is the text '**Acquired & stored data**'. This text is flanked by horizontal arrows: a left-pointing arrow to the left of 'Acquired' and a right-pointing arrow to the right of '&'.\n\n**Bottom Section**\nBelow the timeline, a horizontal arrow spans a specific duration. It is labeled '**Specified amount of data**'.\n*   The arrow has a left-pointing head on the left side and a right-pointing head on the right side.\n*   The left end of the arrow aligns with a vertical dashed line dropping down from the 'Operation start' marker.\n*   The right end of the arrow aligns with a second vertical dashed line extending further right along the timeline.](.pxi-9820-manual-4/29439e38230fd70bb85d156d638ea3253dcaf4d05d8deeba3dc7b34967b92702.jpg)

Figure 3.10 Pre trigger (The trigger signal is accepted anytime after the operation starts)

![Based on the provided image, here is an accurate and concise description of the flowchart/diagram:\n\n**Main Components:**\n*   **Time:** A horizontal blue arrow pointing to the right, labeled 'Time'.\n*   **Operation start:** A vertical dashed line marking the beginning of the timeline.\n*   **Specified amount of data:** A hatched (diagonally striped) rectangular region located immediately after 'Operation start'.\n*   **Trigger event:** A vertical blue arrow pointing down to the timeline, located to the right of the hatched region.\n\n**Annotations and Connections:**\n*   **Ignored Signals:** An arrow points down into the hatched region with the text: 'Trigger signals that occur before the specified amount of data has been acquired (shadow area) will be ignored.'\n*   **Data Association:** Below the timeline on the right, there is text reading 'Acquired & stored data with the specified amount'. An arrow points left from the 'Trigger event' line toward the end of the hatched region, indicating the relationship between the trigger and the buffered data.](.pxi-9820-manual-4/d24cfb45a1c67f9cb00d6fe329cdaeabe0d229fbf92f5d71c7850c2cff430d0d.jpg)

Figure 3.11 Pre trigger (The trigger signal will be ignored until the specified amount of data is acquired)

# 3.5.3 Middle-trigger Acquisition

Use middle-trigger acquisition when you want to collect data before and after the trigger event. The amount of stored data before and after the trigger can be set individually (M and N), as illustrated in Figure 3.12.

![This is a timeline diagram illustrating data acquisition relative to an event.\n\n**Labeled Blocks:**\n*   **Bottom Axis:** A blue horizontal line with an arrowhead pointing right, labeled 'Time'.\n*   **Left Event:** 'Operation start' positioned above a blue vertical arrow pointing down to the timeline.\n*   **Center Event:** 'Trigger event' positioned above a blue vertical line crossing the timeline.\n*   **Left Data Block:** Text reading 'Acquired & stored data with the spec' on one line and 'fied amount (M)' on the next.\n*   **Right Data Block:** Text reading 'Acquired & stored data with the spec' on one line and 'fied amount (N)' on the next.\n\n**Connections and Layout:**\n*   The 'Operation start' arrow connects to the beginning of the timeline.\n*   The 'Trigger event' line intersects the timeline in the center.\n*   To the left of the 'Trigger event' line, the 'Acquired & stored data with the spec\nfied amount (M)' text block is shown. A small arrow points left from this text towards a dashed vertical line.\n*   To the right of the 'Trigger event' line, the 'Acquired & stored data with the spec\nfied amount (N)' text block is shown. A small arrow points right from this text towards a dashed vertical line.\n*   Two small arrows originate near the 'Trigger event' line: one points left towards the (M) block, and one points right towards the (N) block.](.pxi-9820-manual-4/08bcccc9cc4ee12d5e9517299d9f60cb235c1b212f9eef71d318d1e0a54d6499.jpg)

Figure 3.12 Middle trigger

Like pre-trigger mode, the stored data may be less than the amount specified if the trigger event occurs before the specified amount of data (M) has been acquired. Users can also set by program to ignore trigger signals until the specified amount of data (M) has been acquired.

# 3.5.4 Delay-trigger Acquisition

Use delay trigger acquisition to delay the data collection after the trigger event, as illustrated in Figure 3.13. The delay time is specified by a 32-bit counter value so that the maximum delay time is the period of timebase \* $( 2 ^ { 3 2 } - 1 )$ , while the minimum delay time is the period of timebase.

![This is a timeline diagram illustrating a sequence of events over time.\n\n**Labeled Blocks (Time Points):**\n*   **Operation start**: Marked by a solid blue vertical arrow pointing downward.\n*   **Trigger event**: Marked by a solid blue vertical arrow pointing downward.\n*   **Acquisition start**: Marked by a dashed vertical line.\n*   **Acquisition stop**: Marked by a solid blue vertical arrow pointing downward.\n\n**Connections (Intervals and Labels):**\n*   **Time Axis**: A horizontal blue arrow points to the right at the bottom, labeled **Time**.\n*   **Interval 1**: Between 'Trigger event' and 'Acquisition start', there is a label **Delay**. This interval is bracketed by a left-pointing arrow near 'Trigger event' and a right-pointing arrow near 'Acquisition start'.\n*   **Interval 2**: Between 'Acquisition start' and 'Acquisition stop', there is a label spanning two lines: **Acquired & stored data with the speci-** and **fied amount**. This interval is bracketed by a right-pointing arrow near 'Acquisition start' and a left-pointing arrow near 'Acquisition stop'.](.pxi-9820-manual-4/c35ba274e0f6e4f128d6b8efbd52cff192567c1832c8c763b58e352804e257ca.jpg)

Figure 3.13 Delay trigger

# 3.5.5 Post-trigger or Delay-trigger Acquisition with Re-trigger

Use post-trigger or delay-trigger acquisition with re-trigger function to collect data after several trigger events, as illustrated in Figure 3.14. Users can program the number of triggers then the PXI-9820 will acquire an additional record each time a trigger is accepted until all the requested records have been stored in memory. After the initial setup, the process does not require software intervention.

![This diagram illustrates a timeline of events and data acquisition.\n\n**Labeled Blocks and Elements:**\n*   **Time:** A blue horizontal arrow at the bottom pointing to the right, labeled 'Time'.\n*   **Operation start:** Text above a vertical blue arrow pointing down to the timeline.\n*   **Trigger event:** Text above a vertical blue arrow pointing down to the timeline.\n*   **Acquired Data:** Text appearing twice, positioned to the right of the 'Trigger event' arrows.\n*   **Trigger event:** Text above a second vertical blue arrow pointing down to the timeline.\n*   **Acquired Data:** Text appearing a second time, positioned to the right of the second 'Trigger event' arrow.\n\n**Connections and Layout:**\n*   The 'Operation start' arrow is the leftmost element on the timeline.\n*   To the right of 'Operation start', the first 'Trigger event' arrow appears. Next to it, the text 'Acquired Data' is flanked by a left-pointing arrow (pointing toward the 'Trigger event' line) and a right-pointing arrow (pointing toward a dashed vertical line).\n*   Further to the right, a second 'Trigger event' arrow appears. Next to it, the text 'Acquired Data' is flanked by a left-pointing arrow (pointing toward the second 'Trigger event' line) and a right-pointing arrow (pointing toward a second dashed vertical line).](.pxi-9820-manual-4/cdea79aac184ba7d52095fb18cba3c871f9869ae3b78ddd65da209d0bea14fdd.jpg)

Figure 3.14 Post-trigger with re-trigger

# 3.6 Trigger Signals Exporting

The PXI-9820 can export trigger signals to the following connectors: TRG IO, PXI\_STAR or PXI Trigger Bus[0:7].

The TRG IO on the front panel can also be programmed to output the trigger signal when the trigger source is from software trigger, analog trigger, PXI\_STAR trigger, or PXI Trigger Bus[0:7]. The timing characteristic is in Figure 3.15.

![TRG IO\nTw = 2 - 3 TIMEBASE clocks](.pxi-9820-manual-4/8583f252966be545e8f310bcdf2b3c594741c39ac82bf53d58917ec0125db50c.jpg)

Figure 3.15 TRG IO output signal timing

When the PXI-9820 is plugged into the star trigger controller slot, i.e. slot 2, in a PXI system, it can export trigger signals to other 13 generic peripheral slots (PXI\_STAR0 \~ PXI\_STAR12) through the PXI star trigger pin. The trigger signal source can be from software trigger, external digital trigger signal from TRG IO, analog trigger and PXI Trigger Bus[0:7]. The output trigger signal timing characteristic is identical to the TRG IO which is shown in figure 3.15.

The PXI-9820 utilize PXI Trigger Bus[0:7] as System Synchronize Interface. When configured as output, the PXI-9820 can output 3 different trigger signals, SSI\_TRIG1, SSI\_TRIG2 and SSI\_START\_OP. User can route these signals to any one of PXI Trigger Bus[0:7] by software programming.

# 3.7 Data Transfers

Since the maximum data throughput on the PXI-9820 (60MS/s \* 2 channels \* 2 Bytes/channel = 240MB/s) is much higher than the 32bit/33MHz PCI-bus bandwidth, samples are acquired into the onboard SDRAM memory before being transferred to the host computer. Since the number of stored samples per acquisition is limited by the amount of on-board memory, the PXI-9820 supports different sizes of SODIMM SDRAM ranging from 128MB to 512MB in order to meet application requirements.

Once all the data has been stored in the on-board memory, the data will be transferred to the host computer’s memory through bus-mastering DMA.

In a multi-user or multi-tasking OS, like Microsoft Windows, Linux, and so on, it is difficult to allocate a large continuous memory block to do the DMA transfer. Therefore, the PXI-9820 provides the function of scatter /gather DMA to link the non-continuous memory blocks into a linked list so that users can transfer very large amounts of data without being limited by the fragment of small size memory, as illustrated in Figure 3.16.

![The diagram displays a hierarchical structure with blocks and connections:\n\n**Top Row:**\nThere are three rectangular blocks arranged horizontally, each containing a list of four text lines:\n1.  **Left Block:** 'First PCI Address', 'First Local Address', 'Transfer Size', 'Next Descriptor'.\n2.  **Middle Block:** 'PCI Address', 'Local Address', 'Transfer Size', 'Next Descriptor'.\n3.  **Right Block:** 'PCI Address', 'Local Address', 'Transfer Size', 'Next Descriptor'.\n\n**Connections:**\n*   Thick black arrows point from the left block to the middle block, and from the middle block to the right block.\n\n**Middle Row:**\n*   A wide rectangular block labeled 'PCI Bus' is positioned below the top row.\n*   An upward-pointing triangle connects the middle block to the top edge of the 'PCI Bus' block.\n\n**Bottom Row:**\n*   Three rectangular blocks are positioned at the bottom, each labeled 'Local Memory'.\n*   An upward-pointing triangle connects the top of these blocks to the bottom edge of the 'PCI Bus' block.](.pxi-9820-manual-4/81d66422603f4e6b0b80201753134f8da15c2fa63058fb607e9a520b50f00cd4.jpg)

Figure 3.16 Scatter/gather DMA for data transfer

If the data throughput from the PXI-9820 is less than the available PCI bandwidth (For example: 20MS/s \* 2 channels \* 2 Bytes/channel = 80MB/s), the PXI-9820 also features on-board 3k-sample FIFO to achieve real-time transfer bypassing the SDRAM, directly to host memory.

# 3.8 AI Data Format

Table 3.2 illustrates the ideal transfer characteristics of various input ranges of the PXI-9820. Bit13-0 is the acquired 14-bit A/D data with binary coding format while bit14 is the out-of-range (OTR) indicator (logic “1” means out-of-range). As described in section 3.3.7, bit 15 is the synchronous digital input data. SDI0 is within the data format of analog channel 0 while SDI1 is within the data format of analog channel 1.

<table><tr><td>Description</td><td colspan="2">Analog Input Voltage</td><td>Digital code</td></tr><tr><td>Full-scale Range</td><td>±5V</td><td>±1V</td><td></td></tr><tr><td>Least significant bit</td><td>0.61mV</td><td>0.122mV</td><td></td></tr><tr><td>&gt; = FSR</td><td>&gt;= 5V</td><td>&gt;= 1V</td><td>7FFF</td></tr><tr><td>FSR-1LSB</td><td>4.99939V</td><td>0.999878V</td><td>3FFF</td></tr><tr><td>Midscale +1LSB</td><td>0.61mV</td><td>0.122mV</td><td>2001</td></tr><tr><td>Midscale</td><td>0V</td><td>0V</td><td>2000</td></tr><tr><td>Midscale -1LSB</td><td>-0.61mV</td><td>-0.122mV</td><td>1FFF</td></tr><tr><td>-FSR</td><td>-5V</td><td>-1V</td><td>0000</td></tr><tr><td>&lt; -FSR</td><td>&lt; -5V</td><td>&lt; -1V</td><td>4000</td></tr></table>

Table 3.2 Analog input voltage and the output digital code (Note that bit14 is the out-of-range indicator)

# 3.9 Synchronizing Multiple Devices

The eight interconnected lines on PXI backplane named as PXI Trigger Bus[0:7] provide a flexible interface for multiple modules synchronization. The PXI-9820 utilizes the PXI Trigger Bus[0:7] as the System Synchronization Interface (SSI). By providing flexible routing of timebase clock and trigger signals onto PXI Trigger Bus, the PXI-9820 makes the synchronization between multiple modules easy and simple.

The bi-directional SSI I/Os provide a flexible connection between modules, which allows one SSI master PXI-9820 to output the SSI signals to other slaves PXI-9820s to receive the signals. Table 3.3 lists the summary of SSI timing signals and the functionalities. Figure 3.17shows the architecture of SSI. Note that it’s not allowed to route different signals onto the same trigger bus line.

<table><tr><td>SSI timing signal</td><td>Functionality</td></tr><tr><td>SSI_TIMEBASE</td><td>Input/Output 60MHz timebase signal through SSI</td></tr><tr><td>SSI_TRIG1</td><td>Input/Output the trigger signal through SSI</td></tr><tr><td>SSI_TRIG2</td><td>Input/Output the clocked trigger signal through SSI</td></tr><tr><td>SSI_START_OP</td><td>Input/Output the acquisition start signal in pre-trigger or middle-trigger mode</td></tr></table>

Table 3.3 Summary of SSI timing signals and the corresponding function

![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Left Section:**\n*   A vertical double-headed arrow on the far left is labeled **'PXI Interface'**.\n*   This connects to a vertical line labeled **'PXI Trigger Bus(0:7)'**.\n\n**Middle Section (Parallel Paths):**\n*   The 'PXI Trigger Bus(0:7)' splits into four parallel horizontal branches.\n*   Each branch connects to a column of eight small circles (contacts).\n*   From the top circle in each column, a line connects to a switch.\n*   The output of each switch connects to a buffer/driver component (triangular symbol).\n\n**Right Section (Outputs and Logic):**\n*   The four buffer outputs are labeled from top to bottom:\n    1.  **'SSI_TIMEBASE'** (with an arrow pointing right)\n    2.  **'SSI_TRG1'** (with an arrow pointing right)\n    3.  **'SSI_TRG2'** (with an arrow pointing right)\n    4.  **'SSI_START_OP'** (with an arrow pointing right)\n*   Arrows from **'SSI_TRG1'**, **'SSI_TRG2'**, and **'SSI_START_OP'** point into a rectangular box on the far right labeled **'Trigger Decision'**.](.pxi-9820-manual-4/4c04c43ab52277a4c255f6dee89745c85f9d3304d68b120106dce6873e77fa7a.jpg)

Figure 3.17 SSI Architecture

# 3.9.1 SSI\_TIMEBASE

As an output, the SSI\_TIMEBASE signal outputs the onboard 60MHz LVTTL timebase through PXI Trigger Bus.

As an input, the PXI-9820 accepts the SSI\_TIMEBASE signal to be the source of timebase.

# 3.9.2 SSI\_TRIG1

As an output, the SSI\_TRIG1 signal reflects the trigger event signal in an acquisition sequence. Users can use the function SSI\_SourceConn() to output the SSI\_TRIG1 signal.

As an input, the PXI-9820 accepts the SSI\_TRIG1 signal to be the trigger event source. The signal is configured in the rising edge-detection mode. When selecting the trigger sources of the PXI-9820, Users can select TRSRC\_SSI\_1 to set SSI\_TRIG1 as the source of trigger event.

Figure 3.18 and Figure 3.19 show the input and output timing requirements.

![SSI_TRIG1\nTw\nTw = 2 - 3 TIMEBASE clocks](.pxi-9820-manual-4/90aff8404343a9a8458d7af3a95cf81f7b237519aad2513edcf8367a3f944b14.jpg)

Figure 3.18 SSI\_TRIG1 output signal timing

![SSI_TRIG1\nTw\nTw = 20 ns minimum](.pxi-9820-manual-4/b19bdd99294d1aaa27906e3fe0ecd1e95c38f1801e7f4b99aa7c66d4ab91f7f1.jpg)

Figure 3.19 SSI\_TRIG1 input signal timing

# 3.9.3 SSI\_TRIG2 and SSI\_START\_OP

As an output, the SSI\_TRIG2 signal is a clocked SSI\_TRIG1 signal by TIMEBASE, as illustrated in Figure 3.20.

![SSI_TRIG1\nTIMEBASE\nT_w\nSSI_TRIG2\nT_w = 2 TIMEBASE clocks](.pxi-9820-manual-4/e1f98d17795b13f7c111383f497a636b8967f133d4fdcbb2f1822a47148fe86b.jpg)

Figure 3.20 SSI\_TRIG2 output signal timing

As an input, the PXI-9820 accepts the SSI\_TRIG2 signal to be the source of a one-clock delayed trigger event. The controller on the PXI-9820 will then compensate the one-clock delay if using SSI\_TRIG2 as the source of trigger event. The signal is configured in the rising edge-detection mode.

![SSI_TRIG2\nTw\nTw = 20 ns minimum](.pxi-9820-manual-4/20fbca12d9a96e803bec83237fc9ec5e766ce02e4fdb3eac7d108877acc76d76.jpg)

Figure 3.21 SSI\_TRIG2 input signal timing

As an output, the SSI\_START\_OP signal reflects the operation start signal in a pre-trigger or middle-trigger acquisition sequence. Please refer to Figure 3.9 - Figure 3.12 for the relationship between the operation start signal and the acquisition sequence.

As an input, the PXI-9820 accepts the SSI\_START\_OP signal to be the operation start signal in a pre-trigger or middle-trigger acquisition sequence. The signal is configured in the rising edge-detection mode. Figure 3.22 and Figure 3.23 show the SSI\_START\_OP signal input and output timing requirements.

For enabling output operations, users can use the function SSI\_SourceConn() to output the SSI\_TRIG2 and SSI\_START\_OP signals.

For the input operations, users can select TRSRC\_SSI\_2 to set SSI\_TRIG2 and SSI\_START\_OP as the source of the trigger event and operation start signal.

![SSI_START_OP\nTw = 2 TIMEBASE clocks](.pxi-9820-manual-4/2255b1caaa5b1a972ee3773d070e2ed41c0051fda14968dc1f8a71364f4185b3.jpg)

Figure 3.22 SSI\_START\_OP output signal timing

![SSI_START_OP\nT_w\nT_w = 20 ns minimum](.pxi-9820-manual-4/ce2155d45121f6cb889769f30b90e19b8b4a9c81c79a17224de4665b53036624.jpg)

Figure 3.23 SSI\_START\_OP input signal timing

# 3.9.4 Comparing the different trigger sources from SSI

When selecting TRSRC\_SSI\_1 as the trigger source input, the signal SSI\_TRIG1 reflects the trigger event signal in an acquisition sequence. However, when synchronizing multiple PXI-9820 devices, each PXI-9820 may recognize the trigger signal with one-clock time difference because the signal is not related to the timebase.

There is another phenomenon if using TRSRC\_SSI\_2 in pre-trigger and middle-trigger mode. The operation start signal is generated by a software command so multiple PXI-9820 devices don’t start the data acquisition simultaneously, which may result in the fact that the amount of stored samples are different if the trigger event occurs before the specified amount of data has been acquired.

When selecting TRSRC\_SSI\_2 as the trigger source input, SSI\_TRIG2 and SSI\_START\_OP can achieve better synchronization between multiple PXI-9820 devices. A clocked SSI\_TRIG2 can guarantee all PXI-9820 devices recognize the trigger event at the same clock edge if they use the same timebase. In pre-trigger and middle-trigger mode, SSI\_START\_OP guarantees all the PXI-9820 devices start the data acquisition at the same time.

# 3.10 Auto-calibration

By using the auto-calibration feature of the PXI-9820, the calibration software can measure and correct offset and gain errors without any external signal connections, reference voltages, or measurement devices.

After the auto-calibration procedure finishes, the calibration constants can be saved into the EEPROM. In addition to the default bank of factory calibration constants, there are three extra user-modifiable banks in the EERPOM for users to store three sets of calibration constants according to different environments and re-load the calibration constants when necessary.

Because of the fact that errors in measurements will vary with time and temperature, it is recommended that users re-calibrate the PXI-9820 when the module is installed in a new environment.

Note: Before auto-calibration procedure starts, please warm up the module for at least 15 minutes.

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