# PXIe-3987/3977/3937

# PXI Express Embedded Controller

# User’s Manual

![Exterior view of an ADLINK PCIe-3987 PCIe Interface Controller module (no visible text or symbols on main components)](.pxie-3987-3977-3937-50-17056-1010-11/539e8f7593653c0c96bb8954d1e1edcd76f44c575d4ea8fd7040ed8afa3be27a.jpg)

Manual Rev.: 1.1

Revision Date: December 24, 2019

Part No: 50-17056-1010

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.00</td><td>2019-10-22</td><td>Initial release</td></tr><tr><td>1.1</td><td>2019-12-24</td><td>Add support for Intel® CoreTM i5-7440EQ/i3-7100E processors; update BIOS and driver sections</td></tr></table>

# Preface

# Copyright © 2019 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.pxie-3987-3977-3937-50-17056-1010-11/f936cfa8954f962c1099404df4329f14b3d47ab57aec5e3522704f33343807a1.jpg)

Battery Labels (for products with battery)
![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.pxie-3987-3977-3937-50-17056-1010-11/714eb58a967bf8d4c01793f8f6a3491934ab4cc019c12b5b9d682b9f732af170.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.pxie-3987-3977-3937-50-17056-1010-11/473293dff0b93ebcc8952b46cdb7eee06c7a8593cd8736fa80c482142ccdc31f.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.pxie-3987-3977-3937-50-17056-1010-11/fa11266218123180d4a57a02e3293bd44fb472fc7bab7f4502e74e94157d1fda.jpg)

![Abstract geometric pattern with interlocking X and Y shapes (no text or symbols)](.pxie-3987-3977-3937-50-17056-1010-11/4f23302d54ae372478340f4560bcf07a7305aa000d05f2a6ea373c77ac9a53db.jpg)

ᘄ㟁ụㄳᅇᨲ

# California Proposition 65 Warning

![A yellow triangular warning sign featuring a thick black border and a centered black exclamation point.](.pxie-3987-3977-3937-50-17056-1010-11/bd25148f56395db551ecb011f52d7170788280a84c0d0b568c5ee3ddc704f369.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a digital icon of a document. It depicts a white sheet of paper with a folded top-left corner and faint gray horizontal lines running across it. A large, bold red checkmark is superimposed diagonally over the document.](.pxie-3987-3977-3937-50-17056-1010-11/f4a3f9827fd03ec0616383634efbfb857aa4940ed764ac3ab6f8749ab8dd2968.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign with a thick black border. Inside the triangle, there is a centered black exclamation mark.](.pxie-3987-3977-3937-50-17056-1010-11/3f8f96c37111503bb7a664be7638b94880a3361bb3d9a1fdc42d8b5b43663509.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a red triangular warning sign with a thick white border. Centered inside the red triangle is a large white exclamation mark. The background surrounding the triangle is white.](.pxie-3987-3977-3937-50-17056-1010-11/83b9ffd6abd263a1d30f934ce739e8f3b98eae0aecf5d4daf0a9324d90b8301b.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History........ i

# Preface ............. iii

# Table of Contents..........

# List of Figures ......... ix

# List of Tables ........ . xi

# 1 Introduction ........

1.1 Features..... 2
1.2 Specifications...... 3
1.3 I/O and Indicators . 7

1.3.1 Front Panel ... . 7
1.3.2 GPIB Connector .... .. 10
1.3.3 Reset Button.... ... 11
1.3.4 LED Indicators . ... 11
1.3.5 USB 2.0 Ports ... .. 12
1.3.6 Gigabit Ethernet Ports .. .. 13
1.3.7 USB 3.0 Ports ... ... 14
1.3.8 COM Port... .... 14
1.3.9 Onboard Connections and Settings..... .. 15

# 2 Getting Started ........ 17

2.1 Package Contents .... 17
2.2 Operating System Installation.... 18

2.2.1 Installation Environment . . 19
2.2.2 Installing the PXIe-3987/3977/3937 . .. 20
2.2.3 Replacing the Hard Drive or Solid State Drive ......... 23
2.2.4 Replacing the Battery Backup ...... ... 24

2.2.5 Clearing CMOS.. .... 25

# 3 Driver Installation....... . 27

# A Appendix: PXI Trigger I/O Functions ........ ...29

A.1 Data Types.... . 29
A.2 Function Library ....... . 31

A.2.1 TRIG\_Init .... .... 31
A.2.2 TRIG\_Close.... .... 31
A.2.3 TRIG\_SetSoftTrg ........ .. 32
A.2.4 TRIG\_Trigger\_Route ... .. 33
A.2.5 TRIG\_Trigger\_Clear ..... ... 35
A.2.6 TRIG\_GetSoftTrg....... ... 35
A.2.7 TRIG\_Trigger\_Route\_Query ...... .. 36
A.2.8 TRIG\_GetDriverRevision.. .. 38

# B Appendix: BIOS Setup.......... ..39

B.1 Entering the BIOS... . 39
B.2 Navigation... 40
B.3 Menu Structure ... . 41
B.4 Main .. . 42

B.4.1 BIOS Information .... .. 42
B.4.2 Processor Information... .. 42
B.4.3 PCH Information .... .. 43
B.4.4 System Management.. .. 43
B.4.5 System Date and Time .... .. 46

B.5 Advanced.. . 47

B.5.1 CPU Configuration..... .. 47
B.5.2 Memory Configuration ..... .. 49
B.5.3 Graphics Configuration.... .. 49
B.5.4 USB Configuration.. .. 50
B.5.5 TPM 2.0 Configuration.. .. 51
B.5.6 Onboard Devices Configuration.... .. 52

B.5.7 PCI and PCIe Configuration ... .. 53
B.5.8 Advanced Power Management ... 53
B.5.9 Network Stack Configuration .... .. 54
B.5.10 Hardware Health Configuration .... . 54
B.5.11 PXIe Links Control Configuration .... . 54

B.6 Security ....... 55
B.6.1 Secure Boot.. .. 55
B.7 Boot .. 56
B.7.1 CSM... .. 57
B.7.2 UEFI Hard Disk Drive BBS Priorities ..... .. 57
B.8 Save & Exit ... 58
C Appendix: Dual BIOS ..... ...... 59
D Appendix: Legacy Boot Mode Settings.................. ........ 61
Important Safety Instructions ...... 63
Getting Service.......... 65

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# List of Figures

Figure 1-1: Functional Block Diagram.. 3
Figure 1-2: Front Panel .. 7
Figure 1-3: PXI Trigger SMB Jack . 8
Figure 1-4: DisplayPort Connector... 9
Figure 1-5: GPIB Connector... .. 10
Figure 1-6: LED Indicators ... .. 11
Figure 1-7: COM Port... .. 14
Figure 1-8: Onboard Configuration ... .. 15
Figure B-1: BIOS Setup Navigation.. .. 40

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# List of Tables

Table 1-1: Front Panel Legend .
Table 1-2: DisplayPort Pin Assignment 9
Table 1-3: GPIB Pin Description... . 10
Table 1-4: LED Indicator Legend.. . 11
Table 1-5: USB 2.0 Port Pin Assignment.. .. 12
Table 1-6: Ethernet Port Pin Assignments. . 13
Table 1-7: Ethernet Status LED Descriptions .. . 13
Table 1-8: D-sub COM Port Signal Functions.. . 14
Table 1-9: Onboard Configuration Legend . . 15
Table B-1: BIOS Hot Key Functions.. .. 40

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# 1 Introduction

The ADLINK PXIe-3987/3977/3937 PXI Express embedded controller is based on the seventh generation Intel® Core™ processor specifically designed for PXI Express-based testing systems. A rugged and stable operating environment is provided for a variety of testing and measurement applications.

Combining state-of-the-art Intel® Core™ processors and up to 32GB of DDR4 2400MHz memory, the PXIe-3987/3977/3937 utilizes multiple computing engines on a single processor, enabling execution of four independent tasks simultaneously. With a configurable PCIe switch, the PXIe-3987/3977/3937 can support four links x4 or two links x8 x16 PXI Express link capability, with maximum system throughput of up to 16 GB/s (PCI Express 3.0).

PXI Express-based testing systems typically make up a PXI Express platform and diversified standalone instruments for complex testing tasks. The PXIe-3987/3977/3937 series provides ample interfaces, including two DisplayPort connectors, allowing connection to two monitors, dual USB 3.0 connections for high speed peripheral devices, dual Gigabit Ethernet ports, one for LAN connection and the other for controlling LXI instruments, four USB 2.0 ports for peripheral devices and USB instrument control, an SMB connector for configurable input/output routing of signal to/ from PXI Trigger Bus on PXI Express chassis, and a Micro-D GPIB connector for GPIB instrument connection, for hybrid PXIbased testing system control.

![The image displays a white icon of a sheet of paper with a folded top-left corner and faint horizontal lines indicating text. A large, solid red checkmark is superimposed over the document, angled diagonally from the bottom left to the top right.](.pxie-3987-3977-3937-50-17056-1010-11/18b3410ff23f4e8535f00153e9637cd981927dcc6bc99cfd6ebd6a2f3e2224d9.jpg)
NOTE:

Memory addressing over 4 GB is OS-dependent, such that a 32-bit operating system may be unable to address memory space over 4GB. To fully utilize memory, 64-bit operating systems are required.

# 1.1 Features

 PXI-5 PXI Express Hardware Specification Rev.1.0
 7th Generation Intel® Core™ processors
 PXIe-3987: Intel® Core™ i7-7820EQ 3.0/3.7 GHz (Turbo), 45W/35W (cTDP, 4C/GT2)
 PXIe-3977: Intel® Core™ i5-7440EQ 2.9/3.6 GHz (Turbo), 45W/35W (cTDP, 4C/GT2)
 PXIe-3937: Intel® Core™ i3-7100E 2.9 GHz, 35W (2C/GT2)

 Dual Channel DDR4 SO-DIMM
 Up to 32 GB 2400 MHz

 Maximum System Throughput 16 GB/s

 PXI Express Link Capability  4-link Configuration: x4 x4 x4 x4  2-link Configuration: x16 x8

 Preinstalled 240 GB SATA SSD  Supports 2.5” HDD or SSD  SATA 6.0 Gb/s  Supports AHCI

 Integrated I/O  Dual Gigabit Ethernet ports  Two USB 3.0 Ports  Four USB 2.0 Ports  Built-in GPIB (IEEE488) controller  Dual DisplayPort connectors  One COM port (D-sub9 serial)  Trigger I/O for advanced PXITM trigger functions

 OS Microsoft Windows 10 64-bit

# 1.2 Specifications

![**Labeled Blocks:**\n\n*   **Front Panel Connectors** (container box)\n    *   DisplayPort Connector x2\n    *   GPIB Connector\n    *   GbE Connector\n    *   GbE Connector\n    *   USB 3.0 Connector x2\n    *   USB 2.0 Connector x4\n    *   COM Port Connector (RS-232/422/485)\n    *   SMB Connector\n*   GPIB Controller\n*   GbE Controller I219\n*   GbE Controller I210\n*   LCP-COM Port\n*   Mobile 7th Gen Intel® Core i3/i5/i7 Processor (formerly 'Kaby Lake-H')\n*   Mobile Intel® QM175/HM175 Chipset\n*   DDR4 2133/2400 MHz SODIMM x2\n*   PCI Express Switch (PCI Express 3.0)\n*   2.5' SATA Storage\n*   SMBus Controller\n*   Programmable MUX\n*   Rear Connectors to PXI Express Chassis\n\n**Connections:**\n\n*   **DisplayPort Connector x2** connects via 'DP/HDMI Dual Mode' to the **Mobile 7th Gen Intel® Core Processor**.\n*   **GPIB Connector** connects via double arrow to **GPIB Controller**, which connects via 'PCIe x1' to the **Mobile Intel® QM175/HM175 Chipset**.\n*   **GbE Connector** connects via double arrow to **GbE Controller I219**, which connects via 'PCIe x1' to the **Chipset**.\n*   **GbE Connector** connects via double arrow to **GbE Controller I210**, which connects via 'PCIe x1' to the **Chipset**.\n*   **USB 3.0 Connector x2** connects via 'USB 3.0' to the **Chipset**.\n*   **USB 2.0 Connector x4** connects via 'USB 2.0' to the **Chipset**.\n*   **COM Port Connector (RS-232/422/485)** connects via double arrow to **LCP-COM Port**, which connects via 'LPC' to the **Chipset**.\n*   **SMB Connector** connects via 'Trigger Signal' to **Programmable MUX**.\n*   **Mobile 7th Gen Processor** connects via 'Intel FDI' and 'DMI 3.0' (double arrows) to the **Chipset**.\n*   **Mobile 7th Gen Processor** connects via 'Memory Bus' (double arrow) to **DDR4 2133/2400 MHz SODIMM x2**.\n*   **Mobile 7th Gen Processor** connects via 'PCIe 3.0 x16' (double arrow) to **PCI Express Switch (PCI Express 3.0)**.\n*   **Chipset** connects via 'SATA' to **2.5' SATA Storage**.\n*   **Chipset** connects via 'PCIe x1' to the block containing **SMBus Controller** and **Programmable MUX**.\n*   **PCI Express Switch** connects via 'PCIe 3.0 2 Link Mode (x16 x8) or PCIe 3.0 4 Link Mode (x4 x4 x4 x4)' (double arrow) to **Rear Connectors to PXI Express Chassis**.\n*   **SMBus Controller** connects via 'SMBus' to **Rear Connectors to PXI Express Chassis**.\n*   **Programmable MUX** connects via 'Trigger Bus' to **Rear Connectors to PXI Express Chassis**.](.pxie-3987-3977-3937-50-17056-1010-11/4b77582904cbf22ccaced71123ce9b1b0a1c249291e6567b50788b11a62a7111.jpg)

Figure 1-1: Functional Block Diagram

# Processor

 7th Generation Intel® Core™ processor
 DMI (Direct Media Interface) 3.0 with 8 GT/s bandwidth in each direction

# Chipset

Mobile Intel® QM175/HM175 chipset

# Memory

 Two standard 260-pin DDR4 SO-DIMM sockets
 Supports 2133/2400 MHz RAM up to 32 GB total
 Supports non-ECC, unbuffered memory

![The image displays a white document icon featuring horizontal grey lines and a folded top-left corner, overlaid with a large, red checkmark.](.pxie-3987-3977-3937-50-17056-1010-11/45f2f0931eb9450b5115ed551f5edbb9fa695d8b7d0210d825f866c81e033775.jpg)
NOTE:

The externally accessible SO-DIMM socket can accept replacement DDR4 DRAM DIMM modules.

PXIe-3987/3977/3937 specifications and stability guarantees are only supported when ADLINK-provided DDR4 DRAM SO-DIMM modules are used.

# Video

 DisplayPort resolution up to 3840 x 2160 @ 60 Hz
 DVI (with passive DisplayPort-to-DVI adapter) resolution up to 1920 x 1200 @ 60 Hz

![The image displays a white document icon with a curled top-left corner and faint horizontal gray lines, overlaid with a large red checkmark.](.pxie-3987-3977-3937-50-17056-1010-11/f589c837ad7ab7cd334e8807509f66ffaa46deaf0283c5beedd4092062c7ac3f.jpg)
NOTE:

DisplayPort adapters for other standards are available, with maximum available resolution dependent on the adapter

# Storage

Built-in 2.5” 500 GB SATA hard drive or 240 GB SATA solid state hard drive.

# Ethernet Connectivity

Dual Gigabit Ethernet controllers through two RJ-45 connectors with speed/link/active LED on the faceplate, with both supporting Wake on LAN.

# USB

Four USB 2.0 and two USB 3.0 ports on the faceplate.

# GPIB

Onboard IEEE488 GPIB controller through Micro-D 25-pin connector on the faceplate.

# Trigger I/O

One SMB connector on the faceplate to route an external trigger signal to/from PXI trigger bus.

# Dimensions (3U PXI module)

3U/4-slot PXI standard

# Weight

1.0 kg (exclusive of packaging)

Environmental

<table><tr><td>Condition</td><td>Range</td></tr><tr><td>Operating temperature with SSD</td><td>0 to 55°C</td></tr><tr><td>Operating temperature with HDD</td><td>0 to 50°C</td></tr><tr><td>Storage temperature</td><td>-20 to 70°C</td></tr><tr><td>Relative humidity, non-condensing</td><td>5 to 95%</td></tr></table>

# Shock and Vibration

Functional shock 30 G, half-sine, 11 ms pulse duration

Random vibration:

 Operating: 5 to 500 Hz, 0.21 Grms, 3 axes
 Non-operating: 5 to 500 Hz, 2.46 Grms, 3 axes

![The image displays a white document icon with a folded top-right corner and faint horizontal lines suggesting text. Overlaid on the document is a large, bold red checkmark. There is no readable text in the image.](.pxie-3987-3977-3937-50-17056-1010-11/0697516077144a93c84ebaff097be4f664f610467b123e9870e032e108481aee.jpg)
NOTE:

Environmental, shock, and vibration values are only valid with use of an ADLINK-provided SSD/HDD

# Certifications

Electromagnetic compatibility:

 EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
 EN 55011 (CISPR 11): Group 1, Class A emissions
 EN 55032 2015/AC: 2016 Class A
 EN 55032 2015/AC: 2016 Class B
 EN 55024 2010+ A1: 2015
 EN 61000-3-2:2014: Class A
 EN 61000-3-3:2013: Class A
 EN 55024:2010+A1:2015: Immunity
 FCC 47 CFR Part 15 Subpart A (Class A)
 FCC 47 CFR Part 15 Subpart B (Class B)
 ICES-001 Class A
 ICES-003 Issue 6-2016
 AS/NZS CISPR 11: Group 1, Class A emissions
 AS/NZS CISPR 32: 2015 (Ed 2.0)/C1:2016: Class B

The PXIe-3987/3977/3937 meets the essential requirements of applicable European Directives.

Power Requirements

<table><tr><td>Typical Consumption</td><td>DC +3.3V</td><td>DC +5V</td><td>DC +12V</td></tr><tr><td>Typical operation(Measured while W10 is idle)</td><td>5A</td><td>2.5A</td><td>2A</td></tr><tr><td>Heavy operation(Measured while W10 is under heavy CPU and storage utilization)</td><td>5A</td><td>2.8A</td><td>8A</td></tr></table>

# 1.3 I/O and Indicators

# 1.3.1 Front Panel

![ADLINK\nPXIe-3987\nHD USR\nPXIe Embedded\nController\nPW\nI\nH\nG\nTRIG\nSS\nCOM\nE\nF\nGPIB](.pxie-3987-3977-3937-50-17056-1010-11/50b6ee8ec06a7e4d9c29c6ff7718d167364dc571693701c69fbf9ac4ba10dce0.jpg)

Figure 1-2: Front Panel

<table><tr><td>A</td><td>Reset Button</td><td>F</td><td>GPIB Connector (Micro D-Sub 25P)</td></tr><tr><td>B</td><td>2X DisplayPort</td><td>G</td><td>2X Gigabit Ethernet</td></tr><tr><td>C</td><td>2X USB 3.0</td><td>H</td><td>PXI Trigger</td></tr><tr><td>D</td><td>4X Type-A USB 2.0</td><td rowspan="2">I</td><td rowspan="2">LED indicators</td></tr><tr><td>E</td><td>COM port (D-sub9 serial)</td></tr></table>

Table 1-1: Front Panel Legend

# PXI Trigger Connector

![Ground\nTrigger](.pxie-3987-3977-3937-50-17056-1010-11/17f6d6d6f8614ea30698bd050b194f29d954493560cc003fdcc295eac58193c8.jpg)

Figure 1-3: PXI Trigger SMB Jack

The PXI trigger connector is an SMB jack, used to route external trigger signals to or from the PXI backplane. Trigger signals are TTL-compatible and edge sensitive. The PXIe-3987/3977/3937 provides four trigger routing modes from/to the PXI trigger connector to synchronize PXI modules, including

 From a selected trigger bus line to PXI trigger connector
 From the PXI trigger connector to a selected trigger bus line
 From software trigger to a selected trigger bus line
 From software trigger to PXI trigger connector

All trigger modes are programmable by the provided driver.

# DisplayPort Connectors

Provide monitor connection with installation of requisite adapters required if connecting to VGA/DVI/HDMI monitors. Dual display function is also supported.

![19\n1\n20\n2](.pxie-3987-3977-3937-50-17056-1010-11/14350d6ce9e9b645fcbfb4019442b3fc2ba35d29d20b061bb8ec79bc6938eef2.jpg)

Figure 1-4: DisplayPort Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CN_DDPx0+</td><td>11</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>12</td><td>CN_DDPx3-</td></tr><tr><td>3</td><td>CN_DDPx0-</td><td>13</td><td>CN_DDPx_AUX_SEL</td></tr><tr><td>4</td><td>CN_DDPx1+</td><td>14</td><td>CN_DDPx_CONFIG2</td></tr><tr><td>5</td><td>GND</td><td>15</td><td>CN_DDPx_AUX+</td></tr><tr><td>6</td><td>CN_DDPx1-</td><td>16</td><td>GND</td></tr><tr><td>7</td><td>CN_DDPx2+</td><td>17</td><td>CN_DDPx_AUX-</td></tr><tr><td>8</td><td>GND</td><td>18</td><td>CN_DDPx_HPD</td></tr><tr><td>9</td><td>CN_DDPx2-</td><td>19</td><td>GND</td></tr><tr><td>10</td><td>CN_DDPx3+</td><td>20</td><td>+V3.3_DDPx_PWR</td></tr></table>

Table 1-2: DisplayPort Pin Assignment

# 1.3.2 GPIB Connector

The GPIB connector is a micro D-sub 25P connector, controlling external bench-top instruments. Connection to other instruments requires the optional ACL-IEEE488-MD1-A cable. The onboard GPIB controller provides:

 Full compatibility with IEEE 488 standard
 Up to 1.5 MB/s data transfer rates
 Onboard 2 KB FIFO for read/write operations
 Driver APIs are compatible with NI-488.2 driver software
 Connection with up to 14 instruments

![1\n13\n14\n25](.pxie-3987-3977-3937-50-17056-1010-11/3abd01bd8c45a63f14a2e76ca895988c1c7fea61f546e930643ee14d2b5fe10a.jpg)

Figure 1-5: GPIB Connector

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DIO1#</td><td>GPIB Data 1</td><td>14</td><td>DIO5#</td><td>GPIB Data 5</td></tr><tr><td>2</td><td>DIO2#</td><td>GPIB Data 2</td><td>15</td><td>DIO6#</td><td>GPIB Data 6</td></tr><tr><td>3</td><td>DIO3#</td><td>GPIB Data 3</td><td>16</td><td>DIO7#</td><td>GPIB Data 7</td></tr><tr><td>4</td><td>DIO4#</td><td>GPIB Data 4</td><td>17</td><td>DIO8#</td><td>GPIB Data 8</td></tr><tr><td>5</td><td>EOI</td><td>End Or Identify</td><td>18</td><td>REN</td><td>Remote Enable</td></tr><tr><td>6</td><td>DAV</td><td>Data Valid</td><td>19</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>7</td><td>NRFD</td><td>Not Ready For Data</td><td>20</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>8</td><td>NDAC</td><td>No Data Accepted</td><td>21</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>9</td><td>IFC</td><td>Interface Clear</td><td>22</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>10</td><td>SRQ</td><td>Service Request</td><td>23</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>11</td><td>ATN</td><td>Attention</td><td>24</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>12</td><td>Chassis Ground</td><td>Chassis Ground</td><td>25</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>13</td><td>Ground</td><td>Signal Ground</td><td></td><td></td><td></td></tr></table>

Table 1-3: GPIB Pin Description

# 1.3.3 Reset Button

The reset button, activated by insertion of any pin-like implement, executes a hard reset for the PXIe-3987/3977/3937.

# 1.3.4 LED Indicators

Three LED indicators on the faceplate indicate operational status of the PXIe-3987/3977/3937, as follows.

![HD USR\n● ○\nPW ●](.pxie-3987-3977-3937-50-17056-1010-11/4a72a3e3faa308cd075e392fdc60c14aa738b99e51d40073bd75e3bd4d714a98.jpg)

Figure 1-6: LED Indicators

<table><tr><td>LED</td><td>Color</td><td>Description</td></tr><tr><td>PW</td><td>Green</td><td>Indicates system power, remaining lit when the system boots normally and main power supply is functioning.</td></tr><tr><td>HD</td><td>Yellow</td><td>Indicates operating state of the HDD or SSD, flashing during access to or activity on the SATA HDD.</td></tr><tr><td>USR</td><td>Blue</td><td>User-programmable LED indicator.</td></tr></table>

Table 1-4: LED Indicator Legend

# 1.3.5 USB 2.0 Ports

The PXIe-3987/3977/3937 provides four USB 2.0 ports via USB Type-A connectors on the faceplate, all compatible with hi-speed, full-speed and low-speed USB devices. Supported boot devices include USB flash drive, USB floppy, USB CD-ROM, and others, with boot priority and device settings configured in BIOS. See section B.7: "Boot" on page 56 for more information.

![Pure electrical connector pinout diagram without any text or symbols](.pxie-3987-3977-3937-50-17056-1010-11/a6f1ec871e8ff06572bc5de2bb649b2bbf1837b6a65254cab5a0ba35d6558426.jpg)

![1\n2\n3\n4](.pxie-3987-3977-3937-50-17056-1010-11/01b2b9727f0ebb1d5409576e9a52da67fbb631a9ea70ed194f0ba46f3de1719f.jpg)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1/5</td><td>Power 5V</td></tr><tr><td>2/6</td><td>USB Data-</td></tr><tr><td>3/7</td><td>USB Data +</td></tr><tr><td>4/8</td><td>Ground</td></tr></table>

Table 1-5: USB 2.0 Port Pin Assignment

# 1.3.6 Gigabit Ethernet Ports

Dual Gigabit Ethernet connection is provided on the PXIe-3987/ 3977/3937 front panel.

<table><tr><td>Pin</td><td>1000Base-T Signal</td><td>100/10Base-T Signal</td></tr><tr><td>1</td><td>MDI0+</td><td>TX+</td></tr><tr><td>2</td><td>MDI0-</td><td>TX-</td></tr><tr><td>3</td><td>MDI1+</td><td>RX+</td></tr><tr><td>4</td><td>MDI2+</td><td>Reserved</td></tr><tr><td>5</td><td>MDI2-</td><td>Reserved</td></tr><tr><td>6</td><td>MDI1-</td><td>RX-</td></tr><tr><td>7</td><td>MDI3+</td><td>Reserved</td></tr><tr><td>8</td><td>MDI3-</td><td>Reserved</td></tr></table>

Table 1-6: Ethernet Port Pin Assignments

Each Ethernet port includes two LED indicators, one Active/Link indicator and one Speed indicator, functioning as follows.

<table><tr><td></td><td>LED</td><td>Status</td><td>Description</td></tr><tr><td rowspan="6">&lt;img src="images/7dc6db09a69181c96c4653e2ff948b7a775be1035bde8032baee6a243292b6f2.jpg"/&gt;</td><td rowspan="3">Active/Link (Yellow)</td><td>Off</td><td>Ethernet port is disconnected</td></tr><tr><td>On</td><td>Ethernet port is connected with no data transmission</td></tr><tr><td>Flashing</td><td>Ethernet port is connected with data transmitted/received</td></tr><tr><td rowspan="3">Speed (Green/Orange)</td><td>Off</td><td>10 Mbps</td></tr><tr><td>Green</td><td>100 Mbps</td></tr><tr><td>Orange</td><td>1000 Mbps</td></tr></table>

Table 1-7: Ethernet Status LED Descriptions

# 1.3.7 USB 3.0 Ports

The PXIe-3987/3977/3937 provides two Type-A USB 3.0 ports on the front panel, supporting SuperSpeed, Hi-Speed, full-speed, and low-speed downstream transmission. Multiple boot devices, including USB flash, USB external HD, and USB CD-ROM drives are supported, with boot priority configured in BIOS.

![The image displays a white document icon with its top-left corner folded down. Faint gray horizontal lines are visible on the paper, suggesting text. A large, bold red checkmark is superimposed over the document.](.pxie-3987-3977-3937-50-17056-1010-11/524826cb953100932f989a3e6bd7766cda0b478f768836ddb4fc234999e98816.jpg)
NOTE:

USB 3.0 may not be supported by the OS installation programs/environment. Use USB 2.0 ports for OS installation if necessary.

# 1.3.8 COM Port

A COM port on the front panel with D-sub 9P connectors supports RS-232/RS-422/RS-485 by BIOS selection.

![1\n5\n6\n9](.pxie-3987-3977-3937-50-17056-1010-11/cfbbcd5df7ad128d53fbaddaa0932393b8f866ce62777b4255622638ef2cf234.jpg)

Figure 1-7: COM Port

<table><tr><td rowspan="2">Pin</td><td colspan="3">Signal Name</td></tr><tr><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>TXD422-</td><td>485DATA-</td></tr><tr><td>2</td><td>RXD</td><td>TXD422+</td><td>485DATA+</td></tr><tr><td>3</td><td>TXD</td><td>RXD422+</td><td>N/S</td></tr><tr><td>4</td><td>DTR#</td><td>RXD422-</td><td>N/S</td></tr><tr><td>5</td><td>GND</td><td>N/S</td><td>N/S</td></tr><tr><td>6</td><td>DSR#</td><td>N/S</td><td>N/S</td></tr><tr><td>7</td><td>RTS#</td><td>N/S</td><td>N/S</td></tr><tr><td>8</td><td>CTS#</td><td>N/S</td><td>N/S</td></tr><tr><td>9</td><td>RI#</td><td>N/S</td><td>N/S</td></tr></table>

Table 1-8: D-sub COM Port Signal Functions

# 1.3.9 Onboard Connections and Settings

![ADLINK\nTECHNOLOGY CARD\nWD Blue®\n500GB\nA\nB\nC\nA\nB\nC\n1734NC\nR10B\nR27\nR10D\n0.47uH\n1734NC\nR10B\nR27\nR10D\nR528\nSWT\nTC9\nR521\nC6\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n335\nR10B\nR27\nR10D\nR528\nSWT\nC6\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330\n330](.pxie-3987-3977-3937-50-17056-1010-11/f4daa8ea6d55e56222c24fd8efef1faab5008ff15ef2309c8980164cca43a5c1.jpg)

Figure 1-8: Onboard Configuration

<table><tr><td>A</td><td>Clear CMOS switch</td></tr><tr><td>B</td><td>SATA connector</td></tr><tr><td>C</td><td>System battery</td></tr></table>

Table 1-9: Onboard Configuration Legend

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# 2 Getting Started

This chapter describes procedures for installing the PXIe-3987/ 3977/3937 and making preparations for its operation, including hardware and software setup. Note that the PXIe controller is shipped with RAM and an HDD or SSD preinstalled. Contact ADLINK or an authorized dealer if there are any problems during the installation.

![The image displays a digital icon of a white document or piece of paper with a folded top-left corner. Faint horizontal lines are visible across the page, suggesting text or a list. A large, red checkmark is superimposed over the center of the document, indicating approval or completion.](.pxie-3987-3977-3937-50-17056-1010-11/c027a47fe77d98d825060518c78ed636eaf814184abb0c6a78c7c252fadff4da.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Package Contents

Before beginning, check the package contents for any damage and ensure that the following items are included:

 PXIe-3987/3977/3937 Controller (equipped with RAM and HDD or SSD)
 PXIe-3987/3977/3937 Quick Start Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

![The image shows a triangular warning symbol with a thick black border and a dark red background. Inside the triangle is a white exclamation point. Below the triangle, the word 'WARNING:' is printed in black, uppercase letters.](.pxie-3987-3977-3937-50-17056-1010-11/ae6e796fae6f3a413954d17e93e230d73dd68e9e0b9dca5e08a7b266eb5b1490.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Contact an ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Operating System Installation

For more detailed information about the operating system, refer to the documentation provided by the operating system manufacturer. Preferred/supported operating systems for the PXIe controller are:

 Windows 10 64-bit
 For other OS support, contact ADLINK

Most operating systems require initial installation from a hard drive, floppy drive, or CD-ROM drive. The PXIe controller supports USB CD-ROM drive, USB flash disk, USB external hard drive, or a USB floppy drive as the first boot device. See section B.7: "Boot" on page 56 for information about setting the boot devices. These devices should be configured, installed, and tested with the supplied drivers before attempting to load the new operating system.

![The image displays a white document icon with a folded top-right corner. Faint horizontal lines run across the page, and a large, bold red checkmark is superimposed over the center.](.pxie-3987-3977-3937-50-17056-1010-11/b883c2246bb2f834835cb57117ed5261eba7257ec9a603c26c190db90e61809d.jpg)
NOTE:

Read the release notes and installation documentation provided by the operating system vendor. Be sure to read all the README files or documents provided on the distribution disks, as these typically note documentation discrepancies or compatibility problems.

1. Select the appropriate boot device order from the BIOS Boot Setup Menu based on the OS installation media used. For example, if the OS is distributed on a bootable installation CD, select USB CD-ROM as the first boot device and reboot the system with the installation CD in the USB CD-ROM drive.
2. Proceed with the OS installation as directed and be sure to select appropriate device types if prompted. Refer to the appropriate hardware manuals for specific device types and compatibility modes of ADLINK PXI products.
3. When installation is complete, reboot the system and set the boot device order in the BIOS Boot Setup Menu accordingly.

# 2.2.1 Installation Environment

When preparing to install any equipment described in this manual, first refer to Important Safety Instructions.

Only install equipment in well lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools include:

 Phillips (cross-head) screwdriver
 Flat-head screwdriver
 Anti-static wrist strap
 Anti-static mat

ADLINK PXIe system controllers are electrostatically sensitive and can be easily damaged by static electricity. The equipment must be handled on a grounded anti-static mat, and operators must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling may cause damage to the contents. Ensure that all contents are undamaged before installing.

![A yellow triangular warning sign with a black border containing a black exclamation point, with the text 'CAUTION:' printed below it in black capital letters.](.pxie-3987-3977-3937-50-17056-1010-11/6e51e55c364a6e3faa8aec2cceaed3f7a7a04010733b0411225ebabc0d647b8b.jpg)

All equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the antistatic bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing or installing.

# 2.2.2 Installing the PXIe-3987/3977/3937

1. Remove all screw caps (x4).

![The image displays a four-panel instructional diagram illustrating hardware assembly, comparing the use of alignment pins versus screws.\n\n**Top Row:**\n*   **Left Panel:** A metal enclosure houses a green circuit board. Two red circles highlight black, cylindrical alignment pins—one inserted near the top interior corner and another lower down on a metal bracket. The circuit board has 'CE' printed on it.\n*   **Right Panel:** A red arrow points from the left panel. The same view shows the black pins replaced by silver screws in the corresponding circled locations.\n\n**Bottom Row:**\n*   **Left Panel:** A similar view of the assembly shows black alignment pins highlighted by red circles—one near the top left and another lower down on a bracket.\n*   **Right Panel:** A red arrow points from the left panel. The black pins are replaced by silver screws in the circled areas.](.pxie-3987-3977-3937-50-17056-1010-11/e431c0f7caf666274f0d63a4301059a3fc56a406aec6512ef8e3470059670189.jpg)

2. Release the red locking lever.

![Close-up of a black mechanical device with red and black components, showing a red arrow pointing to a specific area (no text or symbols visible)](.pxie-3987-3977-3937-50-17056-1010-11/de2f82f6b8bcb43ebb2a431280b19f43336315d04ca83f3b96ac55d49199350e.jpg)

3. Depress the latch.

![Close-up of a mechanical device with a red arrow pointing to a red component, no visible text or symbols.](.pxie-3987-3977-3937-50-17056-1010-11/ebe9835186b273c3a0ba338b621ed2fa1a42a3fc0e3a039ee4a779458b258b4a.jpg)

4. Locate the system controller slot of the chassis (Slot 1).

![ADLINK\n1\n2 H\n3 H\n4 H](.pxie-3987-3977-3937-50-17056-1010-11/1088f15c237c06b8f87e5b08d2fe24a8cb7cb0e7f059da7b11cb2a0cd8e3e06c.jpg)

5. Align the controller’s top and bottom edges with the card guides, and carefully slide the PXIe-3987/3977/3937 into the chassis, as shown.

![ADLINK\n2 H 3 H 4 H\nADLINK\n01/01/01-01-01\n01/01/01-01-01\n01/01/01-01-01\n01/01/01-01-01\n01/01/01-01-01\n01/01/01-01-01\n01/01/01-01-01\n01/01/01](.pxie-3987-3977-3937-50-17056-1010-11/947804a4e3e414ea389a123992b8a484fb9ed30c1dc38b630d9fc246be3f1f79.jpg)

![Close-up of a computer printer's internal structure with a red circle highlighting a component, no visible text or symbols.](.pxie-3987-3977-3937-50-17056-1010-11/49fe9cc5b3fca48eae55a8e849fe937f89fa90ee99dcc7d8e8a9a76d7351165e.jpg)

6. Elevate the latch until the PXIe-3987/3977/3937 is fully seated in the chassis backplane. The alignment pin on the rear of the latch can be threaded into the best fit alignment port in the chassis rail.
7. Fasten the four mounting screws on the faceplate and connect all peripheral devices.

# 2.2.3 Replacing the Hard Drive or Solid State Drive

The PXIe controller provides a SATA 3.0 port with a pre-installed 2.5" SATA hard drive or solid state drive. Replacing the HDD or SSD is accomplished as follows.

1. Locate the five screws attaching the hard drive housing to the PXIe controller, as shown.

![WD Blue™\n500GB\nW550001.PCX\nSIN 19X1486LTDIC\nAdvanced Power Grid, To volume 6x performance\n- Window 9.7' multi-position and closing software 200V-140\n- HDI 3.0' 1.0' 1.0' 1.0' 1.0' 1.0' 1.0' 1.0' 1.0'\nE2:200\nE2:200\nWSP - 60K\nWST - 100K\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWLD 19X1486LTDIC\nWD Blue™\nWLD 330 GB / WVD\nGNDN: A/B\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB\nPDC: 3.0 GB](.pxie-3987-3977-3937-50-17056-1010-11/3fde3bbc9eaa0eb06332eaf033ed285081f6c05f171e40c3bd06a4e406f6b3dc.jpg)

2. Remove the screws.
3. Gently lift and remove the housing with the installed HDD or SSD.

4. Locate the four screws (two on each side, as shown) fixing the hard drive, and remove them.

![0025-T5S-AE\nSF D6Y17EJ\nZ060-00025-001 REV/P2\nE20 E29 E74\nE30 E44 E78 R72 E55\nE32 E53\nE46 E49 E71 E6\nE73 E75 E73\nE74 E76 E72 E68 E60 E58 E55\nE80 E82 E84 E10 E12\nE86 E90 E92 E94\nE96 E10 E12\nE13 E15 E17 E19\nE18 E20 E22 E24 E26\nE28 E30 E32 E34\nE36 E38 E40 E42\nE38 E44 E46 E48\nE40 E42 E44\nE42 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E44\nE44 E8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE8\nE10\nE12\nE13\nE15\nE17\nE19\nE21\nE23\nE25\nE27\nE29\nE31\nE33\nE35\nE37\nE39\nE41\nE43\nE45\nE47\nE49\nE51\nE53\nE55\nE57\nE59\nE61\nE63\nE65\nE67\nE69\nE71\nE73\nE75\nE77\nE79\nE81\nE83\nE85\nE87\nE89\nC1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99](.pxie-3987-3977-3937-50-17056-1010-11/e0fcdba4f3b75b44f8185e7242c692ac39bb958f0f51008882c580c07e16e4fd.jpg)

5. To install an HDD, SSD, or other compatible SATA hard drive, reverse the steps and reinstall the PXIe controller into the PXI system.

# 2.2.4 Replacing the Battery Backup

The PXIe-3987/3977/3937 is provided with a 3.0 V “coin cell” lithium battery, replacement of which is as follows.

1. Turn off the PXI chassis.
2. Remove the PXIe controller from the chassis. Observe all anti-static precautions.
3. To remove the battery, gently insert a small (approx. 5 mm) flathead screwdriver under the battery at the negative retaining clip. Gently pry up and the battery should easily pop out.

4. Place a fresh identical battery (CR2032 or equivalent) in the socket, ensuring that the positive pole (+) is facing upwards. The battery is most easily seated by first being inserted under the positive retaining clip, and then pushed downward at the negative retaining clip. The battery should easily snap into position.

5. Reinstall the PXIe controller into the PXI chassis and restore power.

# 2.2.5 Clearing CMOS

In the event of a system malfunction causing the PXIe controller to halt or fail to boot, clear the CMOS and restore the controller BIOS to its default settings. To clear the CMOS:

1. Shut down the controller operating system and turn off the PXI Chassis.
2. Remove the PXIe controller from the chassis. Observe all anti-static precautions.
3. Locate the CMOS clear switch (SW1) on the board (see section 1.3.9: "Onboard Connections and Settings" on page 15). Move the switch from the Normal position...

![The image displays a zoomed-in crop of a digital interface element, likely a progress bar or slider. It features a dark gray horizontal rectangular track. Inside the track, the majority of the area is filled with a medium gray color, transitioning into a white rectangular section on the far right. A small white dot is visible on the left side of the track. Above the main bar is a solid black strip. There is no text present in the image.](.pxie-3987-3977-3937-50-17056-1010-11/bc0ae92858be175c59e5a92bb8ad2a9e8a392b32f88b0cb5ea8b4f49c3ea713e.jpg)

...to the Clear position.

![This image displays a horizontal slider interface element. It features a dark grey rectangular track set against a lighter grey background. On the far left side of the track, there is a white square thumb (handle). Directly beneath the left edge of this white square is a small, solitary white dot. Above the slider mechanism is a dark grey horizontal bar.](.pxie-3987-3977-3937-50-17056-1010-11/329f23c8f4fffea510c345e14894b5eb4ec2716afc63477efd5881d265436dd7.jpg)

Wait five seconds, then return the switch to the Normal position.

![This image displays a cropped close-up of a user interface element, appearing to be a slider or progress bar, set against a dark grey background. It features a horizontal rectangular track divided into a larger medium-grey section on the left and a smaller white section on the right. Below the left end of the track, there is a small white circular knob. There is no text visible in the image.](.pxie-3987-3977-3937-50-17056-1010-11/b1ece22b458f527105cd49f34b31c800f96972a0af569620df2f37a0efd8e108.jpg)

4. Remount the controller into the PXI chassis.
5. Press &lt;Delete&gt; or &lt;ESC&gt; to enter BIOS Setup when the splash logo appears.
6. Press &lt;F9&gt; to load optimized defaults in BIOS Setup.
7. Modify the system date and time.
8. Press &lt;F10&gt; to save configuration and exit.

# 3 Driver Installation

Windows 10 already carries most of the device drivers required by the PXIe-3987/3977/3937. Others can be downloaded from the ADLINK website after clicking “Driver” on any of the product pages for this series (the files are exactly the same for each product):

www.adlinktech.com/Products/PXI\_PXIe/PXIControllers/PXIe-3987 www.adlinktech.com/Products/PXI\_PXIe/PXIControllers/PXIe-3977 www.adlinktech.com/Products/PXI\_PXIe/PXIControllers/PXIe-3937

Use of Windows 10 requires the following drivers:

 Chipset Driver
 Graphics Driver
 Ethernet/LAN Driver
 PXI Trigger I/O Driver
 Intel ME Driver
 GPIB Driver
 Intel RST Driver

The following optional utility programs are also provided:

 MAPS Core Windows Software Suite for ADLINK Measurement, Automation, and PXI products
 PXI Platform Services

After downloading and extracting a given file, run the executable and follow its instructions to complete installation.

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# Appendix A PXI Trigger I/O Functions

This appendix describes use of the PXI trigger I/O function library for the PXIe-3987/3977/3937 controller, to program routing of trigger signals between the trigger I/O SMB connector on the faceplate and the PXI trigger bus on the backplane. API files are located in the installation directory of the PXI Trigger I/O driver.

# A.1 Data Types

The PXIe-3987/3977/3937 library uses these data types in pxitrigio.h in the directory X:\ADLINK\PXI Trigger IO\Include. It is recommended that you use these data types in your application programs. The table shows the data type names, ranges, and corresponding data types in C/C++, Visual Basic, and Delphi for reference.

<table><tr><td rowspan="2">Type</td><td rowspan="2">Description</td><td rowspan="2">Range</td><td colspan="3">Type</td></tr><tr><td>C/C++ (for 32-bit compiler)</td><td>Visual Basic</td><td>Pascal (Delphi)</td></tr><tr><td>U8</td><td>8-bit ASCII character</td><td>0 to 255</td><td>unsigned char</td><td>Byte</td><td>Byte</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td><td>short</td><td>Integer</td><td>SmallInt</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td><td>unsigned short</td><td>Not supported by BASIC, use the signed integer (I16) instead</td><td>Word</td></tr><tr><td>I32</td><td>32-bit signed integer</td><td>-2147483648 to 2147483647</td><td>long</td><td>Long</td><td>LongInt</td></tr><tr><td>U32</td><td>32-bit unsigned integer</td><td>0 to 4294967295</td><td>unsigned long</td><td>Not supported by BASIC, use the signed long integer (I32) instead</td><td>Cardinal</td></tr><tr><td>F32</td><td>32-bit single-precision floating-point</td><td>-3.402823E38 to 3.402823E38</td><td>float</td><td>Single</td><td>Single</td></tr><tr><td>F64</td><td>64-bit double-precision floating-point</td><td>1.7976831348 62315E308 to 1.7976831348 62315E309</td><td>double</td><td>Double</td><td>Double</td></tr></table>

# A.2 Function Library

This section provides detailed definitions of the functions available in the PXIe-3987/3977/3937 function library. Each function includes a description, list of supported cards, syntax, parameter list and Return Code information.

# A.2.1 TRIG\_Init

# Description

Initializes trigger I/O function of PXIe-3987/3977/3937 controller. TRIG\_Init must be called before the invocation of any other trigger I/O function.

# Syntax

C/C++

I16 TRIG\_Init()

Visual Basic

TRIG\_Init As Integer

# Parameter

None

# Return Code

ERR\_NoError

ERR\_BoardBusy

ERR\_OpenDriverFail

ERR\_GetGPIOAddress

# A.2.2 TRIG\_Close

# Description

Closes trigger I/O function of PXIe-3987/3977/3937 controller, releasing resources allocated for the trigger I/O function. Users must invoke TRIG\_Close before exiting the application.

# Syntax

C/C++

I16 TRIG\_Close()

# Visual Basic

TRIG\_Close() As Integer

# Parameter

# None

# Return Code

ERR\_NoError

ERR\_BoardNoInit

# A.2.3 TRIG\_SetSoftTrg

# Description

Generates a TTL trigger signal to the trigger I/O SMB connector on the faceplate or the PXI trigger bus on the backplane by software command.

# Syntax

C/C++

I16 TRIG\_SetSoftTrg(U8 Status)

# Visual Basic

TRIG\_SetSoftTrg (ByVal status As Byte) As Integer

# Parameters

# Status

Logic level of trigger signal.

Available value description:

0: Logic low

1: Logic high

# Return Code

ERR\_NoError

ERR\_BoardNoInit

# A.2.4 TRIG\_Trigger\_Route

# Description

Routes the trigger signal between the trigger I/O SMB connector on the faceplate and the PXI trigger bus on the backplane. This function also allows routing of the softwaregenerated trigger signal to SMB connector or trigger bus.

# Syntax

C/C++

I16 TRIG\_Trigger\_Route (U32 source, U32 dest, U32 halfway)

# Visual Basic

TRIG\_Trigger\_Route (ByVal source As Long, ByVal dest As Long, ByVal halfway As Long) As Integer

# Parameters

source

Source of trigger routing can be one of the following values.

<table><tr><td>Available value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>SMB connector on the faceplate</td></tr><tr><td>PXI_TRIG_VAL_SOFT</td><td>Software-generated trigger signal</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>PXI trigger bus #0</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>PXI trigger bus #1</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>PXI trigger bus #2</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>PXI trigger bus #3</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>PXI trigger bus #4</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>PXI trigger bus #5</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>PXI trigger bus #6</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>PXI trigger bus #7</td></tr></table>

#

Destination of trigger routing can be one of the following.

<table><tr><td>Available value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>SMB connector on the faceplate</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>PXI trigger bus #0</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>PXI trigger bus #1</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>PXI trigger bus #2</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>PXI trigger bus #3</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>PXI trigger bus #4</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>PXI trigger bus #5</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>PXI trigger bus #6</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>PXI trigger bus #7</td></tr></table>

# halfway

Halfway point of trigger routing. This parameter is used only to route the software-generated trigger signal to the SMB connector on the faceplate. In this case, the halfway should be set as one of the trigger bus lines, otherwise as PXI\_TRIG\_VAL\_NONE.

<table><tr><td>Available value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>No halfway point</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>PXI trigger bus #0</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>PXI trigger bus #1</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>PXI trigger bus #2</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>PXI trigger bus #3</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>PXI trigger bus #4</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>PXI trigger bus #5</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>PXI trigger bus #6</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>PXI trigger bus #7</td></tr></table>

# Return Code

ERR\_NoError

ERR\_BoardNoInit

ERR\_Set\_Path

# A.2.5 TRIG\_Trigger\_Clear

# Description

Clears the trigger routing setting.

# Syntax

C/C++

I16 TRIG\_Trigger\_Clear()

Visual Basic

TRIG\_Trigger\_Clear() As Integer

# Parameters

None

# Return Code

ERR\_NoError

ERR\_BoardNoInit

ERR\_Trigger\_Clr

# A.2.6 TRIG\_GetSoftTrg

# Description

Acquires the current software trigger state, with default state after system boot of Logic Low.

# Syntax

C/C++

I16 TRIG\_GetSoftTrg(U8 \*Status)

Visual Basic

TRIG\_GetSoftTrg (status As Byte) As Integer

# Parameters

Status

Returns the logic level of software trigger signal.

Returned value:

0: Logic low

1: Logic high

# Return Code

```txt
ERR_NoError
ERR_BoardNoInit
ERR_Query_Status
```

# A.2.7 TRIG\_Trigger\_Route\_Query

# Description

Acquires the current trigger signal routing path.

# Syntax

```txt
C/C++
```

```txt
I16 TRIG_Trigger_Route_Query (U32* source, U32* dest, U32* halfway)
```

# Visual Basic

TRIG\_Trigger\_Route\_Query (source As Long, dest As Long, halfway As Long) As Integer

# Parameters

source

Returns to the current source of trigger routing, with possible values including:

<table><tr><td>Available Definition</td><td>Defined Value</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>0</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>2</td></tr><tr><td>PXI_TRIG_VAL_SOFT</td><td>3</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>111</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>112</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>113</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>114</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>115</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>116</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>117</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>118</td></tr></table>

# dest

Returns to the current destination of trigger routing, with possible values including:

<table><tr><td>Available Definition</td><td>Defined Value</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>0</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>2</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>111</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>112</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>113</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>114</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>115</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>116</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>117</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>118</td></tr></table>

# halfway

Returns to the current halfway point of trigger routing, with possible values including:

<table><tr><td>Available Value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>0</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>111</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>112</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>113</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>114</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>115</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>116</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>117</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>118</td></tr></table>

# Return Code

ERR\_NoError

ERR\_BoardNoInit

ERR\_Query\_Status

# A.2.8 TRIG\_GetDriverRevision

# Description

Acquires the PXI Trigger software driver version; format of the version number is major.minor1.minor2.

# Syntax

```txt
C/C++
```

```txt
I16 TRIG_GetDriverRevision(unsigned short *major, unsigned short *minor1, unsigned short *minor2)
```

# Visual Basic

```txt
TRIG_GetDriverRevision (major As Integer, minor1 As Integer, minor2 As Integer) As Integer
```

# Parameters

```txt
major
```

Returns the major version number of the pxi trigger software driver

```txt
minor1
```

Returns the first minor version number of the pxi trigger software driver

```txt
minor2
```

Returns the second minor version number of the pxi trigger software driver

# Return Code

```txt
ERR_NoError
```

```txt
ERR_Query_Revision
```

# Appendix B BIOS Setup

# B.1 Entering the BIOS

1. Power on or reboot the PXIe-3987/3977/3937 controller.
2. Press the &lt;Delete&gt; or &lt;Esc&gt; key when the controller beeps. This should be concurrent with the main startup screen. The BIOS setup program loads after a short delay.
3. The Main menu is displayed when you first enter the BIOS setup program.

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this chapter.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# B.2 Navigation

The BIOS setup utility uses a key-based navigation system called hot keys. Most hot keys can be used at any time during navigation.

<table><tr><td>Key(s)</td><td>Function</td></tr><tr><td>Right Arrow, Left Arrow</td><td>Moves between different setup menus</td></tr><tr><td>Up Arrow, Down Arrow</td><td>Moves between options within a setup menu</td></tr><tr><td></td><td>Opens a sub-menu or displays all available settings for a highlighted configuration option</td></tr><tr><td></td><td>Returns to the previous menu and shortcuts to the Exit menu from top-level menus</td></tr><tr><td>&lt;+&gt; and &lt;--&gt;</td><td>Cycles between all available settings</td></tr><tr><td></td><td>Selects time and date fields</td></tr><tr><td></td><td>Opens the general help window for the BIOS</td></tr><tr><td></td><td>Loads previous values into the BIOS</td></tr><tr><td></td><td>Restores optimal default values into the BIOS</td></tr><tr><td></td><td>Saves the current configuration and exits BIOS setup</td></tr></table>

Table B-1: BIOS Hot Key Functions

![This flowchart describes the navigation of a BIOS Setup Utility.\n\n**Blocks:**\n*   BIOS Setup Utility\n*   Screens\n*   Left and Right Keys to Select a Setup Screen\n*   Screen 1\n*   Screen 2\n*   Screen 3\n*   Screen 4\n*   Screen 5\n*   Items\n*   Tab Key to Select Fields\n*   Fields\n*   ± To Change Field Values\n*   Up and Down Keys to Select a Setup Item\n*   (Six square boxes containing the '±' symbol)\n\n**Connections:**\n*   **BIOS Setup Utility** points down to **Screens**.\n*   **Left and Right Keys to Select a Setup Screen** connects via a dotted arrow to the area above the screen row.\n*   **Screen 1** connects to **Screen 2** via a double-headed arrow.\n*   **Screen 2** connects to **Screen 3** via a double-headed arrow.\n*   **Screen 3** connects to **Screen 4** via a double-headed arrow.\n*   **Screen 4** connects to **Screen 5** via a double-headed arrow.\n*   **Screens** points down to **Items**.\n*   **Tab Key to Select Fields** connects via a dotted arrow to **Items**.\n*   **Fields** is a label with a bracket pointing to the group of boxes below.\n*   The top row consists of three boxes with the '±' symbol, connected by double-headed arrows. **± To Change Field Values** connects via a dotted arrow to this row.\n*   The bottom row consists of three boxes with the '±' symbol, connected by double-headed arrows.\n*   Between the top and bottom rows of boxes are a downward arrow and an upward arrow. **Up and Down Keys to Select a Setup Item** connects via a dotted arrow to these vertical arrows.](.pxie-3987-3977-3937-50-17056-1010-11/7f35247db0eeb8cfd7e161515897184fe35949bf00ae0a91d6c8e86df57a2529.jpg)

Figure B-1: BIOS Setup Navigation

![The image shows a white document icon with a folded top-right corner and faint horizontal lines, featuring a large red checkmark overlaid on it.](.pxie-3987-3977-3937-50-17056-1010-11/727ec42b94da8141432a4292351a5057dbdd25a0ca21ef8a08bc20f8333c0a92.jpg)
NOTE:

A hot key legend is located in the right frame on most setup screens.

# B.3 Menu Structure

This section presents the primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The sub-sections that follow provide further details for each top-level menu and sub-menu and the setting options for each menu item. Default setting options are presented in bold and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>BIOS Information Processor Information PCH Information System Management ▶ System Date and Time</td></tr><tr><td>Advanced</td><td>CPU Configuration ▶ Memory Configuration ▶ Graphics Configuration ▶ USB Configuration ▶ TPM 2.0 Configuration ▶ Onboard Devices Configuration ▶ PCI and PCIe Configuration ▶ Advanced Power Management ▶ Network Stack Configuration ▶ Hardware Health Configuration ▶ PXIe Links Control Configuration ▶</td></tr><tr><td>Security</td><td>Password Description Administrator Password User Password Secure Boot ▶</td></tr><tr><td>Boot</td><td>Boot Configuration CSM ▶ FIXED BOOT ORDER Priorities UEFI Hard Disk Drive BBS Priorities ▶</td></tr><tr><td>Save &amp; Exit</td><td>Save Options Default Options Boot Override</td></tr></table>

Note: ► indicates a sub-menu

# B.4 Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details about each section/sub-menu.

# B.4.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>Core Version</td><td>Info only</td><td>Displays Core version</td></tr><tr><td>Compliancy</td><td>Info only</td><td>Displays compliance information</td></tr><tr><td>Project Version</td><td>Info only</td><td>ADLINK BIOS version</td></tr><tr><td>Build Date and Time</td><td>Info only</td><td>Date the ADLINK BIOS was built</td></tr><tr><td>Access Level</td><td>Info only</td><td>Current BIOS menu access permission</td></tr><tr><td>Link Cap</td><td>Info only</td><td>PCI Express link configuration to PXIe chassis2 link configuration: x8 x164 link configuration: x4 x4 x4 x4</td></tr></table>

# B.4.2 Processor Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Name</td><td>Info only</td><td>Displays CPU brand name</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Displays CPU signature</td></tr><tr><td>CPU Speed</td><td>Info only</td><td>Displays CPU frequency</td></tr><tr><td>Processor ID</td><td>Info only</td><td>Displays CPU ID</td></tr><tr><td>Stepping</td><td>Info only</td><td>Displays CPU stepping</td></tr><tr><td>Number of Processors</td><td>Info only</td><td>Displays number of processors</td></tr><tr><td>GT Info</td><td>Info only</td><td>Displays GT info of Intel Graphics</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Graphics Output Protocol version</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Displays memory version</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Displays installed memory size</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Displays memory frequency</td></tr></table>

# B.4.3 PCH Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Name</td><td>Info only</td><td>Displays PCH name</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Displays PCH SKU</td></tr><tr><td>Stepping</td><td>Info only</td><td>Displays PCH stepping</td></tr><tr><td>LAN PHY Revision</td><td>Info only</td><td>Displays LAN PHY revision</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Displays version of ME</td></tr><tr><td>ME Firmware SKU</td><td>Info only</td><td>Displays ME Firmware Kit SKU number</td></tr></table>

# B.4.4 System Management

The System Management sub-menu contains the following six sub-menus with read-only system information as well as the option to change the machine’s Power-up Mode.

# B.4.4.1 Board Information

<table><tr><td>Board Information</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Firmware</td><td>Info only</td><td>Displays SEMA firmware</td></tr><tr><td>Build Date</td><td>Info only</td><td>Displays SEMA firmware build date</td></tr><tr><td>SEMA Boot Loader</td><td>Info only</td><td>Displays SEMA boot loader</td></tr><tr><td>Build Date</td><td>Info only</td><td>Displays SEMA boot loader build date</td></tr><tr><td>Hardware Version</td><td>Info only</td><td>Displays SEMA hardware version</td></tr><tr><td>Serial Number</td><td>Info only</td><td>Displays SEMA S/N</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Displays SEMA manufacture date</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Displays last SEMA repair date</td></tr><tr><td>MAC ID</td><td>Info only</td><td>Displays SMC MAC ID</td></tr></table>

# B.4.4.2 Temperatures

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">CPU Temperature</td></tr><tr><td>Current</td><td>Info only</td><td>Displays current CPU temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Displays CPU startup temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Displays min. CPU temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Displays max. CPU temperature</td></tr><tr><td colspan="3">Board Temperature</td></tr><tr><td>Current</td><td>Info only</td><td>Displays current board temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Displays board startup temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Displays min. board temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Displays max. board temperature</td></tr></table>

# B.4.4.3 Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Current Input Current</td><td>Info only</td><td>Displays input current</td></tr><tr><td>Current Input Power</td><td>Info only</td><td>Displays input power</td></tr><tr><td>VCORE</td><td>Info only</td><td>Displays actual voltage of the VCC_CORE</td></tr><tr><td>VGFX</td><td>Info only</td><td>Displays actual voltage of the VGFX</td></tr><tr><td>VMEM</td><td>Info only</td><td>Displays actual voltage of the VMEM</td></tr><tr><td>5VSB</td><td>Info only</td><td>Displays actual voltage of the 5VSB</td></tr><tr><td>VIN</td><td>Info only</td><td>Displays actual voltage of the VIN</td></tr><tr><td>5V</td><td>Info only</td><td>Displays actual voltage of the 5V</td></tr><tr><td>3.3V</td><td>Info only</td><td>Displays actual voltage of the 3.3V</td></tr><tr><td>3.3VSB</td><td>Info only</td><td>Displays actual voltage of the 3.3VSB</td></tr></table>

# B.4.4.4 Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Total Runtime</td><td>Info only</td><td>Specifies the total time in minutes the system has spent running in S0 state</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>Specifies the time in seconds the system has been running in S0 state, where the counter is cleared when the system is removed from the external power supply</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>Specifies the number of times external power has been shut off</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>Boot count is increased after a HW- or SW-Reset or successful power-up</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>Shows the event responsible for reboot of the system</td></tr></table>

# B.4.4.5 Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BMC Flags</td><td>Info only</td><td></td></tr><tr><td>BIOS Select</td><td>Info only</td><td>Displays the current BIOS ROM selection</td></tr><tr><td>ATX/AT-Mode</td><td>Info only</td><td>Displays ATX/AT mode</td></tr><tr><td>Exception Code</td><td>Info only</td><td>System exception reason</td></tr></table>

# B.4.4.6 Power Up

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power-up Mode(only in effect if the module is in ATX-Mode)</td><td>Turn onRemain offLast state</td><td>Turn on: The machine starts automatically when the power supply is turned onRemain off: The power button must be pressed to start the machineLast state: When power is lost and then restored, the machine will either turn on or remain off according to its last power state</td></tr></table>

# B.4.5 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock in hours, minutes, and seconds</td></tr></table>

# B.5 Advanced

Provides settings for most user interfaces in the system.

B.5.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Signature</td><td>Info only</td><td>Displays CPU signature</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Displays microcode revision</td></tr><tr><td>CPU Speed</td><td>Info only</td><td>Displays CPU operating frequency</td></tr><tr><td>Processor Cores</td><td>Info only</td><td>Displays Processor Cores</td></tr><tr><td>Hyper Threading Technology</td><td>Info only</td><td>Displays presence/absence of Intel Hyper Threading support</td></tr><tr><td>VMX</td><td>Info only</td><td>Displays presence/absence of Intel Virtualization Technology support</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Displays presence/absence of Intel SMX Technology support</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>Hyper-Threading</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and disabled for other OS (not optimized); when Disabled only one thread per enabled core is active</td></tr><tr><td>VT-d</td><td>Disabled Enabled</td><td>Enables/disables VT-d function on MCH</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled Enabled</td><td>Enables/disables support for Intel Virtualization technology</td></tr><tr><td>Intel® SpeedStep(TM)</td><td>Disabled Enabled</td><td>Allows support for more than two frequency ranges</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Enables/disables turbo mode</td></tr><tr><td>Configurable TDP Boot Mode</td><td>NominalDownUpDeactivated</td><td>Configures TDP Mode as Nominal/Down/Up/Deactivated, where Deactivated sets MSR to Nominal and MMI/O to Zero</td></tr><tr><td>Configurable TDP Lock</td><td>DisabledEnabled</td><td>Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL When CTDP Lock is enabled, Custom ConfigTDP Count defaults to 1 and Custom ConfigTDP Boot Index to 0</td></tr><tr><td>Custom Configurable TDP</td><td>DisabledEnabled</td><td>Custom Configurable TDP settings</td></tr><tr><td>C States</td><td>EnabledDisabled</td><td>Enables/disables CPU C states</td></tr><tr><td>Package C State Limit</td><td>CPU DefaultC7C6C3C2C0/C1</td><td>Maximum Package C State limit</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enables/disables Intel Trusted Execution Technology</td></tr><tr><td>DTS SMM</td><td>DisabledEnabledCritical Temp Reporting (out of spec)</td><td>Disabled: ACPI thermal management uses EC reported temperatureEnabled: ACPI thermal management uses DTS SMM mechanism to determine CPU temperatureOut of Spec: ACPI thermal management uses EC reported temperature and DTS SMM is used to handle Out of Spec</td></tr><tr><td>ACPI T-States</td><td>DisabledEnabled</td><td>Enables/disables ACPI 3.0 T-States</td></tr></table>

# B.5.2 Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Displays Memory Reference Code version</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Displays memory frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Displays total memory</td></tr><tr><td>DIMM#0/1</td><td>Info only</td><td>Displays DIMM#0/1</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Displays memory timings</td></tr></table>

# B.5.3 Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Selects Graphics Translation Table size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512M1024MB2048MB</td><td>Selects Aperture size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0MB32MB64MB</td><td>Selects DVMT Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128MB256MBMAX</td><td>Selects DVMT Total Graphics Memory size used by the Internal Graphics Device</td></tr></table>

B.5.4 USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Module Version</td><td>Info only</td><td></td></tr><tr><td>USB Devices</td><td>Info only</td><td>Lists USB-connected peripheral devices</td></tr><tr><td>USB Controllers</td><td>Info only</td><td>Display USB Controller type</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables legacy USB support, where Auto disables legacy support if no USB devices are connected, and Disable retains USB devices only for EFI applications and setup</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>A workaround for OS without XHCI hand-off support. XHCI ownership change should be claimed by the XHCI OS driver</td></tr><tr><td>USB Mass Storage Driver Support</td><td>EnabledDisabled</td><td>Enables/disables USB Mass Storage driver support</td></tr><tr><td>Port 60/64 Emulation</td><td>EnabledDisabled</td><td>Enables I/O port 60h/64h emulation; should be enabled for complete USB keyboard legacy support for non-USB aware OS</td></tr><tr><td>USB Transfer Timeout</td><td>1 sec5 sec10 sec20 sec</td><td>Timeout value for Control, Bulk, and Interrupt transfers</td></tr><tr><td>Device Reset Timeout</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command timeout</td></tr><tr><td>Device Power-up Delay</td><td>AutoManual</td><td>Maximum time before the device properly reports itself to the Host Controller. &#x27;Auto&#x27; uses default value: for a Root port, 100 ms, for a Hub port the delay is taken from the Hub descriptor</td></tr></table>

B.5.5 TPM 2.0 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable Enable</td><td>Enable or disable BIOS support for security device</td></tr><tr><td>Active PCR Banks</td><td>Info only</td><td></td></tr><tr><td>Available PCR Banks</td><td>Info only</td><td></td></tr><tr><td>SHA-1 PCR Bank</td><td>Enabled Disabled</td><td>Enable or disable SHA-1 PCR Bank</td></tr><tr><td>SHA-256 PCR Bank</td><td>Enabled Disabled</td><td>Enable or disable SHA-256 PCR Bank</td></tr><tr><td>Pending Operation</td><td>None TPM Clear</td><td>Schedule an operation for the security device</td></tr><tr><td>Platform Hierarchy</td><td>Disabled Enabled</td><td>Enable or disable storage hierarchy</td></tr><tr><td>Storage Hierarchy</td><td>Disabled Enabled</td><td>Enable or disable storage hierarchy</td></tr><tr><td>Endorsement Hierarchy</td><td>Disabled Enabled</td><td>Enable or disable endorsement hierarchy</td></tr><tr><td>TPM2.0 UEFI Spec Version</td><td>TCG_1_2 TCG_2</td><td>TCG_1_2: Win8/10 compatibility mode TCG_2: New protocol and event format for Win10 or later</td></tr><tr><td>Physical Presence Spec Version</td><td>1.2 1.3</td><td>Instruct OS to support PPI spec version 1.2 or 1.3 (note that some HCK tests might not support version 1.3)</td></tr><tr><td>TPC 20 InterfaceType</td><td>Info only</td><td></td></tr></table>

# B.5.6 Onboard Devices Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Serial Port Configuration</td></tr><tr><td>COM Device Settings</td><td>Info only</td><td>Serial port I/O address and IRQ</td></tr><tr><td>COM Control</td><td>RS232RS422RS485</td><td>Selects serial port mode, from among RS232, RS422, and RS485</td></tr><tr><td colspan="3">LAN Port Configuration</td></tr><tr><td>LAN1 Controller</td><td>EnabledDisabled</td><td>Enables/disables onboard I219 LAN controller</td></tr><tr><td>LAN2 Controller</td><td>EnabledDisabled</td><td>Enables/disables onboard I210 LAN controller</td></tr><tr><td colspan="3">SATA Configuration</td></tr><tr><td>SATA Controller(s)</td><td>EnabledDisabled</td><td>Enables/disables SATA device</td></tr><tr><td>SATA Signal Setting</td><td>HDDSSD</td><td>Sets SATA signaling for optional HDD and SSD</td></tr><tr><td>Serial ATA Port X</td><td>Info only</td><td>Installed SATA device name</td></tr><tr><td>Software Preserve</td><td>Info only</td><td>Bootable OS in installed SATA device</td></tr><tr><td>Port X</td><td>DisabledEnabled</td><td>Enables/disables SATA port</td></tr></table>

B.5.7 PCI and PCIe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Above 4G Decoding</td><td>Disabled Enabled</td><td>Enables/disables Memory Mapped I/O BIOS assignment above 4GB</td></tr><tr><td>Holdoff Timer</td><td>0,1,2,3,4,5,6,7,8 sec</td><td>System delay for PCI Express Discovery</td></tr><tr><td>Native PCIe Enable</td><td>Disabled Enabled</td><td>Enables/disables native PCIe</td></tr><tr><td colspan="3">PEG Port Configuration</td></tr><tr><td>PEG 0:1:0</td><td>Info only</td><td>Information about PCI express mode and link to the PCI Express bus root</td></tr><tr><td>Max Link Speed</td><td>Auto Gen1 Gen2 Gen3</td><td>Sets maximum PCI Express link capability of the PCI Express bus root</td></tr></table>

B.5.8 Advanced Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Wake System from S5</td><td>DisabledFixed TimeDynamic Time</td><td>Enables/disables system wake on alarm event, from among Fixed Time, where system wakes at the setting time, and Dynamic Time, in which system wakes at setting time later</td></tr><tr><td>PCIe Wake</td><td>EnabledDisabled</td><td>Enables/disables PCI Express bus and onboard LAN2 Controller (I210) wake capability</td></tr><tr><td>I219 LAN Wake</td><td>EnabledDisabled</td><td>Enables/disables onboard LAN1 Controller (I219) wake capability</td></tr></table>

# B.5.9 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Enabled Disabled</td><td>Enables/disables UEFI network stack</td></tr><tr><td>IPv4 PXE Support</td><td>Enabled Disabled</td><td>Enables/disables IPv4 PXE boot support</td></tr><tr><td>IPv6 PXE Support</td><td>Enabled Disabled</td><td>Enables/disables IPv6 PXE boot support</td></tr><tr><td>PXE Boot Wait Time</td><td>0 sec</td><td>Wait time for ESC key to abort PXE boot</td></tr></table>

# B.5.10 Hardware Health Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Ambient temp of PCIe switch</td><td>Info only</td><td>Ambient temperature near PCIe switch</td></tr><tr><td>Core temp of PCIe switch</td><td>Info only</td><td>Core temperature of PCIe switch</td></tr><tr><td>+3.3V(System)</td><td>Info only</td><td>System +3.3V voltage</td></tr><tr><td>+5V(System)</td><td>Info only</td><td>System +5V voltage</td></tr><tr><td>+12V(System)</td><td>Info only</td><td>System +12V voltage</td></tr><tr><td>VBAT</td><td>Info only</td><td>Battery voltage</td></tr></table>

# B.5.11 PXIe Links Control Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Link Configuration</td><td>Info only</td><td>PCI Express link configuration to PXIe chassis</td></tr><tr><td>Link 1 Width, Speed</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Maximum PCI Express link mode for Link 1</td></tr><tr><td>Link 2 Width, Speed</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Maximum PCI Express link mode</td></tr></table>

# B.6 Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td>Provides information about password characteristics as well as password length requirements: min. 3, max. 20</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>If ONLY the Administrator Password is set, then this only limits access to BIOS Setup and is only asked for when entering BIOS Setup</td></tr><tr><td>User Password</td><td>Enter password</td><td>If ONLY the User Password is set, then this is a power on password and must be entered to boot as well as to enter BIOS Setup and while in BIOS Setup the User will have Administrator rights</td></tr><tr><td>Secure Boot</td><td>Sub-menu</td><td>See section B.6.1 below</td></tr></table>

# B.6.1 Secure Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Attempt Secure Boot</td><td>Disabled Enabled</td><td>Determines whether Secure Boot will be attempted</td></tr></table>

# B.7 Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Boot Configuration</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key; to wait indefinitely, set to 65536 (0xFFFF)</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Set keyboard NumLock state at boot</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enable or disable Quiet Boot option</td></tr><tr><td>CSM</td><td>Sub-menu</td><td>See section B.7.2 on page 57</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enable or disable boot with initialization of a minimal set of devices required to launch active boot option; has no effect for BBS boot options</td></tr><tr><td>Boot Mode Select</td><td>UEFI Legacy</td><td></td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Boot Option #1 to Boot Option #8</td><td>Select which potential boot sources should be checked, and in what order, during the boot process</td></tr><tr><td>UEFI Hard Disk Drive BBS Priorities</td><td>Sub-menu</td><td>See section B.7.2 on page 57</td></tr></table>

B.7.1 CSM

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>EnabledDisabled</td><td>Determines whether CSM will launch</td></tr><tr><td>CSM16 Module Version</td><td>Info only</td><td>Displays the CSM16 module version number</td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>UPON REQUEST means GA20 can be disabled using BIOS services, ALWAYS means GA20 cannot be disabled; useful when any RT code is executed above 1MB</td></tr><tr><td>INT19 Trap Response</td><td>ImmediatePostponed</td><td>BIOS reaction on INT19 trapping by Option ROM; IMMEDIATE executes trap immediately and POSTPONED executes trap during legacy boot</td></tr><tr><td>Boot Option Filter</td><td>UEFI andLegacyLegacy onlyUEFI only</td><td>Controls to which devices the system can boot</td></tr><tr><td colspan="3">Option ROM Execution</td></tr><tr><td>Network</td><td>Do not launchLegacy onlyUEFI only</td><td>Controls execution of UEFI and Legacy PXE OpROM</td></tr><tr><td>Storage</td><td>Do not launchUEFILegacy only</td><td>Controls execution of UEFI and Legacy Storage OpROM</td></tr><tr><td>Video</td><td>Do not launchUEFILegacy only</td><td>Controls execution of UEFI and Legacy Video OpROM</td></tr><tr><td>Other PCI Devices</td><td>UEFILegacy</td><td>For PCI devices other than Network, Mass Storage, or Video, defines the OpROM to launch</td></tr></table>

B.7.2 UEFI Hard Disk Drive BBS Priorities

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Option</td><td>Windows Boot Manager Disable</td><td>Allows specification of a UEFI HDD BBS priority boot option</td></tr></table>

# B.8 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Save Options</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Saves changes and exits system setup</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Discards changes and exits system setup</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Saves changes and resets system</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Discards changes and resets system</td></tr><tr><td>Save Changes</td><td></td><td>Save changes made so far to setup options</td></tr><tr><td>Discard Changes</td><td></td><td>Discards changes made so far to setup options</td></tr><tr><td colspan="3">Default Options</td></tr><tr><td>Restore Defaults</td><td></td><td>Restores/loads default values for all setup options</td></tr><tr><td>Save as User Defaults</td><td></td><td>Saves changes made so far as User Defaults</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restores User Defaults to all setup options</td></tr><tr><td colspan="3">Boot Override</td></tr><tr><td>Launch EFI Shell from filesystem device</td><td></td><td>Attempts to launch EFI shell application (shell.efi) from an available filesystem device</td></tr></table>

# Appendix C Dual BIOS

Dual BIOS is a backup function that maintains normal operation of the PXIe system module when unexpected boot failure occurs under the default BIOS. Dual BIOS consists of a main BIOS, a backup BIOS, and an independent controller. In normal boot, the main BIOS powers on and boots the system into the OS, monitored by the independent controller. If the main BIOS malfunctions, for example, as the result of corruption incurred by a failed update, boot procedure is terminated abnormally. The backup BIOS is then activated automatically to perform boot procedure. When backup BIOS is activated, during BIOS power-on, notifications are generated indicating that backup BIOS has been deployed. To restore main BIOS function, contact technical support.

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# Appendix D Legacy Boot Mode Settings

UEFI boot mode is default for the PXIe-3987/3977/3937 BIOS.

To boot in legacy boot mode, change related settings in the BIOS menu:

1. Power on and press &lt;DEL&gt; or &lt;ESC&gt; to enter BIOS menu
2. Move to Boot
3. Under “Boot mode select” select “LEGACY”
4. Move to Boot, CSM
5. Under “CSM Support” select “Enabled”
6. Under “Network” select “Legacy”
7. Under “Storage” select “Legacy”
8. Under “Video” select “Legacy”
9. Under “Other PCI devices” select “Legacy”
10.Press &lt;F10&gt; and &lt;Enter&gt; to save and exit BIOS menu. The system will restart and apply settings for Legacy boot mode.

To restore UEFI boot mode:

1. Power on and press &lt;DEL&gt; or &lt;ESC&gt; to enter BIOS menu
2. Press &lt;F9&gt; and &lt;Enter&gt; to load optimized defaults
3. Press &lt;F10&gt; and &lt;Enter&gt; to save and exit BIOS menu

The system restarts and default settings for UEFI boot mode are applied.

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# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.

 Read these safety instructions carefully.
 Keep the User’s Manual for future reference.
 Read the Specifications section of this manual for detailed information on the recommended operating environment.
 The device can be operated at an ambient temperature of 55ºC.

When installing/mounting or uninstalling/removing device, or when removal of a chassis cover is required for user servicing (See “Getting Started” on page 17.):

 Turn off power and unplug any power cords/cables.
 Reinstall all chassis covers before restoring power.

 To avoid electrical shock and/or damage to device:

 Keep device away from water or liquid sources.
 Keep device away from high heat or humidity.
 Keep device properly ventilated (do not block or cover ventilation openings).

 Always use recommended voltage and power source settings.

 Always install and operate device near an easily accessible electrical outlet.

 Secure the power cord (do not place any object on/over the power cord).

 Only install/attach and operate device on stable surfaces and/or recommended mountings.

 If the device will not be used for long periods of time, turn off and unplug it from its power source

 Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools

 A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation point. Directly below the triangle is the text 'CAUTION:' in black capital letters.](.pxie-3987-3977-3937-50-17056-1010-11/2d963164ea7686d156e92f56236b10850bd022982570dc02ebfc350fbb00c7e1.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

 The device must be serviced by authorized technicians when:

 The power cord or plug is damaged.
 Liquid has entered the device interior.
 The device has been exposed to high humidity and/or moisture.
 The device is not functioning or does not function according to the User’s Manual.
 The device has been dropped and/or damaged and/or shows obvious signs of breakage.

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

 It is recommended that the device be installed only in a server room or computer room where access is:

 Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.

 Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

<table><tr><td>&lt;img src="images/28f2c5765ce29355033d26aa0e603996e8d95717a58b698380374e3e15ba0aed.jpg"/&gt;</td><td>BURN HAZARDTouching this surface could result in bodily injury.To reduce risk, allow the surface to cool before touching.RISQUE DE BRÛLURESNe touchez pas cette surface, cela pourrait entraîner des blessures.Pour éviter tout danger, laissez la surface refroidir avant de la toucher.</td></tr></table>

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

9F, No.166 Jian Yi Road, Zhonghe District

New Taipei City 235, Taiwan

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

+1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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