# PXIe-3988

# PXI Express Embedded Controller

# User’s Manual

![Exterior view of a ADLINK PCIe-3588 PCI connected controller module (no visible text or symbols on main components)](.pxie-3988-um-50m-00028-1000-10/332baa0e62f8111ede38d540b93ce0970efae48056694816f959ca7e0ae2ec23.jpg)

Manual Rev.: 1.0

Revision Date: July 04, 2021

Part No: 50M-00028-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2021-07-04</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2021 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line, no text or labels present](.pxie-3988-um-50m-00028-1000-10/d4ce6303516de4ba70b6eaf2c535f0667d68cabfad8dd7297a0509cf6b04558d.jpg)

# Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.pxie-3988-um-50m-00028-1000-10/4feb2698099465bac24358864afee5f4663839709e7fe44311de5508893a138e.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.pxie-3988-um-50m-00028-1000-10/219dc21f7b251f5ff7ac4871e367eca9d030f8c318d730d272c21cb282ea88d8.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.pxie-3988-um-50m-00028-1000-10/ccfbc7e0a47881d7185fb7d21db6c48e4ff7b34cf82192d179b66d44c7443ea0.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.pxie-3988-um-50m-00028-1000-10/1b5944edad5df361e1e17aec3756adf1c43c25b5a4af08b8c47117c36457763d.jpg)

ᘄ㟁ụㄳᅇᨲ

# California Proposition 65 Warning

![A yellow triangular warning sign with a black border containing a black exclamation mark in the center.](.pxie-3988-um-50m-00028-1000-10/37ead227a3a4e640b95238b04fa480a55054afea0db6c0eced370872cac0a862.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows a white document icon featuring faint grey horizontal lines representing text. A large red checkmark is superimposed over the center of the document.](.pxie-3988-um-50m-00028-1000-10/332382b35f42dd3c0b78abf0782b12dde15b053f069d9f241678b77009518648.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangle with a thick black border. Centered inside the triangle is a large black exclamation point. The graphic sits against a white background, and black lines extend downward from the bottom corners of the triangle, suggesting this is the upper portion of a warning sign.](.pxie-3988-um-50m-00028-1000-10/9c6bb1652472df89477797857819af144c1ac2543b438378e97399439a00bf15.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image shows a maroon equilateral triangle pointing upward, centered against a white background. Inside the triangle is a large white exclamation point (!). The entire graphic is enclosed within a thin black rectangular border.](.pxie-3988-um-50m-00028-1000-10/1b7897dead9aa7c7229c47bdd5a09efc874501ef90468dbbd6cbbaeb3d261c65.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History....... ii

# Preface ......... iii

# List of Figures ...... ix

# List of Tables ........ .... xi

# 1 Introduction .....

1.1 Features..... 2
1.2 Specifications..... 3
1.3 I/O and Indicators . 7

1.3.1 Front Panel ... . 7
1.3.2 GPIB Connector .... ... 10
1.3.3 Reset Button.... ... 11
1.3.4 LED Indicators . .. 11
1.3.5 USB 2.0 Ports ... .. 12
1.3.6 Gigabit Ethernet Ports .. .. 13
1.3.7 USB 3.0 Ports .... .. 14
1.3.8 COM Port... .... 14
1.3.9 Onboard Connections and Settings..... .. 15

# 2 Getting Started ...... 17

2.1 Package Contents .. . 17
2.2 Operating System Installation.. . 18

2.2.1 Installation Environment . .. 19
2.2.2 Installing the PXIe-3988 .. 20
2.2.3 Replacing the Hard Drive or Solid State Drive ......... 23
2.2.4 Replacing the Battery Backup ....... ... 24
2.2.5 Clearing CMOS . .... 25

# 3 Driver Installation.......... ... 27

# A Appendix: PXI Trigger I/O Functions ........ ...29

A.1 Data Type . . 29
A.2 Function Library ..... 31

A.2.1 TRIG\_Init .... .... 31
A.2.2 TRIG\_Close.... ... 32
A.2.3 TRIG\_SetSoftTrg ........ .... 33
A.2.4 TRIG\_Trigger\_Route .... .. 34
A.2.5 TRIG\_Trigger\_Clear ... .. 36
A.2.6 TRIG\_GetSoftTrg....... ... 37
A.2.7 TRIG\_Trigger\_Route\_Query ..... .. 38
A.2.8 TRIG\_GetDriverRevision.. .. 40

# B Appendix: BIOS Setup........... .....41

B.1 Entering the BIOS .... . 41
B.2 Navigation .... . 42
B.3 Menu Structure .... 43
B.4 Main .. 44

B.4.1 BIOS Information .... .. 44
B.4.2 System Information... .. 44
B.4.3 System Date and Time .. .. 45

B.5 Advanced.. . 46

B.5.1 CPU Configuration..... ... 46
B.5.2 Memory Configuration .... .. 48
B.5.3 Graphics Configuration.... .. 48
B.5.4 USB Configuration.. .. 49
B.5.5 TPM 2.0 Configuration... .. 50
B.5.6 Onboard Devices Configuration... .. 51
B.5.7 PCI and PCIe Configuration . .. 51
B.5.8 Advanced Power Management . .. 52
B.5.9 Network Stack Configuration . .. 52

B.5.10 System Management.. .. 53
B.5.11 Flags ..... .... 53
B.5.12 Power Consumption .... .. 54
B.5.13 Hardware Health Configuration .... .. 55
B.5.14 PXIe Links Control Configuration .... .. 55

B.6 Chipset... 56

B.6.1 System Agent (SA) Configuration.... .. 56
B.6.2 PCH-IO Configuration..... .. 57

B.7 Security ....... 59

B.7.1 Secure Boot.. .. 59

B.8 Boot ... 60

B.8.1 CSM... .. 61
B.8.2 UEFI Hard Disk Drive BBS Priorities ..... .. 61

B.9 Save & Exit .. 62

C Appendix: Dual BIOS ..... ...... 63
D Appendix: Legacy Boot Mode Settings.................. ....... 65

Important Safety Instructions ....... 67

Getting Service.......... 69

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# List of Figures

Figure 1-1: Functional Block Diagram.. 3
Figure 1-2: Front Panel .. 7
Figure 1-3: PXI Trigger SMB Jack . 8
Figure 1-4: DisplayPort Connector... 9
Figure 1-5: GPIB Connector... .. 10
Figure 1-6: LED Indicators ... .. 11
Figure 1-7: COM Port... .. 14
Figure 1-8: Onboard Configuration ... .. 15
Figure B-1: BIOS Setup Navigation.. .. 42

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# List of Tables

Table 1-1: Front Panel Legend .
Table 1-2: DisplayPort Pin Assignment 9
Table 1-3: GPIB Pin Description... . 10
Table 1-4: LED Indicator Legend.. . 11
Table 1-5: USB 2.0 Port Pin Assignment.. .. 12
Table 1-6: Ethernet Port Pin Assignments. . 13
Table 1-7: Ethernet Status LED Descriptions .. . 13
Table 1-8: D-sub COM Port Signal Functions.. . 14
Table 1-9: Onboard Configuration Legend . . 15
Table A-1: Data Type .. . 29
Table B-1: BIOS Hot Key Functions.. .. 42

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# 1 Introduction

The ADLINK PXIe-3988 PXI Express embedded controller is based on the Intel® Xeon® E processor (formerly Coffee Lake) specifically designed for PXI Express-based testing systems. A rugged and stable operating environment is provided for a variety of testing and measurement applications.

Combining state-of-the-art Intel® Core™ processors and up to 64GB of DDR4 2400MHz memory, the PXIe-3988 utilizes multiple computing engines on a single processor, enabling execution of four independent tasks simultaneously. With a configurable PCIe switch, the PXIe-3988 can support four links x4 or two links x8 x16 PXI Express link capability, with maximum system throughput of up to 16 GB/s (PCI Express 3.0).

PXI Express-based testing systems typically make up a PXI Express platform and diversified standalone instruments for complex testing tasks. The PXIe-3988 series provides ample interfaces, including two DisplayPort connectors, allowing connection to two monitors, dual USB 3.0 connections for high speed peripheral devices, dual Gigabit Ethernet ports, one for LAN connection and the other for controlling LXI instruments, four USB 2.0 ports for peripheral devices and USB instrument control, an SMB connector for configurable input/output routing of signal to/from PXI Trigger Bus on PXI Express chassis, and a Micro-D GPIB connector for GPIB instrument connection, for hybrid PXI-based testing system control.

![The image displays a simple graphic icon of a document. It features a white piece of paper with a folded top-right corner and faint horizontal lines running across it. Superimposed over the center of the paper is a large, bold red checkmark.](.pxie-3988-um-50m-00028-1000-10/82b30efbac8e3824585591613ada09ca123f98c664028c1943404ca0bb59e83f.jpg)
NOTE:

Memory addressing over 4 GB is OS-dependent, such that a 32-bit operating system may be unable to address memory space over 4GB. To fully utilize memory, 64-bit operating systems are required.

# 1.1 Features

 PXI-5 PXI Express Hardware Specification Rev.1.0
 Intel® Xeon® E processor E-2276ME (formerly Coffee Lake) 820EQ 2.8/4.5 GHz (Turbo), 45W (cTDP, 6C/GT2)
 Dual Channel DDR4 SO-DIMM  Up to 64 GB 2400 MHz

 Maximum System Throughput 16 GB/s

 PXI Express Link Capability

 4-link Configuration: x4 x4 x4 x4
 2-link Configuration: x16 x8

 SATA Storage (built-in 2.5” 500 GB or 240 GB SATA solid state hard drive)
 Supports 2.5” HDD or SSD
 SATA 6.0 Gb/s
 Supports AHCI

 Integrated I/O

 Dual Gigabit Ethernet ports
 Two USB 3.0 Ports
 Four USB 2.0 Ports
 Built-in GPIB (IEEE488) controller
 Dual DisplayPort connectors
 One COM port (D-sub9 serial)
 Trigger I/O for advanced PXI™ trigger functions

 OS

 Microsoft Windows 10 64-bit

# 1.2 Specifications

![Based on the provided flowchart, here is the accurate and concise description of the labeled blocks and their connections:\n\n**Labeled Blocks**\n*   **Front Panel Connectors** (Grouping box containing: 'DisplayPort Connector x2', 'GPIB Connector', 'GbE Connector' (x2), 'USB3.0 Connector x2', 'USB2.0 Connector x4', 'COM Port Connector (RS-232/422/485)', and 'SMB Connector')\n*   **Intel® Xeon® E Processor (formerly “Coffee Lake”)**\n*   **Intel® CM246 Chipset**\n*   **DDR4 2133/2400 MHz SODIMM x2**\n*   **PCI Express Switch (PCI Express 3.0)**\n*   **GPIB Controller**\n*   **GbE Controller I219**\n*   **GbE Controller I210**\n*   **LCP-COM Port**\n*   **2.5' SATA Storage**\n*   **SMBus Controller / Programmable MUX** (Grouping box)\n*   **Rear Connectors to PXI Express Chassis** (Grouping box)\n\n**Connections**\n*   **DisplayPort Connector x2** connects via **DP/HDMI Dual Mode** to the **Intel® Xeon® E Processor**.\n*   **GPIB Connector** connects to the **GPIB Controller**, which connects via **PCle x1** to the **Intel® CM246 Chipset**.\n*   **GbE Connector** connects to the **GbE Controller I219**, which connects via **PCle x1** to the **Intel® CM246 Chipset**.\n*   **GbE Connector** connects to the **GbE Controller I210**, which connects via **PCle x1** to the **Intel® CM246 Chipset**.\n*   **USB3.0 Connector x2** connects via **USB 3.0** to the **Intel® CM246 Chipset**.\n*   **USB2.0 Connector x4** connects via **USB 2.0** to the **Intel® CM246 Chipset**.\n*   **COM Port Connector (RS-232/422/485)** connects to the **LCP-COM Port**, which connects via **LPC** to the **Intel® CM246 Chipset**.\n*   **Intel® Xeon® E Processor** connects to the **Intel® CM246 Chipset** via **Intel FDI** and **DMI 3.0**.\n*   **Intel® Xeon® E Processor** connects to **DDR4 2133/2400 MHz SODIMM x2** via **Memory Bus**.\n*   **Intel® Xeon® E Processor** connects to the **PCI Express Switch (PCI Express 3.0)** via **PCle 3.0 x16**.\n*   **Intel® CM246 Chipset** connects to **2.5' SATA Storage** via **SATA**.\n*   **Intel® CM246 Chipset** connects to the **SMBus Controller / Programmable MUX** block via **PCle x1**.\n*   **SMB Connector** connects to the **SMBus Controller / Programmable MUX** block via **Trigger Signal**.\n*   **PCI Express Switch (PCI Express 3.0)** connects to the **Rear Connectors to PXI Express Chassis** via **PCle 3.0 2 Link Mode (x16 x8) OR PCle 3.0 4 Link Mode (x4 x4 x4 x4)**.\n*   **SMBus Controller / Programmable MUX** block connects to the **Rear Connectors to PXI Express Chassis** via **SMBus** and **Trigger Bus**.](.pxie-3988-um-50m-00028-1000-10/a82c2d8edd7130ab7440182a8d6c98739fd2f413b50b576366e89bfe05b09ac3.jpg)

Figure 1-1: Functional Block Diagram

# Processor

 Intel® Xeon® E processor (formerly Coffee Lake)
 DMI (Direct Media Interface) 3.0 with 8 GT/s bandwidth in each direction

# Chipset

Intel® CM246 chipset

# Memory

 Two standard 260-pin DDR4 SO-DIMM sockets
 Supports 2133/2400 MHz RAM up to 64 GB total
 Supports non-ECC, unbuffered memory

![The image displays a white document icon featuring a folded top-left corner and horizontal grey lines. Superimposed over the document is a large, bold red checkmark.](.pxie-3988-um-50m-00028-1000-10/58f61806c3207fdf3128ce12739b79f238893d5becc116acb952d7bd22f8d194.jpg)
NOTE:

The externally accessible SO-DIMM socket can accept replacement DDR4 DRAM DIMM modules.

PXIe-3988 specifications and stability guarantees are only supported when ADLINK-provided DDR4 DRAM SO-DIMM modules are used.

# Video

 DisplayPort resolution up to 3840 x 2160 @ 60 Hz
 DVI (with passive DisplayPort-to-DVI adapter) resolution up to 1920 x 1200 @ 60 Hz

![An icon depicting a piece of lined paper with a red checkmark drawn over it.](.pxie-3988-um-50m-00028-1000-10/45bfd00e87e645e149ef1df7d35410ff7a00e9a8cf9f82aec36ac7073756f5f3.jpg)
NOTE:

DisplayPort adapters for other standards are available, with maximum available resolution dependent on the adapter

# Storage

Built-in 2.5” 500 GB or 240 GB SATA solid state hard drive.

# Ethernet Connectivity

Dual Gigabit Ethernet controllers through two RJ-45 connectors with speed/link/active LED on the faceplate, with both supporting Wake on LAN.

# USB

Four USB 2.0 and two USB 3.0 ports on the faceplate.

# GPIB

Onboard IEEE488 GPIB controller through Micro-D 25-pin connector on the faceplate.

# Trigger I/O

One SMB connector on the faceplate to route an external trigger signal to/from PXI trigger bus.

# Dimensions (3U PXI module)

3U/4-slot PXI standard

# Weight

1.0 kg (exclusive of packaging)

Environmental

<table><tr><td>Condition</td><td>Range</td></tr><tr><td>Operating temperature with SSD</td><td>0 to 55°C</td></tr><tr><td>Operating temperature with HDD</td><td>0 to 50°C</td></tr><tr><td>Storage temperature</td><td>-20 to 70°C</td></tr><tr><td>Relative humidity, non-condensing</td><td>5 to 95%</td></tr></table>

# Shock and Vibration

Functional shock 30 G, half-sine, 11 ms pulse duration

Random vibration:

 Operating: 5 to 500 Hz, 0.21 Grms, 3 axes
 Non-operating: 5 to 500 Hz, 2.46 Grms, 3 axes

![The image displays a white document icon with a folded top-left corner and faint horizontal lines. A large, bold red checkmark is superimposed over the document.](.pxie-3988-um-50m-00028-1000-10/acdc86e8326cb6a2479c9ffd9f0c117bc9f313e5f0ed965c571df3f4a2ca4b9d.jpg)
NOTE:

Environmental, shock, and vibration values are only valid with use of an ADLINK-provided SSD/HDD

# Certifications

Electromagnetic compatibility:

 EN 55011:2016+A1: 2017 (Group 1, Class A)
 CISPR 11:2009+A1: 2010 (Group 1, Class A)
 EN 61000-3-2:2014: Class A
 EN 61000-3-3:2013: Class A
 EN 61326-1: 2013, Table 2 (Industrial)
 FCC 47 CFR Part 15 Subpart B (Class B)
 ICES-003 Issue 7-2020
 AS/NZS CISPR 11: Group 1, Class A emissions

The PXIe-3988 meets the essential requirements of applicable European Directives.

Power Requirements

<table><tr><td>Typical Consumption</td><td>DC +3.3V</td><td>DC +12V</td></tr><tr><td>Typical operation(Measured while W10 is idle)</td><td>3A</td><td>6A</td></tr><tr><td>Heavy operation(Measured while W10 is under heavy CPU and storage utilization)</td><td>3A</td><td>11A</td></tr></table>

# 1.3 I/O and Indicators

# 1.3.1 Front Panel

![ADLINK\nPXIe-3988\nPXIe Embedded\nController\nHD USR\nPW\nTRIG\nA\nH\nB\nC\nG\nSSK\nD\nF\nCOM\nE\nGPIB](.pxie-3988-um-50m-00028-1000-10/bb386baf1197418b90ab3d2b863f320754128236cece4170d8d3fa1b6d3707b8.jpg)

Figure 1-2: Front Panel

<table><tr><td>A</td><td>Reset Button</td><td>F</td><td>GPIB Connector (Micro D-Sub 25P)</td></tr><tr><td>B</td><td>2X DisplayPort</td><td>G</td><td>2X Gigabit Ethernet</td></tr><tr><td>C</td><td>2X USB 3.0</td><td>H</td><td>PXI Trigger</td></tr><tr><td>D</td><td>4X Type-A USB 2.0</td><td rowspan="2">I</td><td rowspan="2">LED indicators</td></tr><tr><td>E</td><td>COM port (D-sub9 serial)</td></tr></table>

Table 1-1: Front Panel Legend

# PXI Trigger Connector

![Ground\nTrigger](.pxie-3988-um-50m-00028-1000-10/dc8c079992eb96d4e13a4782a1f589d25d56327e21d7e4152801ec292e845000.jpg)

Figure 1-3: PXI Trigger SMB Jack

The PXI trigger connector is an SMB jack, used to route external trigger signals to or from the PXI backplane. Trigger signals are TTL-compatible and edge sensitive. The PXIe-3988 provides four trigger routing modes from/to the PXI trigger connector to synchronize PXI modules, including

 From a selected trigger bus line to PXI trigger connector
 From the PXI trigger connector to a selected trigger bus line
 From software trigger to a selected trigger bus line
 From software trigger to PXI trigger connector

All trigger modes are programmable by the provided driver.

# DisplayPort Connectors

Provide monitor connection with installation of requisite adapters required if connecting to VGA/DVI/HDMI monitors. Dual display function is also supported.

![19\n1\n20\n2](.pxie-3988-um-50m-00028-1000-10/c315d4ca9523622c18ed0e11e0261d6d0647be2b17182cce925bb7bea0be71f5.jpg)

Figure 1-4: DisplayPort Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CN_DDPx0+</td><td>11</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>12</td><td>CN_DDPx3-</td></tr><tr><td>3</td><td>CN_DDPx0-</td><td>13</td><td>CN_DDPx_AUX_SEL</td></tr><tr><td>4</td><td>CN_DDPx1+</td><td>14</td><td>CN_DDPx_CONFIG2</td></tr><tr><td>5</td><td>GND</td><td>15</td><td>CN_DDPx_AUX+</td></tr><tr><td>6</td><td>CN_DDPx1-</td><td>16</td><td>GND</td></tr><tr><td>7</td><td>CN_DDPx2+</td><td>17</td><td>CN_DDPx_AUX-</td></tr><tr><td>8</td><td>GND</td><td>18</td><td>CN_DDPx_HPD</td></tr><tr><td>9</td><td>CN_DDPx2-</td><td>19</td><td>GND</td></tr><tr><td>10</td><td>CN_DDPx3+</td><td>20</td><td>+V3.3_DDPx_PWR</td></tr></table>

Table 1-2: DisplayPort Pin Assignment

# 1.3.2 GPIB Connector

The GPIB connector is a micro D-sub 25P connector, controlling external bench-top instruments. Connection to other instruments requires the optional ACL-IEEE488-MD1-A cable. The onboard GPIB controller provides:

 Full compatibility with IEEE 488 standard
 Up to 1.5 MB/s data transfer rates
 Onboard 2 KB FIFO for read/write operations
 Driver APIs are compatible with NI-488.2 driver software
 Connection with up to 14 instruments

![1\n13\n14\n25](.pxie-3988-um-50m-00028-1000-10/eea5d4fc6d6281b3d3d1df01b02ba039f4cfee1633f495632313a552b3bf94ee.jpg)

Figure 1-5: GPIB Connector

<table><tr><td>Pin</td><td>Signal</td><td>Description</td><td>Pin</td><td>Signal</td><td>Description</td></tr><tr><td>1</td><td>DIO1#</td><td>GPIB Data 1</td><td>14</td><td>DIO5#</td><td>GPIB Data 5</td></tr><tr><td>2</td><td>DIO2#</td><td>GPIB Data 2</td><td>15</td><td>DIO6#</td><td>GPIB Data 6</td></tr><tr><td>3</td><td>DIO3#</td><td>GPIB Data 3</td><td>16</td><td>DIO7#</td><td>GPIB Data 7</td></tr><tr><td>4</td><td>DIO4#</td><td>GPIB Data 4</td><td>17</td><td>DIO8#</td><td>GPIB Data 8</td></tr><tr><td>5</td><td>EOI</td><td>End Or Identify</td><td>18</td><td>REN</td><td>Remote Enable</td></tr><tr><td>6</td><td>DAV</td><td>Data Valid</td><td>19</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>7</td><td>NRFD</td><td>Not Ready For Data</td><td>20</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>8</td><td>NDAC</td><td>No Data Accepted</td><td>21</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>9</td><td>IFC</td><td>Interface Clear</td><td>22</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>10</td><td>SRQ</td><td>Service Request</td><td>23</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>11</td><td>ATN</td><td>Attention</td><td>24</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>12</td><td>Chassis Ground</td><td>Chassis Ground</td><td>25</td><td>Ground</td><td>Signal Ground</td></tr><tr><td>13</td><td>Ground</td><td>Signal Ground</td><td></td><td></td><td></td></tr></table>

Table 1-3: GPIB Pin Description

# 1.3.3 Reset Button

The reset button, activated by insertion of any pin-like implement, executes a hard reset for the PXIe-3988.

# 1.3.4 LED Indicators

Three LED indicators on the faceplate indicate operational status of the PXIe-3988, as follows.

![HD USR\n● ○\nPW ●](.pxie-3988-um-50m-00028-1000-10/438e1326f7f330331700753dc74456467f26d2c3a73f38b1c0d7a833d4381a3b.jpg)

Figure 1-6: LED Indicators

<table><tr><td>LED</td><td>Color</td><td>Description</td></tr><tr><td>PW</td><td>Green</td><td>Indicates system power, remaining lit when the system boots normally and main power supply is functioning.</td></tr><tr><td>HD</td><td>Yellow</td><td>Indicates operating state of the HDD or SSD, flashing during access to or activity on the SATA HDD.</td></tr><tr><td>USR</td><td>Blue</td><td>User-programmable LED indicator.</td></tr></table>

Table 1-4: LED Indicator Legend

# 1.3.5 USB 2.0 Ports

The PXIe-3988 provides four USB 2.0 ports via USB Type-A connectors on the faceplate, all compatible with hi-speed, full-speed and low-speed USB devices. Supported boot devices include USB flash drive, USB floppy, USB CD-ROM, and others, with boot priority and device settings configured in BIOS. See section B.8: "Boot" on page 60 for more information.

![Pure electrical connector pinout diagram without any text or symbols](.pxie-3988-um-50m-00028-1000-10/b540adf4d265d631d92e634b928666f0dbed1914e3ee488a4442469e8af46878.jpg)

![1\n2\n3\n4](.pxie-3988-um-50m-00028-1000-10/4028c521d2b08a9b39fb0c03cdbfc99da2ea1f46986a96c2fcec2e128d74f3ca.jpg)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1/5</td><td>Power 5V</td></tr><tr><td>2/6</td><td>USB Data-</td></tr><tr><td>3/7</td><td>USB Data +</td></tr><tr><td>4/8</td><td>Ground</td></tr></table>

Table 1-5: USB 2.0 Port Pin Assignment

# 1.3.6 Gigabit Ethernet Ports

Dual Gigabit Ethernet connection is provided on the PXIe-3988 front panel.

<table><tr><td>Pin</td><td>1000Base-T Signal</td><td>100/10Base-T Signal</td></tr><tr><td>1</td><td>MDI0+</td><td>TX+</td></tr><tr><td>2</td><td>MDI0-</td><td>TX-</td></tr><tr><td>3</td><td>MDI1+</td><td>RX+</td></tr><tr><td>4</td><td>MDI2+</td><td>Reserved</td></tr><tr><td>5</td><td>MDI2-</td><td>Reserved</td></tr><tr><td>6</td><td>MDI1-</td><td>RX-</td></tr><tr><td>7</td><td>MDI3+</td><td>Reserved</td></tr><tr><td>8</td><td>MDI3-</td><td>Reserved</td></tr></table>

Table 1-6: Ethernet Port Pin Assignments

Each Ethernet port includes two LED indicators, one Active/Link indicator and one Speed indicator, functioning as follows.

<table><tr><td></td><td>LED</td><td>Status</td><td>Description</td></tr><tr><td rowspan="6">&lt;img src="images/25dc2b4b98141d28d9563ab8d0e3f11b7b27e27eed18df0cea912a2d4d9777d7.jpg"/&gt;</td><td rowspan="3">Active/Link (Yellow)</td><td>Off</td><td>Ethernet port is disconnected</td></tr><tr><td>On</td><td>Ethernet port is connected with no data transmission</td></tr><tr><td>Flashing</td><td>Ethernet port is connected with data transmitted/received</td></tr><tr><td rowspan="3">Speed (Green/Orange)</td><td>Off</td><td>10 Mbps</td></tr><tr><td>Green</td><td>100 Mbps</td></tr><tr><td>Orange</td><td>1000 Mbps</td></tr></table>

Table 1-7: Ethernet Status LED Descriptions

# 1.3.7 USB 3.0 Ports

The PXIe-3988 provides two Type-A USB 3.0 ports on the front panel, supporting SuperSpeed, Hi-Speed, full-speed, and lowspeed downstream transmission. Multiple boot devices, including USB flash, USB external HD, and USB CD-ROM drives are supported, with boot priority configured in BIOS.

![A white piece of paper with horizontal lines has a large red checkmark overlaid on it.](.pxie-3988-um-50m-00028-1000-10/bc7ec9e0c93c3f927763e13a5765fcda47a033af76b241d8368938aad47087f7.jpg)
NOTE:

USB 3.0 may not be supported by the OS installation programs/environment. Use USB 2.0 ports for OS installation if necessary.

# 1.3.8 COM Port

A COM port on the front panel with D-sub 9P connectors supports RS-232/RS-422/RS-485 by BIOS selection.

![1\n5\n6\n9](.pxie-3988-um-50m-00028-1000-10/d9c628f286a59fbd1b73d8159fba5a478473d4ebfd9077aac53fc0ee2895a128.jpg)

Figure 1-7: COM Port

<table><tr><td rowspan="2">Pin</td><td colspan="3">Signal Name</td></tr><tr><td>RS-232</td><td>RS-422</td><td>RS-485</td></tr><tr><td>1</td><td>DCD#</td><td>TXD422-</td><td>485DATA-</td></tr><tr><td>2</td><td>RXD</td><td>TXD422+</td><td>485DATA+</td></tr><tr><td>3</td><td>TXD</td><td>RXD422+</td><td>N/S</td></tr><tr><td>4</td><td>DTR#</td><td>RXD422-</td><td>N/S</td></tr><tr><td>5</td><td>GND</td><td>N/S</td><td>N/S</td></tr><tr><td>6</td><td>DSR#</td><td>N/S</td><td>N/S</td></tr><tr><td>7</td><td>RTS#</td><td>N/S</td><td>N/S</td></tr><tr><td>8</td><td>CTS#</td><td>N/S</td><td>N/S</td></tr><tr><td>9</td><td>RI#</td><td>N/S</td><td>N/S</td></tr></table>

Table 1-8: D-sub COM Port Signal Functions

# 1.3.9 Onboard Connections and Settings

![ADLINK\nWD Blue®\n5000B\nA\nB\nC\nA\nB\nC\n1734NO\n0.47uH\nR105\nR10D\nR27\nR39\nR528\nSWT\nCGB\nR521\nTC8\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n330\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n376\n331\n371](.pxie-3988-um-50m-00028-1000-10/8c4d44e8c11efe267b75d5928da54ab35d257b8128138fb08f3e44ceed6340c1.jpg)

Figure 1-8: Onboard Configuration

<table><tr><td>A</td><td>Clear CMOS switch</td></tr><tr><td>B</td><td>SATA connector</td></tr><tr><td>C</td><td>System battery</td></tr></table>

Table 1-9: Onboard Configuration Legend

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# 2 Getting Started

This chapter describes procedures for installing the PXIe-3988 and making preparations for its operation, including hardware and software setup. Note that the PXIe controller is shipped with RAM and an SSD preinstalled. Contact ADLINK or an authorized dealer if there are any problems during the installation.

![This is an icon depicting a white document with a folded top-right corner and faint grey horizontal lines, featuring a large red checkmark overlaid on top.](.pxie-3988-um-50m-00028-1000-10/265f61bb23553ad5a840b947596384821135d6a9698a34829a0f394453a60fb0.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Package Contents

Before beginning, check the package contents for any damage and ensure that the following items are included:

 PXIe-3988 Controller (equipped with RAM and HDD or SSD)
 PXIe-3988-3987-3977-3937 Quick Start Guide

If any of these items are missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.

![This image shows a standard warning sign. It features a red triangle with a white border containing a large white exclamation point. Below the triangle is a white rectangle with the text 'WARNING:' printed in black capital letters.](.pxie-3988-um-50m-00028-1000-10/a0d7cbf2534f17ef00b9818d4d20d8e4193ddfcf413a4c89cc2bb87c9e88b4fd.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Contact an ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Operating System Installation

For more detailed information about the operating system, refer to the documentation provided by the operating system manufacturer. Preferred/supported operating systems for the PXIe controller are:

 Windows 10 64-bit
 For other OS support, contact ADLINK

Most operating systems require initial installation from a hard drive, floppy drive, or CD-ROM drive. The PXIe controller supports USB CD-ROM drive, USB flash disk, USB external hard drive, or a USB floppy drive as the first boot device. See section B.8: "Boot" on page 60 for information about setting the boot devices. These devices should be configured, installed, and tested with the supplied drivers before attempting to load the new operating system.

![The image displays a graphic icon of a white document or piece of paper with its top-left corner folded down. Faint horizontal grey lines run across the page, resembling writing lines. A large, bold red checkmark is superimposed over the document, angled from the bottom left to the top right.](.pxie-3988-um-50m-00028-1000-10/d8556c698c9db274173f725b9023542f8ccc8344b404b2aedfabea643f56cb24.jpg)
NOTE:

Read the release notes and installation documentation provided by the operating system vendor. Be sure to read all the README files or documents provided on the distribution disks, as these typically note documentation discrepancies or compatibility problems.

1. Select the appropriate boot device order from the BIOS Boot Setup Menu based on the OS installation media used. For example, if the OS is distributed on a bootable installation CD, select USB CD-ROM as the first boot device and reboot the system with the installation CD in the USB CD-ROM drive.
2. Proceed with the OS installation as directed and be sure to select appropriate device types if prompted. Refer to the appropriate hardware manuals for specific device types and compatibility modes of ADLINK PXI products.
3. When installation is complete, reboot the system and set the boot device order in the BIOS Boot Setup Menu accordingly.

# 2.2.1 Installation Environment

When preparing to install any equipment described in this manual, first refer to Important Safety Instructions.

Only install equipment in well lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools include:

 Phillips (cross-head) screwdriver
 Flat-head screwdriver
 Anti-static wrist strap
 Anti-static mat

ADLINK PXIe system controllers are electrostatically sensitive and can be easily damaged by static electricity. The equipment must be handled on a grounded anti-static mat, and operators must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling may cause damage to the contents. Ensure that all contents are undamaged before installing.

![This image displays a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.pxie-3988-um-50m-00028-1000-10/f8ea76f7352eb7c576669a72f17942678f53ee9a11371aef743141d9ce98b26e.jpg)

All equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the antistatic bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing or installing.

# 2.2.2 Installing the PXIe-3988

1. Remove all screw caps (x4).

![The image displays a four-panel diagram illustrating a hardware modification on an electronic device. The top row shows a metal enclosure housing a green circuit board. Red circles highlight black cylindrical pins at the top-right and bottom-right. A red arrow points to the right panel, where these pins are replaced with silver threaded screws. The text 'CE' is visible on the circuit board.\n\nThe bottom row shows a similar enclosure. Red circles highlight black pins at the top-left and bottom-left. A red arrow points to the right panel where they are replaced with silver threaded screws. Visible text includes '106' on a white label and 'K1200' stamped on a metal bracket.](.pxie-3988-um-50m-00028-1000-10/e550e005a268207eecacf99fb6444d90b00810c78a5e5846165cc651618773ca.jpg)

2. Release the red locking lever.

![Close-up of a black mechanical component with red and white parts, showing a red arrow pointing to a specific area (no text or symbols visible)](.pxie-3988-um-50m-00028-1000-10/068aff010978e288117e27f30c71e50872a4343111a22737a8867fa627b0e279.jpg)

3. Depress the latch.

![Close-up of a mechanical device with a red arrow pointing to a red component, no visible text or symbols.](.pxie-3988-um-50m-00028-1000-10/4fcdd58a35e08a5dc969b0741046695f409c9500b20bb3f714b22f636bcd8dd9.jpg)

4. Locate the system controller slot of the chassis (Slot 1).

![ADLINK\n1\n2 H\n3 H\n4 H](.pxie-3988-um-50m-00028-1000-10/7a13875cb74c8e5a01303d7a2087810db50c94d7a3521d88b07a7f2585950d05.jpg)

5. Align the controller’s top and bottom edges with the card guides, and carefully slide the PXIe-3988 into the chassis, as shown.

![ADLINK\n2 H 3 H 4 H\nADLINK\n05000-PC1\n05000-PC1\n05000-PC1\n05000-PC1\n05000-PC1\n05000-PC1](.pxie-3988-um-50m-00028-1000-10/f47769dd5f3473505300c90e81c0c040ada5d8d299a6ca3e9407deab45ca716b.jpg)

![Close-up of a computer motherboard with a red circle highlighting a component, no visible text or symbols](.pxie-3988-um-50m-00028-1000-10/d5c604f86b3167e04d55d460a2efca7299a21a812b6e259986babf7060208657.jpg)

6. Elevate the latch until the PXIe-3988 is fully seated in the chassis backplane. The alignment pin on the rear of the latch can be threaded into the best fit alignment port in the chassis rail.
7. Fasten the four mounting screws on the faceplate and connect all peripheral devices.

# 2.2.3 Replacing the Hard Drive or Solid State Drive

The PXIe controller provides a SATA 3.0 port with a pre-installed 2.5" SATA hard drive or solid state drive. Replacing the HDD or SSD is accomplished as follows.

1. Locate the five screws attaching the hard drive housing to the PXIe controller, as shown.

![WID\nWD Blue®\n500GB\nWID: 200000 PCX\nSIN\nADLINK\nTECHNOLOGY INC.\nWID: 200000 PCX - 422mA/13\nWID: 200000 PCX - 422mA/13\nWID: 200000 PCX - 422mA/13\nWID: 200000 PCX - 422mA/13\nWID: 200000 PCX - 422mA/13\nWID: 200000 PCx - 422mA/13\nWID: 200000 PCx - 422mA/13\nWID: 200000 PCx - 422mA/13\nWID: 200000 PCx - 422mA/13\nWID: 200000 PCx - 422mA/13\nWIC: 2.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB\nWIC: 2.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB\nWIC: 2.5 GB / 1.5 GB / 1.5 GB / 1,5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB / 1.5 GB\nWIC: 2.5 GB / 1.5 GB / 1.5 GB / 1,5 GB / 1.5 GB / 1.5 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB / 1.7 GB\nWIC: 2.5 GB / 1.5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB\nWIC: 2.5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB\nWIC: 2.5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,\nWIC: 2.5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB\nWIC: 2.5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,5 GB\nWIC: 2.5 GB / 1,5 GB / 1,5 GB / 1,5 GB / 1,766 MB\nWIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: W/C\nWIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC:\nWIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC:\nWIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WI\nWIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WI\nWIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WIC: WI\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID\nWID](.pxie-3988-um-50m-00028-1000-10/bb75af78d9cd6e480b604a81b53a5f1251025e6d5721a5d5a6930ab1b938b2c5.jpg)

2. Remove the screws.
3. Gently lift and remove the housing with the installed HDD or SSD.

4. Locate the four screws (two on each side, as shown) fixing the hard drive, and remove them.

![0025-T5S-AE\nSF D6Y17EJ\nE46 E29 E30 E20 E29 E78 R72 E74\nE49 E48 E47 E46 E45 E44 E43 E42 E41 E39 E38 E37 E36 E35 E34 E33 E32 E31 E30 E29\nE47 E46 E45 E44 E43 E42 E41 E39 E38 E37 E36 E35 E34 E33 E32 E31\nE48 E47 E46 E45 E44 E43 E42 E41 E39 E38 E37 E36 E35 E34 E33 E32 E31\nE49 E48 E47 E46 E45 E44 E43 E42 E41 E39 E38 E37 E36 E35 E34 E33 E32 E31\nE50 E51 E52 E53 E54 E55 E56\nE57 E58 E59 E60 E61 E62 E63 E64\nE58 E59 E60 E61 E62 E63\nE64\nE65\nE66\nE67\nE68\nE69\nE70\nE71\nE72\nE73\nE74\nE75\nE76\nE77\nE78\nE79\nE80\nE81\nE82\nE83\nE84\nE85\nE86\nE87\nE88\nE89\nE90\nE91\nE92\nE93\nE94\nE95\nE96\nE97\nE98\nE99\nE100\nE101\nE102\nE103\nE104\nE105\nE106\nE107\nE108\nE109\nE110\nE111\nE112\nE113\nE114\nE115\nE116\nE117\nE118\nE119\nE120\nE121\nE122\nE123\nE124\nE125\nE126\nE127\nE128\nE129\nE130\nE131\nE132\nE133\nE134\nE135\nE136\nE137\nE138\nE139\nE140\nE141\nE142\nE143\nE144\nE145\nE146\nE147\nE148\nE149\nE150\nE151\nE152\nE153\nE154\nE155\nE156\nE157\nE158\nE159\nE160\nE161\nE162\nE163\nE164\nE165\nE166\nE167\nE168\nE169\nE170\nE171\nE172\nE173\nE174\nE175\nE176\nE177\nE178\nE179\nE180\nE181\nE182](.pxie-3988-um-50m-00028-1000-10/9b300b999728ea2aa0553c7548cb55bf5f36c5cabe74725a1ca4aa0512b106fb.jpg)

5. To install an HDD, SSD, or other compatible SATA hard drive, reverse the steps and reinstall the PXIe controller into the PXI system.

# 2.2.4 Replacing the Battery Backup

The PXIe-3988 is provided with a 3.0 V “coin cell” lithium battery, replacement of which is as follows.

1. Turn off the PXI chassis.
2. Remove the PXIe controller from the chassis. Observe all anti-static precautions.
3. To remove the battery, gently insert a small (approx. 5 mm) flathead screwdriver under the battery at the negative retaining clip. Gently pry up and the battery should easily pop out.

4. Place a fresh identical battery (CR2032 or equivalent) in the socket, ensuring that the positive pole (+) is facing upwards. The battery is most easily seated by first being inserted under the positive retaining clip, and then pushed downward at the negative retaining clip. The battery should easily snap into position.

5. Reinstall the PXIe controller into the PXI chassis and restore power.

# 2.2.5 Clearing CMOS

In the event of a system malfunction causing the PXIe controller to halt or fail to boot, clear the CMOS and restore the controller BIOS to its default settings. To clear the CMOS:

1. Shut down the controller operating system and turn off the PXI Chassis.
2. Remove the PXIe controller from the chassis. Observe all anti-static precautions.
3. Locate the CMOS clear switch (SW1) on the board (see section 1.3.9: "Onboard Connections and Settings" on page 15). Move the switch from the Normal position...

![The image displays a cropped section of a digital interface, likely a control or slider. It features a dark grey rectangular background. Inside this, a lighter grey horizontal rectangle is visible. Within the lighter grey area, there is a white square on the right side and a small white dot on the left side, positioned near the bottom edge. There is no text visible in the image.](.pxie-3988-um-50m-00028-1000-10/e599467c98c5d49ae4a00171bc2f3f0f5dca312c74945930ef9201619e157001.jpg)

...to the Clear position.

![The image displays a close-up of a dark grey rectangular interface element, likely a slider or progress bar. On the left side, there is a white square block sitting on a horizontal track. Extending to the right from the white square is a long, light grey rectangular area. Below the track on the far left, there is a small white dot. There is no text visible in the image.](.pxie-3988-um-50m-00028-1000-10/8f28c630e875df3d93c41e8084a7df2493b6157deb183f76c8a0b9d9151fa8ca.jpg)

Wait five seconds, then return the switch to the Normal position.

![The image displays a close-up of a digital interface element, likely a progress bar or slider, set against a dark gray background. A long horizontal rectangle dominates the center. The left approximately 80% of the rectangle is a medium gray, while the right approximately 20% is white. Below the left edge of the rectangle, a small white dot is visible. Faint horizontal lines appear in the upper-left corner.](.pxie-3988-um-50m-00028-1000-10/1f4acfc87f6eaedbaf887ae0402f43734f162ba78699964849b7c4e9fea5862d.jpg)

4. Remount the controller into the PXI chassis.
5. Press &lt;Delete&gt; or &lt;ESC&gt; to enter BIOS Setup when the splash logo appears.
6. Press &lt;F9&gt; to load optimized defaults in BIOS Setup.
7. Modify the system date and time.
8. Press &lt;F10&gt; to save configuration and exit.

# 3 Driver Installation

Windows 10 already carries most of the device drivers required by the PXIe-3988. Others can be downloaded from the ADLINK website after clicking “Driver” on any of the product pages for this series (the files are exactly the same for each product):

www.adlinktech.com/Products/PXI\_PXIe/PXIControllers/PXIe-3988

Use of Windows 10 requires the following drivers:

 Chipset Driver
 Graphics Driver
 Ethernet/LAN Driver
 PXI Trigger I/O Driver
 Intel ME Driver
 GPIB Driver
 Intel RST Driver

The following optional utility programs are also provided:

? MAPS Core Windows Software Suite for ADLINK Measurement, Automation, and PXI products
 PXI Platform Services

After downloading and extracting a given file, run the executable and follow its instructions to complete installation.

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# Appendix A PXI Trigger I/O Functions

This appendix describes use of the PXI trigger I/O function library for the PXIe-3988 controller, to program routing of trigger signals between the trigger I/O SMB connector on the faceplate and the PXI trigger bus on the backplane. API files are located in the installation directory of the PXI Trigger I/O driver.

# A.1 Data Type

The PXIe-3988 library uses these data types in pxitrigio.h in the directory X:\ADLINK\MAPS Core\PXI\PXIe Trigger IO\Include. It is recommended that you use these data types in your application programs. The table shows the data type names, ranges, and corresponding data types in C/C++, Visual Basic, and Delphi for reference.

<table><tr><td rowspan="2">Type</td><td rowspan="2">Description</td><td rowspan="2">Range</td><td colspan="3">Type</td></tr><tr><td>C/C++ (for 32-bit compiler)</td><td>Visual Basic</td><td>Pascal (Delphi)</td></tr><tr><td>U8</td><td>8-bit ASCII character</td><td>0 to 255</td><td>unsigned char</td><td>Byte</td><td>Byte</td></tr><tr><td>I16</td><td>16-bit signed integer</td><td>-32768 to 32767</td><td>short</td><td>Integer</td><td>SmallInt</td></tr><tr><td>U16</td><td>16-bit unsigned integer</td><td>0 to 65535</td><td>unsigned short</td><td>Not supported by BASIC, use the signed integer (I16) instead</td><td>Word</td></tr><tr><td>I32</td><td>32-bit signed integer</td><td>-2147483648 to 2147483647</td><td>long</td><td>Long</td><td>LongInt</td></tr><tr><td>U32</td><td>32-bit unsigned integer</td><td>0 to 4294967295</td><td>unsigned long</td><td>Not supported by BASIC, use the signed long integer (I32) instead</td><td>Cardinal</td></tr></table>

Table A-1: Data Type

<table><tr><td rowspan="2">Type</td><td rowspan="2">Description</td><td rowspan="2">Range</td><td colspan="3">Type</td></tr><tr><td>C/C++ (for 32-bit compiler)</td><td>Visual Basic</td><td>Pascal (Delphi)</td></tr><tr><td>F32</td><td>32-bit single-precision floating-point</td><td>-3.402823E38 to 3.402823E38</td><td>float</td><td>Single</td><td>Single</td></tr><tr><td>F64</td><td>64-bit double-precision floating-point</td><td>1.7976831348 62315E308 to 1.7976831348 62315E309</td><td>double</td><td>Double</td><td>Double</td></tr></table>

Table A-1: Data Type

# A.2 Function Library

This section provides detailed definitions of the functions available in the PXIe-3988 function library. Each function includes a description, list of supported cards, syntax, parameter list and Return Code information.

# A.2.1 TRIG\_Init

# Description

Initializes trigger I/O function of PXIe-3988 controller. TRIG\_Init must be called before the invocation of any other trigger I/O function.

# Syntax

C/C++

I16 TRIG\_Init()

Visual Basic

TRIG\_Init As Integer

# Parameter

None

# Return Code

ERR\_NoError

ERR\_BoardBusy

ERR\_OpenDriverFail

ERR\_GetGPIOAddress

# A.2.2 TRIG\_Close

# Description

Closes trigger I/O function of PXIe-3988 controller, releasing resources allocated for the trigger I/O function. Users must invoke TRIG\_Close before exiting the application.

# Syntax

C/C++

I16 TRIG\_Close()

Visual Basic

TRIG\_Close() As Integer

# Parameter

None

# Return Code

ERR\_NoError

ERR\_BoardNoInit

# A.2.3 TRIG\_SetSoftTrg

# Description

Generates a TTL trigger signal to the trigger I/O SMB connector on the faceplate or the PXI trigger bus on the backplane by software command.

# Syntax

C/C++

I16 TRIG\_SetSoftTrg(U8 Status)

Visual Basic

TRIG\_SetSoftTrg (ByVal status As Byte) As Integer

# Parameters

Status

Logic level of trigger signal.

Available value description:

0: Logic low

1: Logic high

# Return Code

ERR\_NoError

ERR\_BoardNoInit

# A.2.4 TRIG\_Trigger\_Route

# Description

Routes the trigger signal between the trigger I/O SMB connector on the faceplate and the PXI trigger bus on the backplane. This function also allows routing of the softwaregenerated trigger signal to SMB connector or trigger bus.

# Syntax

```txt
C/C++
```

```txt
I16 TRIG_Trigger_Route (U32 source, U32 dest, U32 halfway)
```

# Visual Basic

```txt
TRIG_Trigger_Route (ByVal source As Long, ByVal dest As Long, ByVal halfway As Long) As Integer
```

# Parameters

source

Source of trigger routing can be one of the following values.

<table><tr><td>Available value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>SMB connector on the faceplate</td></tr><tr><td>PXI_TRIG_VAL_SOFT</td><td>Software-generated trigger signal</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>PXI trigger bus #0</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>PXI trigger bus #1</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>PXI trigger bus #2</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>PXI trigger bus #3</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>PXI trigger bus #4</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>PXI trigger bus #5</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>PXI trigger bus #6</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>PXI trigger bus #7</td></tr></table>

# dest

Destination of trigger routing can be one of the following.

<table><tr><td>Available value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>SMB connector on the faceplate</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>PXI trigger bus #0</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>PXI trigger bus #1</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>PXI trigger bus #2</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>PXI trigger bus #3</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>PXI trigger bus #4</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>PXI trigger bus #5</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>PXI trigger bus #6</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>PXI trigger bus #7</td></tr></table>

# halfway

Halfway point of trigger routing. This parameter is used only to route the software-generated trigger signal to the SMB connector on the faceplate. In this case, the halfway should be set as one of the trigger bus lines, otherwise as PXI\_TRIG\_VAL\_NONE.

<table><tr><td>Available value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>No halfway point</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>PXI trigger bus #0</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>PXI trigger bus #1</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>PXI trigger bus #2</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>PXI trigger bus #3</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>PXI trigger bus #4</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>PXI trigger bus #5</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>PXI trigger bus #6</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>PXI trigger bus #7</td></tr></table>

# Return Code

ERR\_NoError ERR\_BoardNoInit ERR\_Set\_Path

# A.2.5 TRIG\_Trigger\_Clear Description

Clears the trigger routing setting.

# Syntax

C/C++

I16 TRIG\_Trigger\_Clear()

Visual Basic

TRIG\_Trigger\_Clear() As Integer

# Parameters

None

# Return Code

ERR\_NoError

ERR\_BoardNoInit

ERR\_Trigger\_Clr

# A.2.6 TRIG\_GetSoftTrg

# Description

Acquires the current software trigger state, with default state after system boot of Logic Low.

# Syntax

C/C++

I16 TRIG\_GetSoftTrg(U8 \*Status)

Visual Basic

TRIG\_GetSoftTrg (status As Byte) As Integer

# Parameters

Status

Returns the logic level of software trigger signal.

Returned value:

0: Logic low

1: Logic high

# Return Code

ERR\_NoError

ERR\_BoardNoInit

ERR\_Query\_Status

# A.2.7 TRIG\_Trigger\_Route\_Query Description

Acquires the current trigger signal routing path.

# Syntax

```txt
C/C++
```

```txt
I16 TRIG_Trigger_Route_Query (U32* source, U32* dest, U32* halfway)
```

# Visual Basic

TRIG\_Trigger\_Route\_Query (source As Long, dest As Long, halfway As Long) As Integer

# Parameters

source

Returns to the current source of trigger routing, with possible values including:

<table><tr><td>Available Definition</td><td>Defined Value</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>0</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>2</td></tr><tr><td>PXI_TRIG_VAL_SOFT</td><td>3</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>111</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>112</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>113</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>114</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>115</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>116</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>117</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>118</td></tr></table>

# dest

Returns to the current destination of trigger routing, with possible values including:

<table><tr><td>Available Definition</td><td>Defined Value</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>0</td></tr><tr><td>PXI_TRIG_VAL_SMB</td><td>2</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>111</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>112</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>113</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>114</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>115</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>116</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>117</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>118</td></tr></table>

# halfway

Returns to the current halfway point of trigger routing, with possible values including:

<table><tr><td>Available Value</td><td>Description</td></tr><tr><td>PXI_TRIG_VAL_NONE</td><td>0</td></tr><tr><td>PXI_TRIG_VAL_TRIG0</td><td>111</td></tr><tr><td>PXI_TRIG_VAL_TRIG1</td><td>112</td></tr><tr><td>PXI_TRIG_VAL_TRIG2</td><td>113</td></tr><tr><td>PXI_TRIG_VAL_TRIG3</td><td>114</td></tr><tr><td>PXI_TRIG_VAL_TRIG4</td><td>115</td></tr><tr><td>PXI_TRIG_VAL_TRIG5</td><td>116</td></tr><tr><td>PXI_TRIG_VAL_TRIG6</td><td>117</td></tr><tr><td>PXI_TRIG_VAL_TRIG7</td><td>118</td></tr></table>

# Return Code

ERR\_NoError

ERR\_BoardNoInit

ERR\_Query\_Status

# A.2.8 TRIG\_GetDriverRevision

# Description

Acquires the PXI Trigger software driver version; format of the version number is major.minor1.minor2.

# Syntax

```txt
C/C++
I16 TRIG_GetDriverRevision(unsigned short *major, unsigned short *minor1, unsigned short *minor2)
```

# Visual Basic

```txt
TRIG_GetDriverRevision (major As Integer, minor1 As Integer, minor2 As Integer) As Integer
```

# Parameters

```txt
major
Returns the major version number of the pxi trigger software driver
minor1
Returns the first minor version number of the pxi trigger software driver
minor2
Returns the second minor version number of the pxi trigger software driver
```

# Return Code

```txt
ERR_NoError
ERR_Query_Revision
```

# Appendix B BIOS Setup

# B.1 Entering the BIOS

1. Power on or reboot the PXIe-3988 controller.
2. Press the &lt;Delete&gt; or &lt;Esc&gt; key when the controller beeps. This should be concurrent with the main startup screen. The BIOS setup program loads after a short delay.
3. The Main menu is displayed when you first enter the BIOS setup program.

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this chapter.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# B.2 Navigation

The BIOS setup utility uses a key-based navigation system called hot keys. Most hot keys can be used at any time during navigation.

<table><tr><td>Key(s)</td><td>Function</td></tr><tr><td>Right Arrow, Left Arrow</td><td>Moves between different setup menus</td></tr><tr><td>Up Arrow, Down Arrow</td><td>Moves between options within a setup menu</td></tr><tr><td></td><td>Opens a sub-menu or displays all available settings for a highlighted configuration option</td></tr><tr><td></td><td>Returns to the previous menu and shortcuts to the Exit menu from top-level menus</td></tr><tr><td>&lt;+&gt; and &lt;--&gt;</td><td>Cycles between all available settings</td></tr><tr><td></td><td>Selects time and date fields</td></tr><tr><td></td><td>Opens the general help window for the BIOS</td></tr><tr><td></td><td>Loads previous values into the BIOS</td></tr><tr><td></td><td>Restores optimal default values into the BIOS</td></tr><tr><td></td><td>Saves the current configuration and exits BIOS setup</td></tr></table>

Table B-1: BIOS Hot Key Functions

![The diagram is titled with a top block labeled **BIOS Setup Utility**, which has a downward arrow pointing to **Screens**.\n\nFrom **Screens**, there is a downward arrow pointing to a horizontal row of connected blocks: **Screen 1** \$\leftrightarrow\$ **Screen 2** \$\leftrightarrow\$ **Screen 3** \$\leftrightarrow\$ **Screen 4** \$\leftrightarrow\$ **Screen 5**.\n*   A dotted arrow from a block labeled **Left and Right Keys to Select a Setup Screen** points to **Screen 1**.\n\nBelow **Screen 3**, there is a downward arrow pointing to **Items**.\n*   A dotted arrow from a block labeled **Tab Key to Select Fields** points to **Items**.\n\nFrom **Items**, a downward arrow points to a top row of three boxes labeled **±**, connected horizontally by double arrows.\n*   A dotted arrow from a block labeled **+ To Change Field Values** points to this top row.\n\nBelow the top row is a second row of three boxes labeled **±**, connected horizontally by double arrows.\n*   Vertical double arrows (up and down) connect the top and bottom rows.\n*   A dotted arrow from a block labeled **Up and Down Keys to Select a Setup Item** points to these vertical arrows.\n*   A bracket labeled **Fields** connects the top and bottom rows of boxes.](.pxie-3988-um-50m-00028-1000-10/26c554e550abefc01e1c2b085ad63c140a7059b35ee7eb21706b23342ce726b4.jpg)

Figure B-1: BIOS Setup Navigation

![The image features a white document icon with a folded top-right corner and faint horizontal lines. A large red checkmark is superimposed over the center of the document.](.pxie-3988-um-50m-00028-1000-10/843f236c82ae0f1f0c157baf36fbdd443f7f6253785ac8a3cb17a2574fe7ccdc.jpg)
NOTE:

A hot key legend is located in the right frame on most setup screens.

# B.3 Menu Structure

This section presents the primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The sub-sections that follow provide further details for each top-level menu and sub-menu and the setting options for each menu item. Default setting options are presented in bold and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>BIOS InformationSystem InformationBoard Information ▶System Date and Time</td></tr><tr><td>Advanced</td><td>CPU Configuration ▶Memory Configuration ▶Graphics Configuration ▶USB Configuration ▶TPM 2.0 Configuration ▶Onboard Devices Configuration ▶PCI and PCIe Configuration ▶Advanced Power Management ▶Network Stack Configuration ▶System Management ▶Flags ▶Power Consumption ▶Hardware Health Configuration ▶PXle Links Control Configuration ▶</td></tr><tr><td>Chipset</td><td>System Agent (SA) Configuration ▶PCH-IO Configuration ▶</td></tr><tr><td>Security</td><td>Password DescriptionAdministrator PasswordUser PasswordSecure Boot ▶</td></tr><tr><td>Boot</td><td>Boot ConfigurationCSM ▶FIXED BOOT ORDER PrioritiesUEFI Hard Disk Drive BBS Priorities ▶</td></tr><tr><td>Save &amp; Exit</td><td>Save OptionsDefault OptionsBoot Override</td></tr></table>

Note: ► indicates a sub-menu

# B.4 Main

The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details about each section/sub-menu.

# B.4.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Displays BIOS version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Date the ADLINK BIOS was built</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Memory reference code version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Graphics output protocol version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>ME firmware version</td></tr><tr><td>BIOS boot Source</td><td>Info only</td><td>Boot BIOS (primary or backup)</td></tr></table>

# B.4.2 System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Name</td><td>Info only</td><td>Displays model name</td></tr><tr><td>Link Cap</td><td>Info only</td><td>PCI Express link configuration to PXIe chassis2 link configurations: x8 x164 link configurations: x4 x4 x4 x4</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Displays board version</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Displays CPU model</td></tr><tr><td>Stepping</td><td>Info only</td><td>Displays CPU stepping</td></tr><tr><td>GT Info</td><td>Info only</td><td>Displays Intel Graphics GT info</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Displays CPU frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Displays installed memory size</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Displays memory frequency</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Displays PCH SKU</td></tr><tr><td>Stepping</td><td>Info only</td><td>Displays PCH stepping</td></tr></table>

# B.4.2.1 Board Information

<table><tr><td>Board Information</td><td>Options</td><td>Description</td></tr><tr><td>Serial Number</td><td>Info only</td><td>Displays SEMA S/N</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Displays SEMA manufacture date</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Displays last SEMA repair date</td></tr><tr><td>MAC ID</td><td>Info only</td><td>Displays SMC MAC ID</td></tr></table>

# B.4.2.2 Runtime Statistics

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Total Runtime</td><td>Info only</td><td>Specifies the total time in minutes the system has spent running in S0 state</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>Specifies the time in seconds the system has been running in S0 state, where the counter is cleared when the system is removed from the external power supply</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>Specifies the number of times external power has been shut off</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>Boot count is increased after a HW- or SW-Reset or successful power-up</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>Shows the event responsible for reboot of the system</td></tr></table>

# B.4.3 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock in hours, minutes, and seconds</td></tr></table>

# B.5 Advanced

Provides settings for most user interfaces in the system.

B.5.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info only</td><td>Displays CPU type</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Displays microcode revision</td></tr><tr><td>Speed</td><td>Info only</td><td>Displays CPU operating frequency</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Displays cache info</td></tr><tr><td>VMX</td><td>Info only</td><td>Displays presence/absence of Intel Virtualization Technology support</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Displays presence/absence of Intel SMX Technology support</td></tr><tr><td>VT-d</td><td>Disabled Enabled</td><td>Enables/disables VT-d function on MCH</td></tr><tr><td>Intel (VMX) Virtualization Technology</td><td>Disabled Enabled</td><td>Enables/disables support for Intel Virtualization technology</td></tr><tr><td>DTS SMM</td><td>Disabled Enabled</td><td>Disabled: ACPI thermal management uses EC reported temperatureEnabled: ACPI thermal management uses DTS SMM mechanism to determine CPU temperature</td></tr><tr><td>Hyper-Threading</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and disabled for other OS (not optimized); when Disabled only one thread per enabled core is active</td></tr><tr><td>Intel® SpeedStep(TM)</td><td>DisabledEnabled</td><td>Allows support for more than two frequency ranges</td></tr><tr><td>Intel® Speed Shift Technology</td><td>DisabledEnabled</td><td>Enable/Disable dynamically adjust processor operating frequency and voltage</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Enables/disables turbo mode</td></tr><tr><td>Configurable TDP Boot Mode</td><td>NominalDown UpDeactivated</td><td>Configures TDP Mode as Nominal/Down/Up/Deactivated, where Deactivated sets MSR to Nominal and MMI/O to Zero</td></tr><tr><td>Configurable TDP Lock</td><td>DisabledEnabled</td><td>Configurable TDP Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL When CTDP Lock is enabled, Custom ConfigTDP Count defaults to 1 and Custom ConfigTDP Boot Index to 0</td></tr><tr><td>Custom Configurable TDP</td><td>DisabledEnabled</td><td>Custom Configurable TDP settings</td></tr><tr><td>C States</td><td>DisabledEnabled</td><td>Enables/disables CPU C states</td></tr><tr><td>Package C State Limit</td><td>CPU DefaultC7C6C3C2C0/C1</td><td>Maximum Package C State limit</td></tr><tr><td>Intel Trusted Execution Technology</td><td>DisabledEnabled</td><td>Enables/disables Intel Trusted Execution Technology</td></tr></table>

# B.5.2 Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Displays Memory Reference Code version</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Displays memory frequency</td></tr><tr><td>Memory voltage</td><td>Info only</td><td>Displays memory voltage</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-RAS)</td><td>Info only</td><td>Displays memory timings</td></tr><tr><td>Channel 0 slot 0</td><td>Info only</td><td>Displays Channel 0</td></tr><tr><td>Channel 1 slot 0</td><td>Info only</td><td>Displays Channel 1</td></tr><tr><td>Channel 2 slot 1</td><td>Info only</td><td>Displays Channel 2</td></tr></table>

# B.5.3 Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Selects Graphics Translation Table size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512M1024MB2048MB</td><td>Selects Aperture size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0MB32MB64MB</td><td>Selects DVMT Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128MB256MBMAX</td><td>Selects DVMT Total Graphics Memory size used by the Internal Graphics Device</td></tr></table>

B.5.4 USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Module Version</td><td>Info only</td><td></td></tr><tr><td>USB Devices</td><td>Info only</td><td>Lists USB-connected peripheral devices</td></tr><tr><td>USB Controllers</td><td>Info only</td><td>Displays USB Controller type</td></tr><tr><td>USB Devices</td><td>Info only</td><td>Displays USB Devices</td></tr><tr><td>XHCI Compliance Mode</td><td>Disabled Enabled</td><td>Enables/Disables XHCI compliance mode</td></tr><tr><td>XDCI Support</td><td>Disabled Enabled</td><td>Enables/Disables XDCI support</td></tr><tr><td>USB Port Disable Overried</td><td>Disabled Enabled</td><td>Enables/Disables the USB port from reporting a device</td></tr></table>

B.5.5 TPM 2.0 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable Enable</td><td>Enable or disable BIOS support for security device</td></tr><tr><td>Active PCR Banks</td><td>Info only</td><td></td></tr><tr><td>Available PCR Banks</td><td>Info only</td><td></td></tr><tr><td>SHA-1 PCR Bank</td><td>Enabled Disabled</td><td>Enable or disable SHA-1 PCR Bank</td></tr><tr><td>SHA-256 PCR Bank</td><td>Enabled Disabled</td><td>Enable or disable SHA-256 PCR Bank</td></tr><tr><td>Pending Operation</td><td>None TPM Clear</td><td>Schedule an operation for the security device</td></tr><tr><td>Platform Hierarchy</td><td>Disabled Enabled</td><td>Enable or disable storage hierarchy</td></tr><tr><td>Storage Hierarchy</td><td>Disabled Enabled</td><td>Enable or disable storage hierarchy</td></tr><tr><td>Endorsement Hierarchy</td><td>Disabled Enabled</td><td>Enable or disable endorsement hierarchy</td></tr><tr><td>TPM2.0 UEFI Spec Version</td><td>TCG_1_2 TCG_2</td><td>TCG_1_2: Win8/10 compatibility mode TCG_2: New protocol and event format for Win10 or later</td></tr><tr><td>Physical Presence Spec Version</td><td>1.2 1.3</td><td>Instruct OS to support PPI spec version 1.2 or 1.3 (note that some HCK tests might not support version 1.3)</td></tr><tr><td>TPC 20 InterfaceType</td><td>Info only</td><td></td></tr></table>

# B.5.6 Onboard Devices Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">LAN Port Configuration</td></tr><tr><td>LAN1 Controller</td><td>EnabledDisabled</td><td>Enables/disables onboard I219 LAN controller</td></tr><tr><td>LAN2 Controller</td><td>EnabledDisabled</td><td>Enables/disables onboard I210 LAN controller</td></tr><tr><td colspan="3">UART Mode Control Configuration</td></tr><tr><td>COM1 Control</td><td>RS232RS422RS485</td><td>Selects serial port mode, from among RS232, RS422, and RS485</td></tr></table>

# B.5.7 PCI and PCIe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Above 4G Decoding</td><td>Disabled Enabled</td><td>Enables/disables Memory Mapped I/O BIOS assignment above 4GB</td></tr><tr><td>Holdoff Timer</td><td>0,1,2,3,4,5,6,7,8 sec</td><td>System delay for PCI Express Discovery</td></tr><tr><td>Native PCIe Enable</td><td>Disabled Enabled</td><td>Enables/disables native PCIe</td></tr></table>

# B.5.8 Advanced Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Wake System from S5</td><td>DisabledFixed TimeDynamic Time</td><td>Enables/disables system wake on alarm event, from among Fixed Time, where system wakes at the setting time, and Dynamic Time, in which system wakes at setting time later</td></tr><tr><td>PCIe Wake</td><td>EnabledDisabled</td><td>Enables/disables PCI Express bus and onboard LAN2 Controller (I210) wake capability</td></tr><tr><td>I219 LAN Wake</td><td>EnabledDisabled</td><td>Enables/disables onboard LAN1 Controller (I219) wake capability</td></tr><tr><td>Power-up Mode</td><td>Turn onRemain offLast state</td><td>Turn on: The machine starts automatically when the power supply is turned on.Remain off: The power button must be pressed to start the machine.Last state: When power is lost and then restored, the machine will either turn on or remain off according to its last power state.</td></tr></table>

# B.5.9 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Enabled Disabled</td><td>Enables/disables UEFI network stack</td></tr><tr><td>IPv4 PXE Support</td><td>Enabled Disabled</td><td>Enables/disables IPv4 PXE boot support</td></tr><tr><td>IPv6 PXE Support</td><td>Enabled Disabled</td><td>Enables/disables IPv6 PXE boot support</td></tr><tr><td>PXE Boot Wait Time</td><td>0 sec</td><td>Wait time for ESC key to abort PXE boot</td></tr></table>

# B.5.10 System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Firmware</td><td>Info only</td><td>Displays SEMA firmware</td></tr><tr><td>Build Date</td><td>Info only</td><td>Displays SEMA firmware build date</td></tr><tr><td>SEMA Bootloader</td><td>Info only</td><td>Displays SEMA boot loader</td></tr><tr><td>Build Date</td><td>Info only</td><td>Displays SEMA boot loader build date</td></tr></table>

# B.5.11 Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BMC Flags</td><td>Info only</td><td></td></tr><tr><td>BIOS Select</td><td>Info only</td><td>Displays the current BIOS ROM selection</td></tr><tr><td>ATX/AT-Mode</td><td>Info only</td><td>Displays ATX/AT mode</td></tr><tr><td>Exception Code</td><td>Info only</td><td>System exception reason</td></tr></table>

B.5.12 Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Current Input Current</td><td>Info only</td><td>Displays input current</td></tr><tr><td>Current Input Power</td><td>Info only</td><td>Displays input power</td></tr><tr><td>VCORE</td><td>Info only</td><td>Displays actual voltage of the power rail VCC_CORE</td></tr><tr><td>VCC-GT</td><td>Info only</td><td>Displays actual voltage of the power rail VCC-GT</td></tr><tr><td>1Vo5_A</td><td>Info only</td><td>Displays actual voltage of the power rail 1Vo5_A</td></tr><tr><td>VDDQ</td><td>Info only</td><td>Display actual voltage of the power rail VDDQ.</td></tr><tr><td>VRTC</td><td>Info only</td><td>Display actual voltage of the power rail VRTC.</td></tr><tr><td>V3P3S</td><td>Info only</td><td>Display actual voltage of the power rail V3P3S.</td></tr><tr><td>V3P3A</td><td>Info only</td><td>Display actual voltage of the power rail V3P3A.</td></tr><tr><td>V5S</td><td>Info only</td><td>Display actual voltage of the power rail V5S.</td></tr><tr><td>VCCST</td><td>Info only</td><td>Display actual voltage of the power rail VCCST.</td></tr><tr><td>VCCIO</td><td>Info only</td><td>Display actual voltage of the power rail VCCIO.</td></tr><tr><td>VCCSTG</td><td>Info only</td><td>Display actual voltage of the power rail VCCSTG.</td></tr><tr><td>VCCSA</td><td>Info only</td><td>Display actual voltage of the power rail VCCSA.</td></tr><tr><td>1V8_A</td><td>Info only</td><td>Display actual voltage of the power rail 1V8_A.</td></tr><tr><td>V5SBY</td><td>Info only</td><td>Display actual voltage of the power rail V5SBY.</td></tr><tr><td>V12</td><td>Info only</td><td>Display actual voltage of the power rail V12.</td></tr></table>

# B.5.13 Hardware Health Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Ambient temp of PCIe switch</td><td>Info only</td><td>Ambient temperature near PCIe switch</td></tr><tr><td>Core temp of PCIe switch</td><td>Info only</td><td>Core temperature of PCIe switch</td></tr><tr><td>+3.3V(System)</td><td>Info only</td><td>System +3.3V voltage</td></tr><tr><td>+5V(System)</td><td>Info only</td><td>System +5V voltage</td></tr><tr><td>+12V(System)</td><td>Info only</td><td>System +12V voltage</td></tr><tr><td>VBAT</td><td>Info only</td><td>Battery voltage</td></tr></table>

# B.5.14 PXIe Links Control Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Link Configuration</td><td>Info only</td><td>PCI Express link configuration to PXIe chassis</td></tr><tr><td>Link 1 Width, Speed</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Maximum PCI Express link mode for Link 1</td></tr><tr><td>Link 2 Width, Speed</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Maximum PCI Express link mode</td></tr></table>

# B.6 Chipset

B.6.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SA PCIe Code Version</td><td>Info only</td><td>Displays SA PCIe code version</td></tr><tr><td>VT-d</td><td>Info only</td><td>Displays virtualization technology for directed I/O (VT-d) support status.</td></tr></table>

B.6.1.1 PEG Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">PEG Port Configuration</td></tr><tr><td>PEG 0:1:0</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Enable root port</td><td>AutoDisableEnable</td><td>Auto/Enable/Disable the PCI Express bus root port</td></tr><tr><td>Max Link speed</td><td>AutoGen1Gen2Gen3</td><td>Sets maximum PCI Express link capability of the PCI Express bus root port</td></tr><tr><td>PEG 0:1:1</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Enable root port</td><td>AutoDisableEnable</td><td>Auto/Enable/Disable the PCI Express bus root port</td></tr><tr><td>Max Link speed</td><td>AutoGen1Gen2Gen3</td><td>Sets maximum PCI Express link capability of the PCI Express bus root port</td></tr><tr><td>PEG 0:1:2</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Enable root port</td><td>AutoDisableEnable</td><td>Auto/Enable/Disable the PCI Express bus root port</td></tr><tr><td>Max Link speed</td><td>AutoGen1Gen2Gen3</td><td>Sets maximum PCI Express link capability of the PCI Express bus root port</td></tr><tr><td>PEG 0:6:0</td><td>Info only</td><td>Link lanes and mode</td></tr><tr><td>Enable root port</td><td>AutoDisableEnable</td><td>Auto/Enable/Disable the PCI Express bus root port</td></tr><tr><td>Max Link speed</td><td>AutoGen1Gen2Gen3</td><td>Sets maximum PCI Express link capability of the PCI Express bus root port</td></tr></table>

# B.6.2 PCH-IO Configuration

B.6.2.1 PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Clock Gating</td><td>EnabledDisabled</td><td>Enable/Disable PCI Express Clock Gating</td></tr><tr><td>DMI Link ASPM control</td><td>EnabledDisabled</td><td>Enable/Disable Native Active State Power Management</td></tr><tr><td>PCIE port assigned to LAN</td><td>Info only</td><td>PCIe port number assigned to LAN</td></tr><tr><td>Compliance Test Mode</td><td>EnabledDisabled</td><td>Enable when using Compliance Load Board.</td></tr><tr><td>PCIe-USB Glitch W/A</td><td>EnabledDisabled</td><td>PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG Port.</td></tr><tr><td>PCIE function swap</td><td>EnabledDisabled</td><td>When Disabled, prevents PCIE root port function swap. If any function other than 0th is enabled, 0th will become visible.</td></tr><tr><td>PCIE Ports 0-3 Configuration</td><td>Info only</td><td>PCI Express port configuration info</td></tr></table>

B.6.2.2 SATA and RST Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>EnabledDisabled</td><td>Enables/disables SATA device</td></tr><tr><td>SATA Mode Selection</td><td>AHCIIDE</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td colspan="3">Software Feature Mask Configuration</td></tr><tr><td>Aggressive LPM support</td><td>EnabledDisabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Controller speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>Serial ATA port 0</td><td>Info only</td><td>SATA device info</td></tr><tr><td>Software preserve</td><td>Info only</td><td></td></tr><tr><td>Port 0</td><td>EnabledDisabled</td><td>Enable/Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>EnabledDisabled</td><td>Enable/Disable hot plug</td></tr><tr><td>Configured as eSATA</td><td>Info only</td><td></td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid state Drive</td><td>Set optimized operation mode for HDD or SSD</td></tr></table>

# B.7 Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td>Provides information about password characteristics as well as password length requirements: min. 3, max. 20</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>If ONLY the Administrator Password is set, then this only limits access to BIOS Setup and is only asked for when entering BIOS Setup</td></tr><tr><td>User Password</td><td>Enter password</td><td>If ONLY the User Password is set, then this is a power on password and must be entered to boot as well as to enter BIOS Setup and while in BIOS Setup the User will have Administrator rights</td></tr><tr><td>Secure Boot</td><td>Sub-menu</td><td>See section B.7.1 below</td></tr></table>

# B.7.1 Secure Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Attempt Secure Boot</td><td>Disabled Enabled</td><td>Determines whether Secure Boot will be attempted</td></tr></table>

B.8 Boot

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Boot Configuration</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key; to wait indefinitely, set to 65536 (0xFFFF)</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Set keyboard NumLock state at boot</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enable or disable Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td>Enable or disable boot with initialization of a minimal set of devices required to launch active boot option; has no effect for BBS boot options</td></tr><tr><td>CSM</td><td>Sub-menu</td><td>See section B.8.2 on page 61</td></tr><tr><td>Boot Mode Select</td><td>UEFI Legacy</td><td>Select Boot Mode</td></tr><tr><td>UEFI Hard Disk Drive BBS Priorities</td><td>Boot Option #1 to Boot Option #8</td><td>Priority of boot devices</td></tr><tr><td>FIXED BOOT ORDER Priorities</td><td>Boot Option #1 to Boot Option #8</td><td>Select which potential boot sources should be checked, and in what order, during the boot process</td></tr><tr><td>UEFI Hard Disk Drive BBS Priorities</td><td>Sub-menu</td><td>See section B.8.2 on page 61</td></tr></table>

# B.8.1 CSM

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>EnabledDisabled</td><td>Determines whether CSM will launch</td></tr><tr><td>CSM16 Module Version</td><td>Info only</td><td>Displays the CSM16 module version number</td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>UPON REQUEST means GA20 can be disabled using BIOS services, ALWAYS means GA20 cannot be disabled; useful when any RT code is executed above 1MB</td></tr><tr><td>Boot Option Filter</td><td>UEFI andLegacyLegacy onlyUEFI only</td><td>Controls to which devices the system can boot</td></tr><tr><td colspan="3">Option ROM Execution</td></tr><tr><td>Network</td><td>Do not launchLegacy onlyUEFI only</td><td>Controls execution of UEFI and Legacy PXE OpROM</td></tr><tr><td>Storage</td><td>Do not launchUEFILegacy only</td><td>Controls execution of UEFI and Legacy Storage OpROM</td></tr><tr><td>Video</td><td>Do not launchUEFILegacy only</td><td>Controls execution of UEFI and Legacy Video OpROM</td></tr><tr><td>Other PCI Devices</td><td>UEFILegacy</td><td>For PCI devices other than Network, Mass Storage, or Video, defines the OpROM to launch</td></tr></table>

# B.8.2 UEFI Hard Disk Drive BBS Priorities

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Option</td><td>Windows Boot Manager Disable</td><td>Allows specification of a UEFI HDD BBS priority boot option</td></tr></table>

# B.9 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td colspan="3">Save Options</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Saves changes and exits system setup</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Discards changes and exits system setup</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Saves changes and resets system</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Discards changes and resets system</td></tr><tr><td>Save Changes</td><td></td><td>Save changes made so far to setup options</td></tr><tr><td>Discard Changes</td><td></td><td>Discards changes made so far to setup options</td></tr><tr><td colspan="3">Default Options</td></tr><tr><td>Restore Defaults</td><td></td><td>Restores/loads default values for all setup options</td></tr><tr><td>Save as User Defaults</td><td></td><td>Saves changes made so far as User Defaults</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restores User Defaults to all setup options</td></tr><tr><td colspan="3">Boot Override</td></tr><tr><td>Launch EFI Shell from filesystem device</td><td></td><td>Attempts to launch EFI shell application (shell.efi) from an available filesystem device</td></tr></table>

# Appendix C Dual BIOS

Dual BIOS is a backup function that maintains normal operation of the PXIe system module when unexpected boot failure occurs under the default BIOS. Dual BIOS consists of a main BIOS, a backup BIOS, and an independent controller. In normal boot, the main BIOS powers on and boots the system into the OS, monitored by the independent controller. If the main BIOS malfunctions, for example, as the result of corruption incurred by a failed update, boot procedure is terminated abnormally. The backup BIOS is then activated automatically to perform boot procedure. When backup BIOS is activated, during BIOS power-on, notifications are generated indicating that backup BIOS has been deployed. To restore main BIOS function, contact technical support.

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# Appendix D Legacy Boot Mode Settings

UEFI boot mode is default for the PXIe-3988 BIOS.

To boot in legacy boot mode, change related settings in the BIOS menu:

1. Power on and press &lt;DEL&gt; or &lt;ESC&gt; to enter BIOS menu
2. Move to Boot
3. Under “Boot mode select” select “LEGACY”
4. Move to Boot, CSM
5. Under “CSM Support” select “Enabled”
6. Under “Network” select “Legacy”
7. Under “Storage” select “Legacy”
8. Under “Video” select “Legacy”
9. Under “Other PCI devices” select “Legacy”
10.Press &lt;F10&gt; and &lt;Enter&gt; to save and exit BIOS menu. The system will restart and apply settings for Legacy boot mode.

To restore UEFI boot mode:

1. Power on and press &lt;DEL&gt; or &lt;ESC&gt; to enter BIOS menu
2. Press &lt;F9&gt; and &lt;Enter&gt; to load optimized defaults
3. Press &lt;F10&gt; and &lt;Enter&gt; to save and exit BIOS menu

The system restarts and default settings for UEFI boot mode are applied.

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# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.

 Read these safety instructions carefully.
 Keep the User’s Manual for future reference.
 Read the Specifications section of this manual for detailed information on the recommended operating environment.
 The device can be operated at an ambient temperature of 55ºC.

When installing/mounting or uninstalling/removing device, or when removal of a chassis cover is required for user servicing (See “Getting Started” on page 17.):

 Turn off power and unplug any power cords/cables.
 Reinstall all chassis covers before restoring power.

 To avoid electrical shock and/or damage to device:

 Keep device away from water or liquid sources.
 Keep device away from high heat or humidity.
 Keep device properly ventilated (do not block or cover ventilation openings).

 Always use recommended voltage and power source settings.

 Always install and operate device near an easily accessible electrical outlet.

 Secure the power cord (do not place any object on/over the power cord).

 Only install/attach and operate device on stable surfaces and/or recommended mountings.

 If the device will not be used for long periods of time, turn off and unplug it from its power source

 Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools

 A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image displays a standard safety warning sign featuring a yellow triangle with a black border and a black exclamation point in the center. Below the triangle is a white rectangle containing the text 'CAUTION:' in bold black capital letters.](.pxie-3988-um-50m-00028-1000-10/f2d49c240b1e3246e4b4d85538afff618bd3c81ed849b2d0c1e5d0f8efdf7e95.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

 The device must be serviced by authorized technicians when:

 The power cord or plug is damaged.
 Liquid has entered the device interior.
 The device has been exposed to high humidity and/or moisture.
 The device is not functioning or does not function according to the User’s Manual.
 The device has been dropped and/or damaged and/or shows obvious signs of breakage.

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

 It is recommended that the device be installed only in a server room or computer room where access is:

 Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.

 Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

<table><tr><td>&lt;img src="images/d75026adffcae3abb93d86215149c6bc919895fd80e385f06a030417d0865b8d.jpg"/&gt;</td><td>BURN HAZARDTouching this surface could result in bodily injury.To reduce risk, allow the surface to cool before touching.RISQUE DE BRÛLURESNe touchez pas cette surface, cela pourrait entraîner des blessures.Pour éviter tout danger, laissez la surface refroidir avant de la toucher.</td></tr></table>

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

9F, No.166 Jian Yi Road, Zhonghe District

New Taipei City 235, Taiwan

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

+1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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