# PXIe-9529H

# User’s Manual

8-CH 24-Bit 256 kS/s

Dynamic Signal Acquisition Module

![Exterior view of a ADLINK Technology Inc. processor module with gold connectors and a green circuit board (no readable text or symbols beyond branding)](.pxie-9529h-50m-38205-1010-11/c77617e405561fec5781afd1643d5a8278f32e56d8b98518ff5558037c176815.jpg)

Manual Rev.: Rev. 1.1

Revision Date: June 12, 2025

Part Number: 50M-38205-1010

# Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-04-01</td><td>AL</td></tr><tr><td>1.1</td><td>Crosstalk spec updated</td><td>2025-06-12</td><td>CC</td></tr></table>

# Preface

# Copyright

Copyright 2025 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with no text or labels, accompanied by a blank rectangular block below (no text or symbols present)](.pxie-9529h-50m-38205-1010-11/aac19c9bbe3fc01aaefebe605be330a46e9de21a2598a79d816bf57e1eb37c0a.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.pxie-9529h-50m-38205-1010-11/5653c672a5798851521362c497ccff2724db70b4682e4e425f1eaa2875dcccc4.jpg)

![Li-ion](.pxie-9529h-50m-38205-1010-11/766272268eef912d6b304f42a5aa2fd3bf110e68779c13ba1ed7200340d72368.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.pxie-9529h-50m-38205-1010-11/9c8f2e5f090260dcaac012be5a648bd10800bb64b5e781e78c6efce10a8de86a.jpg)

![廢電池請回收](.pxie-9529h-50m-38205-1010-11/8fd4b4994c8a624536828b464acf376cc603e262774987e60935ee688b02b2d1.jpg)

# California Proposition 65 Warning

![The image displays a standard warning symbol. It consists of a bright yellow triangle with a thick black border. Centered within the triangle is a large black exclamation mark.](.pxie-9529h-50m-38205-1010-11/381921fe41e1e9268676cfa7ddcd8088120f67b12dec328629a191702dde9a07.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![A white document icon with a folded top-right corner and horizontal lines, overlaid with a large red checkmark.](.pxie-9529h-50m-38205-1010-11/00780d9aafa2ba609541b7d7c0d86b416f176223d8b09d316d55c3cc82490ad1.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign with a thick black border featuring a large black exclamation point in the center.](.pxie-9529h-50m-38205-1010-11/a093356d86b8b1041c60f40282ef5d14f75fbf1ddd851bfd3188ab2028ca2a49.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![A red triangle containing a white exclamation point.](.pxie-9529h-50m-38205-1010-11/e2cb8e99da96c933229ca7f40fc30cdc44320ddd23b1852fcd27a45635731939.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

Preface...

List of Figures .... ..vi

List of Tables...... ..vi

1 Introduction....

1.1 Overview..
1.2 Features.. .7
1.3 Applications . .7
1.4 Software Support ...

2 Getting Started... .11

2.1 Installation Environment.. .11
2.2 Module Installation ... .11

3 Specifications ... .13

3.1 Analog Input... ..13
3.2 Timebase. ..13
3.3 Triggers.. ..13
3.4 General Specifications .. ..14

4 Mechanical Layout .. .15

4.1 Device Layout .. .15
4.2 I/O Array ...... ...16

5 Operations............ .17

5.1 Functional Block Diagram . .17
5.2 Analog Input Chanel . .17
5.3 Trigger Source and Trigger Modes.. ..19
5.4 Trigger Mode . .22
5.5 ADC Timing Control ... .23
5.6 Synchronizing Multiple Modules... .23

6 Appendix A Calibration ........... .25

6.1 Calibration Constant . ..25
6.2 Auto-Calibration . .25

Safety Instructions.... .26

Getting Services..... .28

# List of Figures

Figure 1: PXIe-9529H schematic.. ..15

Figure 2: PCIe-9529H I/O array.. ..16

Figure 3: Functional block diagram. .17

Figure 4: Analog input architecture. .17

Figure 5: Linked list of PCI address DMA descriptors... ..19

Figure 6: Trigger architecture .. ..19

Figure 7: External digital trigger.. ..20

Figure 8: Analog trigger conditions . .21

Figure 9: Post-trigger acquisition . .22

Figure 10: Delay trigger mode acquisition.. .22

Figure 11: Re-trigger mode acquisition. .23

Figure 12: Timebase architecture.. ..23

# List of Tables

Table 1: Input range and data format.. ..18

Table 2: Input range midscale values ... .18

Table 3: Preferred characteristics for analog triggers .21

Table 4: Configuration for synchronizing multiple modules .. .24

Table 5: SSI timing signal definitions .. .24

# 1 Introduction

# 1.1 Overview

The PXIe-9529H is a high-performance 8-CH 24-bit 256 kS/s dynamic signal acquisition module, specifically designed for structural health monitoring, noise, vibration, and harshness (NVH) measurement, and phased array data acquisition.

The PXIe-9529H features 24-bit simultaneous sampling at 256 kS/s over 8 channels, and a 105 dB dynamic range, providing ample power for high-density, high channel count signal measurement, and vibration-optimized lower AC cutoff frequency of 0.3 Hz. All input channels incorporate a 4 mA bias current for integrated electronic piezoelectric (IEPE) signal conditioning for accelerometers and microphones.

The PXIe-9529H is auto-calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors. Following auto-calibration, the calibration constant is stored in EEPROM, so these values can be loaded and used as needed by the board. There is no requirement to calibrate the module manually.

# 1.2 Features

24-bit high-resolution
8 simultaneous analog inputs
256 kS/s maximum sampling rate with 105 dB dynamic range
• AC(0.3Hz), or DC coupling, software selectable
IEPE – 4mA, software configurable

# 1.3 Applications

Structural health monitoring
Phase array data acquisition
Noise, vibration, and harshness (NVH) detection
• Machine status monitoring

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website. Commercial software drivers are protected with licensing authorization codes. Without an authorization code, you can install and run the demo version for trial/demonstration purposes for up to two hours. Contact your ADLINK dealer to purchase a software license. ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation, and PXI platforms.

By leveraging low-level kernel management and a user-friendly API, users can easily manage devices under a Windows environment and focus on developing applications.

![Based on the provided image, here is an accurate and concise description of the blocks and their arrangement:\n\n**Top Layer (User Interface & Management)**\n*   **Left Vertical Block:** A red section labeled 'MAPS Core' and 'Device Management'. It contains four gray buttons: 'Device Manager (ACE)', 'PXI Platform Resource Mgmt. Utility', 'PXI Platform ChassisWatch Utility', and 'DAQ/IO Module Function Test Utility'.\n*   **Right Section (White Blocks):** Three columns labeled 'User APPs in C/C++', 'User APPs in LabVIEW', and 'User APPs in C#'. These sit adjacent to the 'MAPS Core Device Management' block.\n\n**Middle Layer (SDKs & Runtime)**\n*   **SDK Blocks:** Directly below the 'User APPs' blocks are three colored rectangles:\n    *   Orange: 'MAPS/C', 'C/C++ SDK for DAQ/IO module'.\n    *   Green: 'MAPS/LV', 'LabVIEW SDK for DAQ/IO module'.\n    *   Purple: 'MAPS/C#', 'C# SDK for DAQ/IO module', 'Coming soon'.\n*   **Runtime Bar:** A full-width red bar below the SDKs labeled 'MAPS Core -Device Runtime'. To its right, it lists: 'PXI Platform Service', 'DAQ/IO Module Device Driver', and 'DAQ/IO Module Runtime Library'.\n\n**Bottom Layer (Hardware)**\n*   A blue/grey horizontal strip at the bottom displaying hardware images with labels: 'Digitizers', 'DAQ', 'Edge Platform', 'PXIe Controllers', and 'PXIe/PXI Chassis'.\n\n**Connections (Implicit Hierarchy)**\n*   The 'User APPs' blocks sit directly above their corresponding SDK blocks ('MAPS/C', 'MAPS/LV', 'MAPS/C#').\n*   The SDK blocks and the 'MAPS Core Device Management' column sit above the 'MAPS Core -Device Runtime' bar.\n*   The 'MAPS Core -Device Runtime' bar sits above the hardware layer ('Digitizers', 'DAQ', etc.).](.pxie-9529h-50m-38205-1010-11/b3e3b6c20c0abc688c5979a6103cfa53b273fead1f8d84a9a04d88f5f4f646db.jpg)

# 1.4.1 MAPS Core

ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system-level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access. MAPS Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service. MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules to reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPCI\n0: PCIe9141 Device 'PCIE'\n0: PCIe9101 Device 'PCIE'\nUSB\nNETWORK\nGeneral\nSettings\nAlias Name	PCIE-9141-0\nVendor	ADLINK Technology Inc.\nModel	PCIE9141 Device\nPCI Bus	2\nPCI Device	0\nPCI Function	0\nDMA Buffer\nAI	1024 KB\nAO	1024 KB\nDI	1024 KB\nDO	1024 KB\nUtility\nSoftFrontPanel	Launch\nSave\nPlease reboot your system to activate driver registry](.pxie-9529h-50m-38205-1010-11/cb5ca0546b52bcc5642452d29f226dd91850766832df6d1019b0ad29e20732f9.jpg)

ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control DAQ cards through the UI and display the acquired waveform/data on the screen.

# 1.4.2 MAPS/LV, LabVIEW Support

Customers who develop their own programs in LabVIEW must install the MAPS/LV software package. MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. For more information, download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual:

https://www.adlinktech.com/Products/Data\_Acquisition/DAQSoftware\_Utility/MAPS\_LV

# 1.4.3 MAPS/C, C& C++ Support

Customers who develop their own programs in a C or C++ environment must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library, and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website.

https://www.adlinktech.com/Products/Data\_Acquisition/DAQSoftware\_Utility/MAPS\_C

This page intentionally left blank.

# 2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents, and basic information users should be aware of regarding the PCIe-9529H.

![The image displays a graphic of a white document or sheet of paper featuring a folded top-left corner and horizontal grey lines across the lower portion. A large, bold red checkmark is superimposed diagonally over the center of the document.](.pxie-9529h-50m-38205-1010-11/3ce4bd9f4f91e4e4e6b80c7501d652dfc14e769540d5b031447b0902aceafbb8.jpg)
NOTE

Diagrams and illustrated equipment are for reference only.

Actual system configuration and specifications may vary.

# 2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and crosshead screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

# Recommended Installation Tools

Philips (cross-head) screwdriver
• Flat-head screwdriver
Anti-static wrist strap
Antistatic mat

ADLINK PXIe-9529H DSA modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage, as shipping and handling could affect the equipment inside. Ensure that the equipment and its components are undamaged before installation.

![The image displays a yellow triangular warning sign with a black border. Centered inside the triangle is a large black exclamation mark consisting of a vertical line and a dot below it.](.pxie-9529h-50m-38205-1010-11/9017f934383312657889b7f3773568d4966e434500981e9b5ed835f0cd4075a7.jpg)
CAUTION:

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

# Package Contents

PXIe-9529H dynamic signal acquisition module

If the item is missing or damaged, please contact the dealer.

![The image displays a red, upward-pointing triangle containing a white exclamation mark in the center, set against a white background.](.pxie-9529h-50m-38205-1010-11/6083690df293a82c02e6a8ff8f016c242e53ee6c915bd75ea143c1dd9fb1dcbb.jpg)
WARNING:

Do not install or power on damaged equipment or equipment missing components. Retain the shipping carton and packing materials for inspection. Contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Module Installation

1. Turn off the PXI system/chassis and disconnect the power cable from the power source.
2. Align the module edge with the module guide in the PXI chassis.
3. Slide the module into the chassis until resistance is felt from the PXI connector.
4. Push the ejector upwards and firmly seat the module into the chassis.
5. Once the module is fully seated, a “click” can be heard from the ejector latch.
6. Tighten the screw on the front panel.
7. Connect the power plug to a power source and turn on the PXI system/chassis.

This page intentionally left blank.

# 3 Specifications

# 3.1 Analog Input

<table><tr><td colspan="3">Analog Input</td></tr><tr><td colspan="2">Number of Channels</td><td>8 (simultaneously)</td></tr><tr><td colspan="2">Resolution</td><td>24-bit</td></tr><tr><td colspan="2">Sampling Rate</td><td>8 kS/s to 256 kS/s</td></tr><tr><td colspan="2">Bandwidth (-3 dB)</td><td>0.433FS</td></tr><tr><td colspan="2">Input Range</td><td>±1 V, ±10 V</td></tr><tr><td colspan="2">Input configuration</td><td>Differential, Pseudo-differential</td></tr><tr><td rowspan="2">Input impedance</td><td>Between positive input and system ground</td><td>1 MΩ</td></tr><tr><td>Between negative input and system ground</td><td>Differential Configuration: 1 MΩPseudo-differential Configuration: 50 Ω</td></tr><tr><td colspan="2">Input coupling</td><td>AC, DC (software selectable)</td></tr><tr><td colspan="2">AC coupling cutoff frequency (-3 dB)</td><td>0.3 Hz</td></tr><tr><td colspan="2">Integrated Electronic Piezoelectric (IEPE)</td><td>Current: 4 mA for each channelIEPE compliance: 24 V</td></tr><tr><td rowspan="2">Overvoltage protection</td><td>Differential</td><td>±42.4V</td></tr><tr><td>Pseudo-differential</td><td>Positive terminal: ±42.4VNegative terminal: Not protected, rated at ±2.5V</td></tr><tr><td colspan="2">Offset error</td><td>±0.2 mV max</td></tr><tr><td colspan="2">Gain error</td><td>±0.05% max</td></tr><tr><td colspan="2">System Noise</td><td>40 μVrms ( $f_s$ =256 kS/s)</td></tr><tr><td rowspan="2">SNR</td><td>±1 V Input Range</td><td>91 dB ( $f_s$ =256 kS/s)</td></tr><tr><td>±10 V Input Range</td><td>93 dB ( $f_s$ =256 kS/s)</td></tr><tr><td rowspan="2">THD</td><td>±1 V Input Range</td><td>-118 dB ( $f_s$ =256 kS/s)</td></tr><tr><td>±10 V Input Range</td><td>-113 dB ( $f_s$ =256 kS/s)</td></tr><tr><td rowspan="2">Dynamic range</td><td>±1 V Input Range</td><td>104 dB ( $f_s$ =256 kS/s)</td></tr><tr><td>±10 V Input Range</td><td>105 dB ( $f_s$ =256 kS/s)</td></tr><tr><td colspan="2">Crosstalk</td><td>-105 dB</td></tr></table>

# 3.2 Timebase

<table><tr><td colspan="2">Timebase</td></tr><tr><td>Delay trigger timebase</td><td>125 MHz</td></tr><tr><td>Sample clock timebase</td><td>Internal: Onboard synthesizer (10 MHz)External: PXIe backplane 10 MHz</td></tr></table>

# 3.3 Triggers

<table><tr><td colspan="2">Trigger</td></tr><tr><td>Trigger source</td><td>Software trigger, Analog trigger, External digital trigger, PXI STAR trigger, PXI trigger bus [0..7]</td></tr><tr><td>Trigger mode</td><td>Post trigger, Delay trigger</td></tr><tr><td>External digital trigger</td><td>5 V TTL compatibilityTrigger polarity: Rising edge, Falling edgePulse width : 20 ns minimum</td></tr></table>

3.4 General Specifications

<table><tr><td colspan="2">General Specifications</td></tr><tr><td>I/O Connector</td><td>SMB x 8 for analog inputsSMB x 1 for external digital input</td></tr><tr><td>Dimensions</td><td>160 (W) x 100 (H) mm (6.24&quot; x 3.9&quot;)(not including connectors)</td></tr><tr><td>Ambient Temperature</td><td>Operation: 0°C to 55°C (32°F to 131°F)Storage: -20°C to 80°C (-4°F to 176°F)</td></tr><tr><td>Relative Humidity</td><td>10% to 90%, non-condensing</td></tr><tr><td>Certifications</td><td>EMC/EMI : CE, FCC Class A</td></tr></table>

# 4 Mechanical Layout

![The image displays a white document icon with faint horizontal lines, overlaid by a large red checkmark. Below the graphic is the text 'NOTE:' in black capital letters.](.pxie-9529h-50m-38205-1010-11/d578c4948f887ca148a5485864e47919b28f513a089aa24eb688ad4ec9f36c59.jpg)

All dimensions shown are in millimeters.

# 4.1 Device Layout

![| Dimension         | Value   |\n| ----------------- | ------- |\n| Width (CB width)  | 165.04  |\n| Width (CB width)  | 162.54  |\n| Width (CB width)  | 160     |\n| Total Width (CB width) | 200.73 |\n| Height (cm)       | 100     |](.pxie-9529h-50m-38205-1010-11/83a3c2cc15820b833870e1533b375dba62010f5a79fc7b87515e2d0f7e6a6988.jpg)

Figure 1: PXIe-9529H schematic

# 4.2 I/O Array

The PXIe-9529H I/O array is labeled to indicate connectivity, as shown below.

![ADLINK\nPXIe-9529H\nTRQ\nIN\nCH0\nCH1\nCH2\nCH3\nCH4\nCH5\nCH6\nCH8\nCH7](.pxie-9529h-50m-38205-1010-11/df4d96e29a950db999a53debfb767372c68218aeb53d734b81ce4bd31d602620.jpg)

Figure 2: PCIe-9529H I/O array

# 5 Operations

This chapter contains information regarding analog input, triggering, and timing for the PXIe-9529H.

# 5.1 Functional Block Diagram

![**Labeled Blocks:**\n\n*   **Analog Inputs:** CH0, CH1, CH2, CH3, CH4, CH5, CH6, CH7\n*   **Amplifiers:** PGA (Programmable Gain Amplifier) - there are 8 total, arranged in two columns.\n*   **Converters:**\n    *   Quad 24bit ADC no.0 (containing 4 ADC blocks)\n    *   Quad 24bit ADC no.1 (containing 4 ADC blocks)\n*   **Control/IO:**\n    *   Reference & Calibration\n    *   TRG IN\n    *   IO Control\n    *   MUX\n*   **Clocking:**\n    *   OSC10M\n    *   CLK Synthesizer\n*   **Interconnect:**\n    *   Board to Board Connector x 2 (Vertical black bar)\n*   **Digital Processing:**\n    *   FPGA (containing: PCIe controller, ADC Control, Trigger Control, AI Data Processing, FIFO Interface, Remote Update)\n    *   flash\n*   **Peripheral Interface:**\n    *   PXIe Hybrid Peripheral Slot (Vertical black bar)\n    *   XJ4\n    *   XJ3\n*   **Power:**\n    *   DC-DC converter, LDO\n\n**Connections and Signals:**\n\n*   **Analog Front End:**\n    *   Inputs **CH0**, **CH1**, **CH2**, **CH3** and **CH4**, **CH5**, **CH6**, **CH7** connect to the **PGA** blocks.\n    *   **PGA** blocks connect to the **ADC** blocks within the 'Quad 24bit ADC' groups.\n    *   **Reference & Calibration** connects to the **PGA** column.\n    *   **TRG IN** connects to **IO Control**.\n    *   **Quad 24bit ADC no.0** connects via **ADC Data & Control bus no.0** to the **Board to Board Connector x 2**.\n    *   **Quad 24bit ADC no.1** connects via **ADC Data & Control bus no.1** to the **Board to Board Connector x 2**.\n    *   **IO Control** connects via a thick arrow to the **Board to Board Connector x 2**.\n\n*   **Clocking:**\n    *   **OSC10M** connects via **OSC 10M** to **MUX**.\n    *   **Board to Board Connector x 2** connects via **PXI CLK 10M** to **MUX**.\n    *   **MUX** connects to **CLK Synthesizer**.\n    *   **Board to Board Connector x 2** connects via **PXIe_DSTARAPIN** to **CLK Synthesizer**.\n    *   **CLK Synthesizer** connects via **ADC_CLKIN_A** to **Quad 24bit ADC no.0**.\n    *   **CLK Synthesizer** connects via **ADC_CLKIN_B** to **Quad 24bit ADC no.1**.\n    *   **CLK Synthesizer** connects via **FPGA_MCLK** to **Board to Board Connector x 2**, which then connects via **FPGA_MCLK** to the **FPGA**.\n\n*   **FPGA and Peripheral Interface:**\n    *   **Board to Board Connector x 2** connects to **FPGA** via **ADC Data & Control bus no.0/no.1** (arrow points towards the connector).\n    *   **FPGA** connects to **PXIe Hybrid Peripheral Slot** via **PCIe Gen1 x1** (bidirectional).\n    *   **FPGA** connects to **flash** (bidirectional).\n    *   **PXIe Hybrid Peripheral Slot** connects to **FPGA** via **PXIe_DSTARAPIN**, **PXIe_DSTARB_PIN**, and **PXIe_DSTARC_PIN** (arrows point towards FPGA).\n    *   **PXIe Hybrid Peripheral Slot** connects to **FPGA** via **PXI CLK 10M** (arrow points towards FPGA).\n    *   **FPGA** connects to **PXIe Hybrid Peripheral Slot** via **Geographical Address(6:0)** and **PXI Trigger bus(7:0)** (arrows point towards the slot).\n    *   **PXIe Hybrid Peripheral Slot** connects to **XJ4** and **XJ3**.\n\n*   **Power Distribution:**\n    *   **DC-DC converter, LDO** connects to **Board to Board Connector x 2** and **PXIe Hybrid Peripheral Slot** via power rails labeled **3.3V**, **5V**, and **12V**.](.pxie-9529h-50m-38205-1010-11/82fbe524ff7f5990140c92b499acf786f3e81ec7d0316d8ae3228f758bb7c54e.jpg)

Figure 3: Functional block diagram

# 5.2 Analog Input Chanel

# 5.2.1 Analog Input Front-End Configuration

![Based on the provided circuit diagram, here is an accurate and concise description of the blocks and their connections:\n\n**Input and Signal Conditioning Section (Left to Center)**\n*   **Signal Source:** A circle labeled with **G** connects to a main horizontal signal line.\n*   **Branching Connections:**\n    *   The main line branches upward through an **SPST** switch to a terminal labeled **IEPE+**.\n    *   The main line branches downward through an **SPST** switch to a terminal labeled **IEPE-**.\n    *   The main line branches downward through an **SPST** switch to a **49.9R** resistor connected to ground.\n*   **Signal Switch:** The main line continues to a block labeled **Signal Switch**, which is a dual-pole switch mechanism:\n    *   **Top Path:** Connects the signal to either **CAL+** or a capacitor labeled **330nF / 25V**.\n    *   **Bottom Path:** Connects the signal to either **CAL-** or a capacitor labeled **330nF / 25V**.\n*   **Termination:** The outputs from the **Signal Switch** connect to nodes with **1MR** resistors that go to ground. These nodes feed into the amplifier.\n\n**Amplification and Conversion Section (Center to Right)**\n*   **Amplifier:** The signals enter a triangle block labeled **X1 X10 PGA** (Programmable Gain Amplifier).\n*   **ADC:** The output of the PGA connects to a block labeled **24-bit ADC**.\n*   **ADC Connections:**\n    *   The ADC connects to a block labeled **CARR** via three lines: **DATA**, **SCK**, and **ADC Ctrl**.\n    *   The ADC also connects downward to a **Vref** block.\n\n**Calibration Circuit (Bottom Left)**\n*   **Reference Voltage:** A square block labeled **Vref** connects to a resistor divider network consisting of two **10k** resistors in series (the bottom resistor connects to ground).\n*   **Cal Switch:** A switch labeled **Cal+** connects to this network:\n    *   One position connects to the top of the upper **10k** resistor (full Vref).\n    *   The other position connects to the node between the two **10k** resistors (split Vref).\n    *   The output of this switch is labeled **Cal+**.](.pxie-9529h-50m-38205-1010-11/86f3d032e2e01d0a31c7f3c1633b6f7c8dc1a7961d7d423504984993fba4aadd.jpg)

Figure 4: Analog input architecture

# Differential and Pseudo-Differential Input Configuration

The PXIe-9529H provides both differential and pseudo-differential input configurations, with differential input mode providing voltage to the anode and cathode inputs of the SMB connector according to the signal voltage difference between them. If the signal source is ground-referenced, differential input mode can be used for common-mode noise rejection. If the signal source is a floating signal, pseudo-differential input mode can provide a reference ground connected to the cathode input of the SMB through a 50 Ω resistor, preventing the floating source from drifting over the input common-mode range.

Recommended configurations for the signal sources are as follows.

<table><tr><td>Signal Source Type</td><td>Card Configuration</td></tr><tr><td>Floating</td><td>Pseudo Differential</td></tr><tr><td>Ground-Reference</td><td>Differential</td></tr></table>

# AC and DC Input Coupling

AC and DC coupling are available. With DC coupling, the DC offset present in the input signal is passed to ADC, and is indicated if the signal source has a small level of offset voltage or if the DC content of the signal is important. In AC coupling, the DC offset present in the input signal is erased, and is indicated if the DC content of the input signals is to be rejected. AC coupling enables a high-pass R-C filter through the input signal path. The corner frequency (-3dB) is about 0.3Hz.

# Input for IEPE

For applications that require sensors such as accelerometers or microphones, the PXIe-9529H provides an excitation current source. The common excitation current is usually about 4mA for these IEPE sensors. A DC voltage offset is generated due to the excitation current and sensor impedance. When IEPE current sources are enabled, the PXIe-9529H automatically sets input configuration to AC coupling.

# 5.2.2 Input Range and Data Format

Table 1: Input range and data format

<table><tr><td>Description</td><td>Full-scale range</td><td>Least significant bit</td><td>FSE-1LB</td><td>-FSR</td></tr><tr><td rowspan="2">Bipolar Analog Input</td><td>±10 V</td><td>1.19 μV</td><td>9.99999881 V</td><td>-10 V</td></tr><tr><td>±1 V</td><td>0.119 μV</td><td>0.999999881V</td><td>-1 V</td></tr><tr><td>Digital Code</td><td>N/A</td><td>N/A</td><td>7FFFFFF</td><td>800000</td></tr></table>

Table 2: Input range midscale values

<table><tr><td>Description</td><td>Midscale +1LSB</td><td>Midscale</td><td>Midscale-1LB</td></tr><tr><td rowspan="2">Bipolar Analog Input</td><td>1.19 μV</td><td>0V</td><td>-1.19 μV</td></tr><tr><td>0.119 μV</td><td>0V</td><td>-0.119 μV</td></tr><tr><td>Digital Code</td><td>000001</td><td>000000</td><td>-FFFFFF</td></tr></table>

# 5.2.3 DMA Data Transfer

The PXIe-9529H, as a PCI Express Gen1 X 4 device, provides a 256 kS/s sampling rate ADC, generating an 8.192 MByte/second rate. To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve the full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once the analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a userdefined DMA buffer in the computer.

Using a high-level programming library for high-speed DMA data acquisition, the sampling period and the number of conversions need simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA. In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or others, it is difficult to allocate a large continuous memory block.

Therefore, the bus controller provides DMA transfer with a scatter-gather function to link non-contiguous memory blocks into a linked list to enable the transfer of large amounts of data without memory limitations. In non-scattergather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system. Users can also link descriptor nodes circularly to achieve a multibuffered DMA. A linked list comprising three DMA descriptors.

Each descriptor contains a PCI address, a PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space, as shown.

![The diagram depicts a data flow structure involving memory, a bus, and descriptor blocks.\n\n**Blocks:**\n*   **Bottom:** A block labeled 'Local Memory (FIFO)'.\n*   **Middle:** A wide rectangular block labeled 'PCI Bus'.\n*   **Top Row (Left):** A block containing four rows of text: 'First PCI Address', 'First Dual Address', 'Transfer Size', and 'Next Descriptor'.\n*   **Top Row (Center):** A block containing four rows of text: 'PCI Address', 'Dual Address', 'Transfer Size', and 'Next Descriptor'.\n*   **Top Row (Right):** A block containing four rows of text: 'PCI Address', 'Dual Address', 'Transfer Size', and 'Next Descriptor'.\n\n**Connections:**\n*   An arrow points upward from 'Local Memory (FIFO)' to the 'PCI Bus'.\n*   An arrow points upward from the 'PCI Bus' to the central 'Top Row' block.\n*   A horizontal arrow points from the left 'Top Row' block to the central 'Top Row' block.\n*   A horizontal arrow points from the central 'Top Row' block to the right 'Top Row' block.](.pxie-9529h-50m-38205-1010-11/7e442ceb040ab586cce9a75d2c6719fda970f08aeb1a1fb41fbd85b2cc1ee825.jpg)

Figure 5: Linked list of PCI address DMA descriptors

# 5.3 Trigger Source and Trigger Modes

![The diagram illustrates a signal processing flow for trigger inputs and outputs.\n\n**Left Side Inputs:**\n*   **Analog Inputs:** Eight lines labeled `Analog CH0` through `Analog CH7` feed into a rectangular block labeled **Analog Trigger Selection**. This block outputs a line labeled **Analog Trigger**.\n*   **Digital/Trigger Inputs:** A connector symbol labeled **TRG IN** with the text '**SMB Connector**' below it connects to a line labeled **Digital Trigger Input**.\n*   **PXI Bus Inputs:** A **PXI Interface** block (with vertical arrows) connects to three horizontal lines: **PXI_STAR**, **PXIe_DSTARB**, and **PXI Trigger Bus(0:7)**.\n*   **Software Input:** A line labeled **Software Trigger** enters from the top.\n\n**Central Processing:**\n*   All the aforementioned input lines (**Software Trigger**, **Digital Trigger Input**, **Analog Trigger**, **PXI_STAR**, **PXIe_DSTARB**, and **PXI Trigger Bus(0:7)**) converge into a tall, trapezoidal block labeled **Trigger Source Mux**.\n*   The output of the **Trigger Source Mux** goes to a central rectangular block labeled **Trigger Decision**.\n\n**Right Side Outputs:**\n*   From the **Trigger Decision** block, the path splits:\n    *   One line goes upward to text labeled **To Internal FPGA Circuit**.\n    *   Another line goes to the right into a tall, trapezoidal block labeled **Trigger Output Mux**.\n*   The **Trigger Output Mux** outputs a thick arrow labeled **PXI Trigger Bus(0:7)**.\n*   This thick arrow connects to a final **PXI Interface** block on the far right (with vertical arrows).](.pxie-9529h-50m-38205-1010-11/1994485f2844be33f5bd1356aaa1cd5794d34b81a8eee415c853b3cb7643a65b.jpg)

Figure 6: Trigger architecture

The PXIe-9529H requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PXIe-9529H supports an internal software trigger, external digital trigger, PXI\_STAR trigger, PXIe\_DSTARB, PXI Trigger Bus [0.7], and SSI bus as well as the analog trigger.

# Software Trigger

The software trigger, generated by the software command, is asserted immediately following the execution of specified function calls to begin the operation.

# External Digital Trigger

An external digital trigger is generated when a TTL rising edge or a falling edge is detected at the SMB connector on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, with a minimum pulse width of 10ns.

![Pulse Width ) 10ns\nRising edge trigger\nevent](.pxie-9529h-50m-38205-1010-11/c81cab8a337206bd9062ed9739382e95f64f26fbe3f734fa4037112c14ecb281.jpg)

![Pulse Width ) 10ns\nFalling edge trigger\nevent](.pxie-9529h-50m-38205-1010-11/ee2911c1a529932fc43112762256c05e9f3461f537b8e2304a4e83e0b7454742.jpg)

Figure 7: External digital trigger

# PXI STAR Trigger

When PXI STAR is selected as the trigger source, the PXIe-9529H accepts a TTL-compatible digital signal as a trigger signal. The trigger occurs when a rising edge or falling edge is detected at PXI STAR, with trigger polarity configurable by software, with a minimum pulse width requirement of the digital trigger signal of 300ns.

# PXIe\_DSTARB Trigger

The PXIe\_DSTARB signal, a differential signal transmitted via the PXI Express Chassis backplane, distributes high-speed, high-quality trigger signals. When PXIe\_DSTARB is selected as the trigger source, the PXIe-9529H accepts a fast-switching LVDS digital signal as a trigger signal. Triggering occurs when a rising edge or falling edge is detected at PXIe\_DSTARB, with trigger polarity configurable by software, with a minimum pulse width requirement 300ns.

# PXI Trigger Bus

The PXIe-9529H utilizes PXI Trigger Bus Numbers 0 through 7 to act as a System Synchronization Interface (SSI). With the interconnected bus provided by the PXI Trigger Bus, multiple modules are easily synced. When configured as input, the PXIe-9529H serves as a slave module and can accept trigger signals from one of the buses 0 through 7. When configured as output, the PXIe-9529H serves as a master module and can output trigger signals to the PXI Trigger Bus Numbers 0 through 7.

# Analog Trigger

The PXIe-9529H analog trigger circuitry can be configured to monitor one analog input channel from which data is acquired. The selection of an analog input channel as the analog trigger channel does not influence the input channel acquisition operation. The analog trigger circuit generates an internal digital trigger signal based on the condition between the analog signal and the defined trigger level.

Analog trigger conditions are as follows:

Positive-slope trigger: The trigger event occurs when the analog input signal changes from a voltage lower than the specified trigger level to a voltage exceeding the specified trigger level.
Negative-slope trigger: The trigger event occurs when the analog input signal changes from a voltage exceeding the specified trigger level to a voltage lower than the specified trigger level.

![| Trigger Level | Analog Signal |\n| ------------- | ------------- |\n| Lower Level   | Low           |\n| Lower Level   | Medium        |\n| Lower Level   | High          |\n| Higher Level  | Low           |\n| Higher Level  | Medium        |\n| Higher Level  | High          |](.pxie-9529h-50m-38205-1010-11/f50c5e8cdf62834e563679d8460ad890d796556a804068db1bf11ad82d58f376.jpg)

Figure 8: Analog trigger conditions

The trigger signal can be chosen from among CH0, CH1, CH2, CH3, CH4, CH5, CH6, and CH7 during the use of an external analog trigger source. The trigger level can be set by software with 24-bit resolution, with characteristics as shown.

Table 3: Preferred characteristics for analog triggers

<table><tr><td>Trigger Level Setting (Hex)</td><td>Trigger Voltage (-10V to +10V Range)</td><td>Trigger Voltage (-1V to +1V Range)</td></tr><tr><td>7FFFFFF</td><td>9.99999881 V</td><td>0.999999881 V</td></tr><tr><td>7FFFFE</td><td>9.99999762 V</td><td>0.999999762 V</td></tr><tr><td>1</td><td>1.19 μV</td><td>0.119 μV</td></tr><tr><td>0</td><td>0V</td><td>OV</td></tr><tr><td>FFFFFF</td><td>-1.19 μV</td><td>-0.119 μV</td></tr><tr><td>800001</td><td>-9.99999881 V</td><td>-0.999999881 V</td></tr><tr><td>800000</td><td>-10 V</td><td>-1 V</td></tr></table>

# Trigger Export

The PXIe-9529H can export trigger signals to PXI Trigger Bus Numbers 0 through 7, utilizing them to act as the System Synchronization Interface. When configured as the output, the PXIe-9529H serves as a master module and can output trigger signals to synchronize the slave modules, with the trigger signal routed to any of the seven PXI Trigger Bus Numbers via software.

# 5.4 Trigger Mode

Two trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs, as applied to analog input and output functions.

# Post Trigger Mode

If post-trigger mode is configured, activity commences once the following trigger conditions are met:

• The analog input channel acquires a programmed number of samples at a specified sampling rate.
• The analog output channel outputs pre-defined voltage at a specified output rate.

![Based on the provided image, here is an accurate and concise description of the flowchart:\n\n**Timeline Section (Top)**\n*   A horizontal arrow pointing right is labeled **'Time'** at the far right end.\n*   Four vertical arrows point downward onto the timeline to mark sequential events:\n    1.  **'Operation start'**\n    2.  **'Trigger Event Occurs'**\n    3.  **'Acquisition start'**\n    4.  **'Acquisition stop'**\n*   A horizontal arrow pointing right connects the 'Trigger Event Occurs' point to the 'Acquisition start' point. This arrow is labeled **'Delay Time'**.\n\n**Signal Section (Middle)**\n*   Labeled **'Trigger'** on the left.\n*   A signal line remains flat until a square pulse occurs, aligning vertically with the 'Trigger Event Occurs' mark on the timeline above.\n\n**Data Section (Bottom)**\n*   Labeled **'Data'** on the left.\n*   A signal line remains flat until a long, hexagonal block appears. This block spans the duration between 'Acquisition start' and 'Acquisition stop' on the timeline above.\n*   The text inside the block reads: **'N samples'**.](.pxie-9529h-50m-38205-1010-11/457aed9ecf2127cffc130053710f0ad0e6ad1fa85750e33903860e9b9df4d634.jpg)

Figure 9: Post-trigger acquisition

# Delay Trigger Mode

If delay trigger mode is configured, the delay time from when the trigger event asserts to the beginning of the acquisition and waveform generation can be specified, as shown. The delay time is specified by a 32-bit counter value with the counter clocking based on the PCIe clock. Accordingly, the maximum delay time is the period of PCIe\_CLK X (2^32 - 1) and the minimum is the period of PCIe\_CLK (8 ns).

![Based on the provided image, here is an accurate description of the diagram:\n\n**Timeline and Events**\nA horizontal arrow pointing right is labeled **Time**. Along this axis, four vertical arrows point downward at specific intervals:\n1.  **Operation start**\n2.  **Trigger Event Occurs**\n3.  **Acquisition start**\n4.  **Acquisition stop / Begin to transfer data to system**\n\n**Connections and Timing**\n*   A horizontal arrow labeled **Delay Time** connects the vertical line of the 'Trigger Event Occurs' point to the vertical line of the 'Acquisition start' point.\n\n**Signal Tracks**\nBelow the timeline are two signal tracks:\n*   **Trigger:** A waveform line showing a square pulse that aligns vertically with the 'Trigger Event Occurs' point.\n*   **Data:** A waveform line containing a hexagonal block labeled **N samples**. This block spans the horizontal distance between the 'Acquisition start' and 'Acquisition stop' points.](.pxie-9529h-50m-38205-1010-11/7cb7ee1db38af30280d4158bda29e86306bc48ed4e45396b81e173a4b20284af.jpg)

Figure 10: Delay trigger mode acquisition

# Post-Trigger or Delay-Trigger Acquisition with Re-Trigger

Post-trigger or delay trigger acquisition with re-trigger function enables collection of data after several trigger events, as shown. When the number of triggers is defined, the PXIe-9529H acquires specific sample data each time a trigger is accepted. All sampled data is stored in onboard memory first until all trigger events have occurred, such that the time between the previous sampled data and the subsequent trigger event can be only one clock period of PCIe CLK. After the initial setup, no additional software intervention is required.

![This diagram illustrates a sequence of events over time across three horizontal tracks:\n\n1.  **Top Track (Timeline):** A horizontal arrow pointing right is labeled **'Time'**. Three downward arrows mark specific points on this line:\n    *   **'Operation start'**\n    *   **'1st Trigger Event Occurs'**\n    *   **'2nd Trigger Event Occurs'**\n\n2.  **Middle Track (Trigger):** A signal line labeled **'Trigger'** displays two rectangular pulses. The first pulse aligns vertically with the **'1st Trigger Event Occurs'** marker, and the second pulse aligns with the **'2nd Trigger Event Occurs'** marker.\n\n3.  **Bottom Track (Data):** A line labeled **'Data'** features two hexagonal blocks. Each block is aligned with a corresponding trigger pulse and contains the text **'N samples'**.](.pxie-9529h-50m-38205-1010-11/e8ad0617d08a504c3d35cd78d6875326a4448a65313489719fa7a5e4a2f33ffc.jpg)

Figure 11: Re-trigger mode acquisition

# 5.5 ADC Timing Control

# 5.5.1 Timebase

![This block diagram illustrates a clock distribution system involving the following labeled blocks and verbatim connections:\n\n**Blocks:**\n*   **on-board OSC10M**\n*   **MUX**\n*   **CLK Synthesizer**\n*   **ADC no.0/no.1**\n*   **FPGA**\n*   **PXle Hybrid Peripheral Slot (XLB)** (represented as a vertical double-headed arrow on the left)\n\n**Connections:**\n*   **OSC_10M**: Connects from **on-board OSC10M** to the **MUX**.\n*   **PXI_CLK_10M**: Connects from **PXle Hybrid Peripheral Slot (XLB)** to the **MUX**.\n*   **MUX Output**: Connects from the **MUX** to the **CLK Synthesizer**.\n*   **PXI_DSTARA_P/N**: Connects from **PXle Hybrid Peripheral Slot (XLB)** to the **CLK Synthesizer**.\n*   **ADC_CLKIN_A**: Connects from the **CLK Synthesizer** to **ADC no.0/no.1**.\n*   **ADC_CLKIN_B**: Connects from the **CLK Synthesizer** to **ADC no.0/no.1**.\n*   **FPGA_MCLK**: Connects from the **CLK Synthesizer** to the **FPGA**.\n*   **PCle_REFCLK_P/N**: Connects from **PXle Hybrid Peripheral Slot (XLB)** to the **FPGA**.](.pxie-9529h-50m-38205-1010-11/477cb4cfc5d7ee745eb399b2ba3d9fab33889c4e2ad9f951290c1eaf96f8c667.jpg)

Figure 12: Timebase architecture

An onboard timebase clock drives the sigma-delta ADC, with a frequency exceeding the sample rate and produced by a PLL chip, with output frequency programmable to superior resolution. The PXIe- 9529H accepts the external 10MHz and 100MHz clocks from the PXI Express backplane for improved synchronization between modules.

# 5.6 Synchronizing Multiple Modules

The SSI (System Synchronization Interface) provides DAQ timing synchronization between multiple cards, with a bidirectional SSI I/O providing a flexible connection between cards and allowing a single SSI master to output the signal to other slave modules. SSI signals are designed for card synchronization only, not external devices. In the PXI Express form factor, the PXI trigger bus built on the PXI Express backplane provides the necessary timing signal connections. All SSI signals are routed to the XJ4 connector, with no requirement for additional cabling. The eight interconnected lines on the PXI Express backplane, labeled PXI Trigger Bus[0:7] provide a flexible interface for syncing multiple modules.

Table 4: Configuration for synchronizing multiple modules

<table><tr><td>Module</td><td>Trigger source</td><td>Trigger out to PXI backplane</td><td>Timebase</td></tr><tr><td rowspan="4">Master</td><td rowspan="2">External Trigger</td><td>PXI Trigger Bus</td><td rowspan="4">PXI backplane 10MHz</td></tr><tr><td>PXI Star Trigger</td></tr><tr><td rowspan="2">Software Trigger</td><td>PXI Trigger Bus</td></tr><tr><td>PXI Star Trigger</td></tr><tr><td rowspan="2">Slave [1..n]</td><td>PXI Trigger Bus</td><td>N/A</td><td rowspan="2">PXI backplane 10MHz</td></tr><tr><td>PXI Star Trigger</td><td>N/A</td></tr></table>

The PXIe-9529H utilizes the PXI Trigger Bus [0:7] as a System Synchronization Interface (SSI). Flexible routing of trigger signals onto the PXI Trigger Bus enables the PXIe-9529H to simplify synchronization between multiple modules. SSI timing signals and functions are as shown, as is the SSI architecture.

Table 5: SSI timing signal definitions

<table><tr><td>SSI Timing Signal</td><td>Functionality</td></tr><tr><td>SSI_AD_TRIG</td><td>SSI master: issues internal AD_TRIGSSI slave: accepts SSI_AD_TRIG as the digital trigger signal.</td></tr></table>

![This image depicts a simple icon of a white document or piece of paper with a folded top-right corner. Faint grey horizontal lines run across the page, simulating text. A large, bold red checkmark is stamped diagonally across the left side of the document. There is no legible text present in the image.](.pxie-9529h-50m-38205-1010-11/75943cd78a2c9d1aa26b55632ef89950855fef8a40995eca975e0a85d88ef08e.jpg)
NOTE

Different signals cannot be routed onto the same trigger bus line.

The internal timing signals can be routed to the PXI trigger bus through software drivers. Physically, signal routing is accomplished in the FPGA, with cards connected through the PXI trigger bus achieving synchronization on the timing signal.

# 5.6.1 SSI\_TRIG

As output, the SSI\_TRIG signal reflects the trigger event signal in an acquisition sequence. As input, the PXIe-9529H accepts the SSI\_TRIG signal as the trigger event source. The signal is configured in the rising edgedetection mode, with minimum pulse width of 8ns.

# 6 Appendix A Calibration

This chapter introduces the calibration process to minimize analog input measurement errors.

# 6.1 Calibration Constant

The PXIe-9529H is factory-calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PXIe-9529H driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PXIe-9529H.

The onboard EEPROM provides two banks for calibration constant storage. Bank 0, the default bank, records the factory-calibrated constants, providing written protection and preventing erroneous auto-calibration. Bank 1 is a user-defined space, provided for the storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to Bank 1.

When PXIe-9529H boots, the driver accesses the calibration constants and is automatically set to hardware. In the absence of user assignment, the driver loads constants stored in bank 0. If constants from Bank 1 are to be loaded, the preferred bank can be designated as a boot bank by software. Following the re-assignment of the bank, the driver will load the desired constants on the system reboot. This setting is recorded to EEPROM and is retained until reconfiguration.

# 6.2 Auto-Calibration

Errors in measurements and outputs will vary with time and temperature, recalibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PXIe-9529H has an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the onboard EEPROM.

Before initializing auto-calibration, it is recommended to warm up the PXIe-9529H for at least 20 minutes and remove connected cables.

![The image displays a document icon featuring a white sheet of paper with faint horizontal lines, overlaid by a large red checkmark. Below the graphic, the word 'NOTE' is written in black, uppercase letters.](.pxie-9529h-50m-38205-1010-11/f105bec3ed9d0df165efee304f0504db9beb6978aaf056bf234d2b798c69abd1.jpg)

It is not necessary to manually factor delay into applications, as the PXIe-9529H driver automatically adds the compensation time.

# Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.

► Read these safety instructions carefully.
► Keep the User’s Manual for future reference.
► Read the Specifications section of this manual for detailed information on the recommended operating environment.
► The device can be operated at an ambient temperature of 50ºC.
► When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing (See “Getting Started” on page 9.):

[> Turn off power and unplug any power cords/cables.

[> Reinstall all chassis covers before restoring power.

► To avoid electrical shock and/or damage to device:

[> Keep device away from water or liquid sources.
[> Keep device away from high heat or humidity.
[> Keep device properly ventilated (do not block or cover ventilation openings).
[> Always use recommended voltage and power source settings.
[> Always install and operate device near an easily accessible electrical outlet.
[> Secure the power cord (do not place any object on/over the power cord).
[> Only install/attach and operate device on stable surfaces and/or recommended mountings.

► If the device will not be used for long periods of time, turn off and unplug from its power source.
► Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools.
► A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![The image shows a standard yellow triangular warning sign with a black border. In the center of the triangle is a large black exclamation point.](.pxie-9529h-50m-38205-1010-11/240fba2bb9f94dfbe7c3d01f1293971b4ea988b81e2e285d82f52fa4fbcc20e2.jpg)
CAUTION:

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

► The device must be serviced by authorized technicians when:

[> The power cord or plug is damaged.
[> Liquid has entered the device interior.
[> The device has been exposed to high humidity and/or moisture.
[> The device is not functioning or does not function according to the User’s Manual.
[> The device has been dropped and/or damaged and/or shows obvious signs of breakage.

► Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

► It is recommended that the device be installed only in a server room or computer room where access is:

[> Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefore, and any precautions required.

[> Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

► If PoE (Power over Ethernet) is enabled for the device, the system can ONLY be deployed indoors. Unless otherwise noted, the PoE system is NOT designed to withstand the rigors of outdoor use.

<table><tr><td>&lt;img src="images/dedf3ca9890fc9601ddbec81294eb6d1a5eb56a87c2cacce37cafa1bc12bfd07.jpg"/&gt;</td><td>BURN HAZARDTouching this surface could result in bodily injury.To reduce risk, allow the surface to cool before touching.RISQUE DE BRÛLURESNe touchez pas cette surface, cela pourrait entraîner des blessures.</td></tr></table>

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

Address: No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.pxie-9529h-50m-38205-1010-11/pxie-9529h-50m-38205-1010-11.pdf)