# PXle-9834

4CH 16-bit 80MS/s PXIe Digitizer

# User's Manual

![ADLINK\nFXIE-9854\nCHI\nCHI\nCHI\nCHI\nCHI\nCUIN\nTIC IN\nADLINK\nTECHNOLOGY INC.](.pxie-9834-50-17057-1000-10/9ada2686c99c7fe71561bf60e976d51eafe20d5197e23dca862c231420749ee1.jpg)

Manual Rev.: 1.0

Revision Date: September 12, 2019

Part No: 50-17057-1000

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>September 12, 2019</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2019 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.pxie-9834-50-17057-1000-10/248134693cadbcb646d379a20763995160411b74353535f3857f016321f3843a.jpg)

![The image displays the top-left corner of a table or grid structure. It features thick black lines forming a border on a white background. A horizontal line runs across the top edge, followed immediately by a second horizontal line just below it. On the far left, a vertical line connects the uppermost horizontal line to the one beneath it.](.pxie-9834-50-17057-1000-10/407a2b9ba2dc8ae75bb1144fbff86d15c478eafbe0019a180625d069be8b59a7.jpg)

# Battery Labels (for products with battery)

![Symbol of a trash bin crossed with no text or numbers, representing waste sorting or disposal (no text present)](.pxie-9834-50-17057-1000-10/736b9dd9d7445f03e20c569fedd77f9b61ccd9d305b57b52b4ab74e9a08204d1.jpg)

![Li-ion](.pxie-9834-50-17057-1000-10/233ba4cf91543dcb94e88cbee70d40ab08cc49a4f98e37373b4131547289be0e.jpg)

![RECYCLE\nRBRC\nLi-ion\n1.800.822.8837](.pxie-9834-50-17057-1000-10/e7b918d37b66b0493e770af4c2e6dc3a8a5598eca60aedf9c383a468ec3df673.jpg)

![廢電池請回收](.pxie-9834-50-17057-1000-10/d15b0852a4821598e11b45447de9fd6dcfddb5c7a0c2d24495ef68813dea49e9.jpg)

# California Proposition 65 Warning

![The image displays a yellow triangular warning sign with a thick black border and a black exclamation mark centered inside.](.pxie-9834-50-17057-1000-10/bc53ebc3da080be2e40f81120483da5fc227ae8c1a4c141b2bee7803df4c02eb.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4- Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a standard document icon featuring a white sheet of paper with faint horizontal lines and a folded upper-right corner. A large, bold red checkmark is superimposed diagonally across the center, angling upwards from left to right.](.pxie-9834-50-17057-1000-10/27597e0db794581c901a577440f732c1ecd19d216084ba7488db18ab557225a0.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![A yellow triangular warning sign featuring a large black exclamation point in the center.](.pxie-9834-50-17057-1000-10/db0dae7ea63850e565943e5a5085818276c318adfdd815ac9166d3a56002c2f5.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a red triangular warning sign with a white border. Centered inside the triangle is a large white exclamation point.](.pxie-9834-50-17057-1000-10/eb12d7f29393d345e466d25339edd6f43c171a3239b2b2d80998946fc0673a07.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

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# Table of Contents

# Preface .... iii

# List of Figures ix

# List of Tables.... xi

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 2

1.3.1 Analog Input 2
1.3.2 Accuracy....3
1.3.3 System Noise 3
1.3.4 Crosstalk, DC to 10MHz 3
1.3.5 Spectral Characteristics....4
1.3.6 Timebase 6
1.3.7 Triggers 7
1.3.8 Mechanical and Environmental 9
1.3.9 Power Consumption 9

1.4 Software Support 10

1.4.1 MAPS Core.... 11
1.4.2 MAPS/LV, LabVIEW Support 14
1.4.3 MAPS/C, C & C++ Support 14

1.5 Device Layout and I/O Connectors 15

# 2 Getting Started 19

2.1 Installation Environment 19
2.2 Package Contents 20
2.3 Installing the Module 21

# 3 Operations 23

3.1 Functional Block Diagram 23
3.2 Analog Input Channel 23

3.2.1 Analog Input Front-End Configuration 23
3.2.2 Input Range and Data Format 24
3.2.3 DMA Data Transfer 26

3.3 Trigger Source 27

3.3.1 Software Trigger 28
3.3.2 External Digital Trigger 28
3.3.3 Analog Trigger 29
3.3.4 PXI Trigger Bus 30
3.3.5 PXI Star 30
3.3.6 PXIe Differential Trigger 30

3.4 Trigger Modes.... 31

3.4.1 Post Trigger Mode 31
3.4.2 Delayed Trigger Mode 32
3.4.3 Pre-Trigger Mode....32
3.4.4 Middle Trigger Mode....33
3.4.5 Acquisition with Re-Triggering 34

3.5 Timebase 35

3.5.1 Internal Sampling Clock....35
3.5.2 External Sampling Clock....35
3.5.3 External Reference Clock 36

3.6 Acquisition Timing Control 37
3.7 Synchronizing Multiple Modules 39
3.7.1 Multi-module Synchronization Interfaces......43

# A Appendix: Calibration.... 45

A.1 Calibration Constant 45
A.2 Auto-Calibration 46

# Important Safety Instructions.... 49

# Getting Service 53

# List of Figures

Figure 1-1: Typical Frequency Response, 1MΩ input impedance 4
Figure 1-2: Typical Frequency Response, 50Ω input impedance. 5
Figure 1-3: ADLINK MAPS Architecture 10
Figure 1-4: ADLINK Connection Explorer (ACE) 12
Figure 1-5: ADLINK Connection Explorer Soft Front Panel ..... 13
Figure 1-6: PXIe-9834 Dimensions....15
Figure 1-7: PXIe-9834 Front Panel 16
Figure 3-1: Functional Block Diagram....23
Figure 3-2: Analog Input Architecture 23
Figure 3-3: Linked List of PCI Address DMA Descriptors ..... 27
Figure 3-4: Trigger Architecture 27
Figure 3-5: External Digital Trigger 28
Figure 3-6: Analog Trigger Conditions 29
Figure 3-7: Post-Trigger Acquisition 31
Figure 3-8: Delayed Trigger Mode Acquisition....32
Figure 3-9: Pre-Trigger Mode Acquisition 32
Figure 3-10: Middle Trigger Mode Acquisition .... 33
Figure 3-11: Re-Trigger Mode Acquisition 34
Figure 3-12: Timebase Architecture.... 35
Figure 3-13: Varying Sampling Rates via Scan Interval Counter.. 37
Figure 3-14: Non-synched Digitizer Modules....39
Figure 3-15: External Instrument Synchronization....40
Figure 3-16: Module-based Synchronization 41
Figure 3-17: PXIe Instrumentation Signals 42
Figure 3-18: Trigger Architecture 43
Figure 3-19: PXI\_CLK10 as 10MHz Reference 44
Figure A-1: Auto-Calibration Block Diagram 46
Figure A-2: Auto-Calibration Flow 47

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# List of Tables

Table 1-1: Analog Input Channel Characteristics ...... 2

Table 1-2: Accuracy....3

Table 1-3: System Noise....3

Table 1-4: Crosstalk, DC to 10MHz 3

Table 1-5: Spectral Characteristics....4

Table 1-6: Timebase Specifications....6

Table 1-7: External Sample Clock 6

Table 1-8: External Reference Clock....7

Table 1-9: Triggers....7

Table 1-10: External Digital Trigger Input 8

Table 1-11: Onboard Reference (Calibration)......8

Table 1-12: Specifications....9

Table 1-13: Power Consumption 9

Table 1-14: PXIe-9834 I/O Array Legend 17

Table 3-1: Input Range and Data Format 24

Table 3-2: Input Range FSR and -FSR Values....25

Table 3-3: Input Range Midscale Values....25

Table 3-4: Counter Parameters and Description ...... 38

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# 1 Introduction

The ADLINK PXIe-9834 PXI Express digitizer delivers high speed, high quality data acquisition, with each of four input channels supporting up to 80MS/s sampling with 16-bit resolution A/D converter. This provides simultaneous recording of signals on all channels with no inter-channel phase delay, and the extremely large onboard memory enables long recording times even at the highest sampling rates.

The PXIe-9834 features flexible input, $\pm10V$ (only for 1M $\Omega$ ), $\pm5V$ , $\pm1V$ and $\pm0.5V$ along with software selectable 50 $\Omega$ or 1M $\Omega$ input impedance. Four high resolution 16-bit A/D converters combined with low-noise, high bandwidth analog front-end enable highly accurate signal acquisition. Providing extremely large onboard memory, the PCI Express 4 lane interface supports data streaming even at the highest sampling rates. The PXIe-9834 is also auto-calibrated with an onboard reference circuit compensating the offset and gain error of acquired analog input signals.

The PXIe-9834 is, accordingly, ideal for applications such as radar signal acquisition, fiber optic detection, and many others.

# 1.1 Features

▶ Up to 80MS/s sampling
▶ 4 simultaneous analog inputs
▶ High resolution 16-bit ADC
▶ Up to 40 MHz bandwidth for analog input
▶ 1GB onboard storage
▶ Programmable input voltage of ±0.5V, ±1V, ±5V, or ±10V
▶ 10 or 20MHz onboard digital filter
▶ Support for external sampling clock (20MHz to 80MHz) or external reference clock (10MHz)
▶ Scatter-Gather DMA data transfer for high speed data streaming
- PXI/PXIe instrumentation signals supported for triggers and timebase
▶ Full auto-calibration

# 1.2 Applications

▶ Testing/monitoring for Energy Management applications, including:
▷ Partial discharge
▶ Power line/device monitoring
▶ Non-destructive testing
▶ Radar acquisition
LiDAR

# 1.3 Specifications

# 1.3.1 Analog Input

<table><tr><td>Item</td><td>Specification</td><td>Comment</td></tr><tr><td>Channels</td><td>4 single-ended</td><td></td></tr><tr><td>Connector type</td><td>SMA</td><td></td></tr><tr><td>Input coupling</td><td>DC or AC, software selectable</td><td></td></tr><tr><td>ADC resolution</td><td>16-Bit</td><td></td></tr><tr><td>Input range</td><td>±0.5 V, ±1 V, ± 5V, or ± 10V</td><td>±10V range support only for 1MΩ input impedance</td></tr><tr><td>Bandwidth (-3dB)</td><td>40MHz</td><td></td></tr><tr><td rowspan="3">Maximum input overload</td><td>7Vrms</td><td>For 50Ω: ±0.5V or ±1V or ± 5V input range</td></tr><tr><td>±10V</td><td>For 1MΩ: ±0.5V or ±1V</td></tr><tr><td>±30V</td><td>For 1MΩ: ±5V or ±10V</td></tr><tr><td>Input impedance</td><td>50Ω or 1MΩ, software selectable</td><td></td></tr><tr><td>Digital filter</td><td>10MHz or 20MHz, software selectable</td><td></td></tr></table>

Table 1-1: Analog Input Channel Characteristics

# 1.3.2 Accuracy

<table><tr><td rowspan="2">Input Range</td><td colspan="2">Offset Error</td><td rowspan="2">Gain Error</td></tr><tr><td>50Ω Input Impedance</td><td>1MΩ Input Impedance</td></tr><tr><td>±0.5V</td><td>±0.8mV</td><td>±0.8mV</td><td rowspan="4">±0.6%</td></tr><tr><td>±1V</td><td>±0.8mV</td><td>±1.2mV</td></tr><tr><td>±5V</td><td>±1.5mV</td><td>±4.0mV</td></tr><tr><td>±10V</td><td>N/A</td><td>±8mV</td></tr></table>

Table 1-2: Accuracy

# 1.3.3 System Noise

<table><tr><td>Input Range</td><td>System Noise</td></tr><tr><td>±0.5V</td><td> $0.1mV_{rms}$ </td></tr><tr><td>±1V</td><td> $0.15mV_{rms}$ </td></tr><tr><td>±5V</td><td> $1mV_{rms}$ </td></tr><tr><td>±10V</td><td> $1.5mV_{rms}$ </td></tr></table>

Table 1-3: System Noise

# 1.3.4 Crosstalk, DC to 10MHz

<table><tr><td>Input Range</td><td>Crosstalk</td><td>Comment</td></tr><tr><td>±0.5V</td><td>&lt;-80dB</td><td>1MHz sine wave, 90% of full scale range</td></tr><tr><td>±1V, ±5V, ±10V</td><td>&lt;-90dB</td><td>1MHz sine wave, 90% of full scale range</td></tr></table>

Table 1-4: Crosstalk, DC to 10MHz

# 1.3.5 Spectral Characteristics

<table><tr><td>Index</td><td>Specification</td><td>Comment</td></tr><tr><td rowspan="2">SINAD</td><td>68dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td>65dB</td><td>±10V</td></tr><tr><td>THD</td><td>-78dB</td><td>For all ranges</td></tr><tr><td>SFDR</td><td>78dB</td><td>For all ranges</td></tr><tr><td rowspan="2">SNR</td><td>69dB</td><td>±0.5V, ±1V, ±5V</td></tr><tr><td>65dB</td><td>±10V</td></tr></table>

![The image displays a digital icon featuring a white document sheet with a folded top-left corner and faint horizontal lines representing text. A large, bold red checkmark is superimposed over the left side of the document.](.pxie-9834-50-17057-1000-10/f80222d9058fdf65a64d46a64f4f716024b5cbf72c6934bbd76f8c95350c6a57.jpg)
NOTE:

Values reflect $50\Omega$ and $1M\Omega$ input impedance with digital filter off.

Table 1-5: Spectral Characteristics
![| Freq(Hz) | 10V    | 5V     | 1V     | 0.5V   |\n| -------- | ------ | ------ | ------ | ------ |\n| 10^3     | 0.0    | 0.0    | 0.0    | 0.0    |\n| 10^4     | 0.0    | 0.0    | 0.0    | 0.0    |\n| 10^5     | 0.0    | 0.0    | 0.0    | 0.0    |\n| 10^6     | -0.1   | -0.1   | -0.1   | -0.1   |\n| 10^7     | -2.5   | -2.8   | -3.0   | -3.5   |\n| 10^8     | -8.5   | -8.8   | -9.0   | -9.2   |](.pxie-9834-50-17057-1000-10/832f1e4f80744afdbf9ba37388517757c67a54910b7294816ec36e4d7d20440b.jpg)

Figure 1-1: Typical Frequency Response, 1MΩ input impedance

![| Freq(Hz) | 10V    | 5V     | 1V     | 0.5V   |\n| -------- | ------ | ------ | ------ | ------ |\n| 10^3     | -      | -      | -      | -      |\n| 10^4     | -      | -      | -      | -      |\n| 10^5     | -      | -      | -      | -      |\n| 10^6     | -      | -      | -      | -      |\n| 10^7     | -2.5   | -2.8   | -3.0   | -3.2   |\n| 10^8     | -4.0   | -4.5   | -5.0   | -5.5   |](.pxie-9834-50-17057-1000-10/c47392f2065861de34fe8a967db2d626b0660e1b3285955d3e38e5e9385760a4.jpg)

Figure 1-2: Typical Frequency Response, 50Ω input impedance

# 1.3.6 Timebase

<table><tr><td>Sample Clock</td><td>Detail</td><td>Comment</td></tr><tr><td rowspan="3">Timebase options</td><td>Internal: Onboard oscillator</td><td></td></tr><tr><td>External: CLK IN (front panel SMA connector)</td><td></td></tr><tr><td>External reference clock: ► CLK IN (front panel SMA connector) ► PXI_10M (PXle backplane 10MHz reference clock)</td><td>The reference clock supplies an onboard PLL circuit and generates 80MHz for ADC.</td></tr><tr><td rowspan="3">Sampling clock frequency</td><td>Internal 80MS/s maximum, ranges from 1.22KS/s to 80MS/s</td><td>1.22kS/s to 80MS/s</td></tr><tr><td>External sample clock: 20MHz to 80MHz (through CLK IN)</td><td></td></tr><tr><td>External reference clock: 10MHz</td><td></td></tr><tr><td>Internal onboard oscillator accuracy</td><td>&lt; ± 25ppm</td><td></td></tr></table>

Table 1-6: Timebase Specifications

<table><tr><td>External Sample Clock</td><td>Specification</td></tr><tr><td>Clock input range</td><td> $0.45V_{pp}$  to  $5V_{pp}$ </td></tr><tr><td>Clock input coupling</td><td>AC</td></tr><tr><td>Clock input impedance</td><td>50Ω</td></tr><tr><td>Duty cycle tolerance</td><td>45% to 55%</td></tr></table>

Table 1-7: External Sample Clock

<table><tr><td>External Reference Clock</td><td>Specification</td></tr><tr><td>Clock input range</td><td> $0.45V_{pp}$  to  $5V_{pp}$ </td></tr><tr><td>Clock input coupling</td><td>AC</td></tr><tr><td>Clock input impedance</td><td> $50\Omega$ </td></tr><tr><td>Duty cycle tolerance</td><td>45% to 55%</td></tr><tr><td>Reference clock frequency range</td><td> $10MHz \pm 2KHz$ </td></tr></table>

Table 1-8: External Reference Clock

# 1.3.7 Triggers

<table><tr><td colspan="2">Trigger Source &amp; Mode</td></tr><tr><td rowspan="2">Trigger source</td><td>Internal: software trigger</td></tr><tr><td>External:► External digital trigger from TRG IN (front panel)► Analog trigger from any of analog input channels► PXI Trigger Bus[0..7]► PXI STAR Trigger► PXIe_DSTARB</td></tr><tr><td>Trigger modes</td><td>► Post-trigger► Delay trigger► Pre-trigger► Middle trigger► Re-trigger for post-trigger and delay trigger modes</td></tr></table>

Table 1-9: Triggers

<table><tr><td colspan="2">External Digital Trigger Input</td></tr><tr><td>Sources</td><td>TRG IN, front panel SMA connector</td></tr><tr><td>Compatibility</td><td>3.3 V TTL, 5 V tolerant</td></tr><tr><td>Input high threshold (VIH)</td><td>2.0 V</td></tr><tr><td>Input low threshold (VIL)</td><td>0.8 V</td></tr><tr><td>Maximum input overload</td><td>-0.5 V to +5.5 V</td></tr><tr><td>Trigger polarity</td><td>Rising or falling, software selectable</td></tr><tr><td>Trigger pulse width</td><td>20 ns minimum</td></tr></table>

Table 1-10: External Digital Trigger Input

<table><tr><td colspan="2">Onboard Reference (Calibration)</td></tr><tr><td>Calibration</td><td>Specification</td></tr><tr><td>Onboard reference</td><td>+1.8V, +0.9V, +0.45V</td></tr><tr><td>Temperature coefficient</td><td>5.0 ppm/°C</td></tr><tr><td>Warm-up time</td><td>15 minutes (recommended)</td></tr></table>

Table 1-11: Onboard Reference (Calibration)

# 1.3.8 Mechanical and Environmental

<table><tr><td>Item</td><td>Specification</td><td>Comment</td></tr><tr><td>Dimensions</td><td>165mm (W) x 100mm (H) (PCB)</td><td>3U, one-slot, PXI Express module</td></tr><tr><td>Bus Interface</td><td>PCI Express x4 Gen1</td><td></td></tr><tr><td>Operating Conditions</td><td>Temperature: 0°C to 50°CRelative humidity: 5% to 95%, non-condensing</td><td></td></tr><tr><td>Storage Conditions</td><td>Temperature: -20°C to 80°CRelative humidity: 5% to 95%, non-condensing</td><td></td></tr><tr><td>Compliance &amp; Certification</td><td colspan="2">► EN 55032: 2015 / AC: 2016, Class B► EN 55024 (2010 + A1: 2015): Immunity► EN61326-1/2: Class B► FCC 47 CFR Part 15B: Class B► ICES-003 Issue 6-2016: Class B► ANSI C63.4-2014: Class B</td></tr></table>

Table 1-12: Specifications

# 1.3.9 Power Consumption

<table><tr><td>Power Rail</td><td>Standby</td><td>Maximum</td></tr><tr><td>+3.3V</td><td>18 mA</td><td>70 mA</td></tr><tr><td>+12V</td><td>450 mA</td><td>753 mA</td></tr><tr><td>Total Power</td><td>5.46W</td><td>9.28W</td></tr></table>

Table 1-13: Power Consumption

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW. All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license. The ADLINK Measurement, Automation & Platform Service (MAPS) is a software service package designed for data acquisition, automation and PXI platform. By leveraging the sophisticated architecture in low-level kernel management and user friendly API, users can easily manage devices under a Windows environment and focus on developing applications.

![This block diagram illustrates a layered software architecture for a PXI platform, organized into three main sections:\n\n**Top Section (Application & Management Layer)**\nThis section is divided into a left-hand management column and a right-hand application stack.\n\n*   **Left Column (Red Background):** Labeled 'MAPS Core Device Management,' containing four stacked blocks:\n    *   'Device Manager (ACE)'\n    *   'PXI Platform Resource Mgmt. Utility'\n    *   'PXI Platform ChassisWatch Utility'\n    *   'DAQ/IO Module Function Test Utility'\n*   **Right Columns (White Background):** Three vertical columns representing different programming environments, each with a top block for applications and a colored bottom block for the SDK:\n    *   **Column 1 (Orange):** Top block reads 'User APPs in C/C++'. Bottom block reads 'MAPS/C' followed by 'C/C++ SDK for DAQ/IO module'.\n    *   **Column 2 (Green):** Top block reads 'User APPs in LabVIEW'. Bottom block reads 'MAPS/LV' followed by 'LabVIEW SDK for DAQ/IO module'.\n    *   **Column 3 (Purple):** Top block reads 'User APPs in C#'. Bottom block reads 'MAPS/C#' followed by 'C# SDK for DAQ/IO module' and 'Coming soon'.\n\n**Middle Section (Runtime Layer)**\nA wide red horizontal bar labeled 'MAPS Core -Device Runtime'. To the right of this title, text lists:\n*   'PXI Platform Service'\n*   'DAQ/IO Module Device Driver'\n*   'DAQ/IO Module Runtime Library'\n\n**Bottom Section (Hardware Layer)**\nA blue horizontal strip displaying five hardware images with labels underneath:\n*   'Digitizers'\n*   'DAQ'\n*   'Edge Platform'\n*   'PXIe Controllers'\n*   'PXIe/PXI Chassis'](.pxie-9834-50-17057-1000-10/8e2af853a38164453e8fd67b340e028500a2350ed7a40e0d179991a36b9cd735.jpg)

Figure 1-3: ADLINK Measurement, Automation & Platform Service (MAPS) Architecture

# 1.4.1 MAPS Core

ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed in a user-provided PC, the operating system can identify ADLINK's devices correctly and assign necessary resources for low-level access, such as IO read/write or direct memory access. MAPS/Core is necessary for all ADLINK DAQ modules. To ensure the user has the latest software, go to the ADLINK product webpage or contact ADLINK technical service.

MAPS Core also comes with a system management portal called ADLINK Connection Explorer (ACE). Through ACE, users can discover and manage ADLINK DAQ modules. For example, the user can reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment.

![ADLINK Connection Explorer\nFile View Config Help\nPXI\nPXES-2301 'Chassis1'\n1: PXIe-3987 'Chassis\n4: PXIe-9834 Device '\nPCI\nUSB\nSettings\nAlias Name PXIE-9834-4\nVendor ADLINK Technology Inc.\nModel PXIe-9834 Device\nSlotNumber 4\nPCI Bus 14\nPCI Device 0\nPCI Function 0\nDMA Buffer\nAI 512000 KB\nAO 0 KB\nDI 0 KB\nDO 0 KB\nVendor Information\nSupport Link Test Utility Company Info.\nADLINK\nUtility\nSoftFrontPanel Launch](.pxie-9834-50-17057-1000-10/5e2b001116fa697e40f424c3e984b35cabd5dee999002304776680831080b55f.jpg)

Figure 1-4: ADLINK Connection Explorer (ACE)

ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. By clicking the Launch button in the lowest "Utility" block, this soft-front panel allows users to control digitizers through the UI and display the acquired waveform/data on the screen.

![ADLINK Soft Front Panel\nFile Utilities Call Log Help\nCH0: (5.0713ms/405705Sa) 0.960388V\n0.00\nStart\nAmplitude Zoom=0.5V/Div\nTime: 1.221μs/Div\nData Count: 80M Sa/s\n800000\nDeviceID=None Disconnected Acquisition Done](.pxie-9834-50-17057-1000-10/6d85f8bbc1fd01414e87a9b8eb1567cafcae34033c67cbf9b35c463c7198e579.jpg)

Figure 1-5: The ADLINK Connection Explorer (ACE) Soft Front Panel

# 1.4.2 MAPS/LV, LabVIEW Support

For customers who develop their own programs in LabVIEW, please install the MAPS/LV software package. The MAPS/LV, also called DAQ-LabVIEW Plus, includes the software library and sample program for LabVIEW. Download and install the latest MAPS/LV software from the following website and refer to the MAPS/LV manual: https://www.adlinktech.com/Products/Data\_Acquisition/DAQSoftware\_Utility/MAPS\_LV?Lang=en

# 1.4.3 MAPS/C, C & C++ Support

For customers who develop their own programs in C or C++ environments, install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, device API library and versatile sample programs for understanding how to manipulate the device correctly. Find the latest MAPS/C on the ADLINK website.

# 1.5 Device Layout and I/O Connectors

All dimensions are in mm.

![ADLINK\nTECHNOLOGY INC.\n165.04\n(200.73)\n99.85](.pxie-9834-50-17057-1000-10/814a241b542a098eec05a93bdf1d924c107f136c40baf01cfe066718a8057ce6.jpg)

Figure 1-6: PXle-9834 Dimensions

The PXIe-9834 I/O array is labeled to indicate connectivity, as shown. All I/O connectors are SMA.

![ADLINK\nTECHNOLOGY INC.\nPXIe-9834\nCH0\nCH1\nCH2\nCH3\nCLK IN\nTRG IN\nCH1\nCH2\nCH3\nCLK IN\nTRG IN](.pxie-9834-50-17057-1000-10/c1e9f9264a1a212de571e1b6183dbbe49d9d38efed8bd6f8117bb073d1980d1a.jpg)

Figure 1-7: PXle-9834 Front Panel

<table><tr><td>Input</td><td>Faceplate Label</td><td>Comment</td></tr><tr><td>Analog</td><td>CH0</td><td rowspan="4">Analog Input Channel</td></tr><tr><td>Analog</td><td>CH1</td></tr><tr><td>Analog</td><td>CH2</td></tr><tr><td>Analog</td><td>CH3</td></tr><tr><td>External sampling clock and reference clock</td><td>CLK IN</td><td>Input for external sampling clock or reference clock to the digitizer</td></tr><tr><td>External Digital Trigger</td><td>TRG IN</td><td>External digital trigger input, receiving trigger signal from external instrument, thus initiating acquisition</td></tr></table>

Table 1-14: PXIe-9834 I/O Array Legend

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# 2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PXIe-9834.

![A white document icon with faint gray horizontal lines and a folded top-right corner, overlaid with a large red checkmark.](.pxie-9834-50-17057-1000-10/b14c0fc4ea302dfeadb81eff1469cd22a98219dc389227fa1e6221c87296a889.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools:

▶ Phillips (cross-head) screwdriver
▶ Flat-head screwdriver
Anti-static wrist strap
▶ Antistatic mat

The ADLINK PXIe-9834 is electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle is a black exclamation point. Below the triangle, the word 'CAUTION' is printed in black, capital letters.](.pxie-9834-50-17057-1000-10/7a9503594ef0b3dd5048e5a4e2d1c1159c26a9f1368f9a2829dc2bb6663760e5.jpg)

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

# 2.2 Package Contents

▶ PXIe-9834 digitizer
▶ PXIe-9834 Quick Start Guide

If any of these items are missing or damaged, contact the dealer.

![The image features a red triangular warning sign containing a white exclamation point in the center. Below the triangle, the text 'WARNING:' is displayed in black, capital letters.](.pxie-9834-50-17057-1000-10/207002b351d6be0f77ef23117aeb93111a49840239b17f93dddee83bc31739cf.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.3 Installing the Module

![The image displays a white document icon featuring a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark.](.pxie-9834-50-17057-1000-10/42ba545ac26ff32a12122553bc0b9a3d604383e4b1df4057f09c6681e5441871.jpg)
NOTE:

The power cable provides grounding to prevent hazardous ESD (electrostatic discharge).

![The image displays a red triangular warning sign featuring a white exclamation point in the center. Below the triangle, the word 'WARNING' appears in black, uppercase letters.](.pxie-9834-50-17057-1000-10/780a38daeedbed5e52dfaf1f8db839710f70f0e9bdbd829d8c1c614f133d4131.jpg)

Do not to perform "hot swapping", replacement, disconnecting or connecting of any components (including cards and cabling) on chassis while the system is powered up. By not observing this Warning, system damage and/or data loss, and physical injury (due to possible shock hazard) may result.

1. Turn off the PXle system/chassis and ensure the power cable from the power source is connected.
2. Align the module's edge with the module guide in the PXIe chassis.
3. Slide the module into the chassis until resistance is felt from the PXIe connector.
4. Push the ejector latch upwards and fully insert the module into the chassis.
5. Once the module is fully seated, a "click" can be heard from the ejector latch.
6. Tighten the screw on the faceplate.
7. Power up the PXIe system/chassis.

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# 3 Operations

This chapter contains information regarding analog input, triggering and timing for the PXIe-9834.

# 3.1 Functional Block Diagram

![Based on the provided image, here is the accurate description of the flowchart blocks and connections:\n\n**Labeled Blocks:**\n*   **Inputs:** CH0, CH1, CH2, CH3, CLK IN, TRG IN\n*   **Processing/Control:** Analog Front End, ADC (appears 4 times), FPGA, Calibration, System Clock, Trigger Buffer\n*   **Memory/Interfaces:** DDR3, XJ4, XJ3\n*   **System:** System Power\n*   **Labels:** PXI Instrumentation Signals, PCI Express\n\n**Connections:**\n*   **Inputs to Analog Front End:** The inputs labeled **CH0**, **CH1**, **CH2**, and **CH3** pass through yellow hexagonal connectors and enter the **Analog Front End** block.\n*   **Clock and Trigger Paths:**\n    *   **CLK IN** passes through a yellow connector into the **System Clock** block.\n    *   **TRG IN** passes through a yellow connector into the **Trigger Buffer** block.\n*   **Data Acquisition Path:**\n    *   The **Analog Front End** outputs to four yellow blocks labeled **ADC**.\n    *   The **System Clock** sends red arrows to the **ADC** blocks and the **FPGA**.\n    *   The **Trigger Buffer** sends a blue arrow to the **FPGA**.\n    *   The four **ADC** blocks send blue arrows into the **FPGA**.\n*   **Calibration Loop:**\n    *   The **FPGA** sends a green arrow to the **Calibration** block.\n    *   The **Calibration** block sends a green arrow back to the **Analog Front End**.\n*   **External Interfaces:**\n    *   The **FPGA** connects via blue arrows to **DDR3**, **XJ4**, and **XJ3**.\n    *   The connection to **XJ4** is labeled **PXI Instrumentation Signals**.\n    *   The connection to **XJ3** is labeled **PCI Express**.\n*   **System Power:** The **System Power** block is shown on the right but has no connecting lines.](.pxie-9834-50-17057-1000-10/37031c4417c70a3f66fe573aa4e5bd9893b8c22f740c004142cddecec72cf494.jpg)

Figure 3-1: Functional Block Diagram

# 3.2 Analog Input Channel

# 3.2.1 Analog Input Front-End Configuration

![Based on the provided diagram, here is the accurate description of the blocks and connections:\n\n**Labeled Blocks:**\n*   **Analog Channel** (connected to ground)\n*   **Calibration Sources**\n*   **AC / DC**\n*   **Hi-Z / 50 Ω**\n*   **Attenuation (+1 or +10)**\n*   **Multiplier (x1 or x2)**\n*   **OPA**\n*   **FDA**\n*   **L.P.F**\n*   **Quad ADC 16 Bits** (containing an inner block labeled **ADC**)\n*   **FPGA**\n\n**Connections:**\n1.  The **Analog Channel** connects to the **Calibration Sources**.\n2.  The signal path flows from the **Analog Channel** through a series of switch sections labeled **AC / DC**, **Hi-Z / 50 Ω**, **Attenuation (+1 or +10)**, and **Multiplier (x1 or x2)**.\n3.  The signal then enters the **OPA** and passes to the **FDA**.\n4.  The signal passes through the **L.P.F**.\n5.  The signal enters the **Quad ADC 16 Bits** block.\n6.  Finally, the signal exits to the **FPGA**.](.pxie-9834-50-17057-1000-10/a9316f452277550fe72b51721572a3342c7e45fbb01455fdc4aea00838353396.jpg)

Figure 3-2: Analog Input Architecture

The PXIe-9834's 50Ω or 1MΩ input impedance circuit, along with AC/DC coupling, makes it easy to acquire a wide variety of signals. Sophisticated attenuation circuit design offers several input ranges with high noise-to-signal ratio and high spurious-free dynamic range in AC performance. Analog bandwidth up to 40MHz and two digital filters provide more options to filter out unwanted high frequency signals and lower incoming noise. The overall analog path design provides flexible configuration, acquiring high speed signals and restore them in digital data, with all designs applied to four analog input channels independently.

For auto-calibration, an elaborate onboard reference circuit provides stable and low drift voltage, of particular benefit whenever auto-calibration is executed in response to environmental temperature change. For more details about auto-calibration, please see “Calibration” on page 45.

# 3.2.2 Input Range and Data Format

Data format of the PXle-9834 is 2's complement.

<table><tr><td>D15</td><td>D14</td><td>D13</td><td>D12</td><td>...</td><td>D3</td><td>D2</td><td>D1</td><td>D0</td></tr><tr><td colspan="9">D15 to D0 bits represent the 16-bit data from ADC (2&#x27;s complement)</td></tr></table>

Table 3-1: Input Range and Data Format

The following table shows the represented digital code when input voltage is at negative full scale and positive full scale. Since the data format for the PXIe-9834 is 2's complement, the most significant bit represents the sign of input voltage.

<table><tr><td></td><td>Input Range</td><td>Least Significant Bit</td><td>FSR-1LSB</td><td>-FSR</td></tr><tr><td rowspan="4">Bipolar Analog Input</td><td>± 10.0V</td><td>0.305 mV</td><td>9.999694824</td><td>-10V</td></tr><tr><td>± 5.0V</td><td>0.153 mV</td><td>4.999847412</td><td>-5V</td></tr><tr><td>± 1.0V</td><td>0.031 mV</td><td>0.999969482</td><td>-1V</td></tr><tr><td>± 0.5V</td><td>0.015 mV</td><td>0.499984741</td><td>-0.5V</td></tr><tr><td>Digital Code</td><td>N/A</td><td>N/A</td><td>7FFF</td><td>8000</td></tr></table>

Table 3-2: Input Range FSR and -FSR Values

The following table shows the digital code when input voltage is roughly midscale, approximately 0 V.

<table><tr><td></td><td>Midscale +1LSB</td><td>Midscale</td><td>Midscale -1LSB</td></tr><tr><td rowspan="4">Bipolar Analog Input</td><td>0.305 mV</td><td>0 V</td><td>-0.305 mV</td></tr><tr><td>0.153 mV</td><td>0 V</td><td>-0.153 mV</td></tr><tr><td>0.031 mV</td><td>0 V</td><td>-0.031 mV</td></tr><tr><td>0.015 mV</td><td>0 V</td><td>-0.015 mV</td></tr><tr><td>Digital Code</td><td>0001</td><td>0000</td><td>FFFF</td></tr></table>

Table 3-3: Input Range Midscale Values

In the PXIe chassis, a system timing slot distributes trigger signals through PXI\_STAR and PXIe differential star triggers. The 8-bit parallel PXI Trigger bus provides additional channels to transmit and receive triggers between peripheral slots. The PXIe chassis further provides 10MHz (PXI\_CLK10) clock options distributed to each peripheral slot with minimal clock skew.

# 3.2.3 DMA Data Transfer

The PXIe-9834, a PXIe Gen 1 X 4 device, is equipped with four 80MS/s high sampling rate ADCs, generating a 640 MByte/second rate.

To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list so users can transfer large amounts of data without being limited by memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi-buffered DMA. Figure 3-3 illustrates a linked list comprising three DMA descriptors. Each descriptor contains a PCI address, PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space, but the subsequent descriptor address must be less than 4GB.

![The diagram depicts a data flow structure with the following labeled blocks and connections:\n\n**Bottom Section**\n*   **Block:** Local Memory (FIFO)\n*   **Connection:** An arrow points upward from 'Local Memory (FIFO)' to the 'PCI Express Bus' block.\n\n**Middle Section**\n*   **Block:** PCI Express Bus\n*   **Connection:** An arrow points upward from 'PCI Express Bus' to the central block in the top row.\n\n**Top Section (Flowing Left to Right)**\n*   **Block (Left):**\n    *   First PCI Address\n    *   First Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n*   **Connection:** An arrow points from the left block to the central block.\n*   **Block (Center):**\n    *   PCI Address\n    *   Dual Address\n    *   Transfer Size\n    *   Next Descriptor\n*   **Connection:** An arrow points from the central block to the right block.\n*   **Block (Right):**\n    *   PCI Address\n    *   Dual Address\n    *   Transfer Size\n    *   Next Descriptor](.pxie-9834-50-17057-1000-10/bc6a81b4a733300c5eb2b5a8803ccf3be995fce02d211a992e0eb5bb96ca9072.jpg)

Figure 3-3: Linked List of PCI Address DMA Descriptors

# 3.3 Trigger Source

This section details PXIe-9834's triggering operations.

![The diagram shows a signal flow starting with six input lines entering a block labeled **MUX** on the left:\n*   **Software Trigger**\n*   **External Digital Trigger**\n*   **Analog Trigger**\n*   **PXI Trigger Bus**\n*   **PXI_STAR**\n*   **PXIe_DSTARB**\n\nThe output of the **MUX** block connects to a central block labeled **Trigger Decision**. From this block, a single line splits into two outputs on the right:\n*   One output points to the right and is labeled **To internal FPGA**.\n*   The second output branches downward and points to the right, labeled **PXI Trigger Bus**.](.pxie-9834-50-17057-1000-10/98be14a97b0e5ba700a2cea4a0a5ed23784599d63c738b04672dcda632bf4f75.jpg)

Figure 3-4: Trigger Architecture

The PXIe-9834 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger sources. The PXIe-9834 supports internal software trigger, external digital trigger, analog trigger from AI CH0 to CH3, PXI Trigger Bus [0..7],

PXI Star and PXIe differential star (PXIe\_DSTARB). The trigger decision sends a trigger signal to internal FPGA for acquisition operation, as well as one of the PXI Trigger Bus bit for multi-module synchronization operations.

# 3.3.1 Software Trigger

The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation.

# 3.3.2 External Digital Trigger

An external digital trigger is generated when a TTL signal rising edge or falling edge is detected at the SMA connector TRG IN on the front panel. As shown, trigger polarity can be selected by software. Note that the signal level of the external digital trigger signal should be TTL compatible, and the minimum pulse width 20 ns.

![The image displays two diagrams side-by-side illustrating pulse timing and trigger events.\n\nAt the top of both diagrams is the text **'Pulse Width ) 20ns'** accompanied by a horizontal dimension line indicating the width of the square pulse below.\n\n*   **Left Diagram:** Shows a square pulse with an arrow pointing upward on the leading vertical edge. Below the pulse is the text **'Rising Edge Trigger Event'**.\n*   **Right Diagram:** Shows a square pulse with an arrow pointing downward on the trailing vertical edge. Below the pulse is the text **'Falling Edge Trigger Event'**.](.pxie-9834-50-17057-1000-10/211d60472395708d4ad1ca3551482eba0afd42c4c33597b5ce9b10cf6b261492.jpg)
Figure 3-5: External Digital Trigger

# 3.3.3 Analog Trigger

An analog trigger is generated when one of AI input signal CH0 to CH3 meets the trigger condition. The trigger conditions for analog triggers as shown in Figure 3-6.

# Rising Edge Trigger

This trigger event occurs when the analog input signal changes from a voltage lower than the specified trigger level to one higher than the specified trigger level.

# Falling Edge Trigger

This trigger event occurs when the analog input signal changes from a voltage higher than the specified trigger level to one lower than the specified trigger level.

![| Trigger Level | Analog Signal |\n| ------------- | ------------- |\n| Low           | Low           |\n| Rising Edge Trigger | Rising Edge Trigger |\n| Falling Edge Trigger | Falling Edge Trigger |](.pxie-9834-50-17057-1000-10/05da3301a221518236c4049ea27669bcba20b8d421bd79545069c7a5d5ca29c9.jpg)

Figure 3-6: Analog Trigger Conditions

# 3.3.4 PXI Trigger Bus

The PXIe-9834 utilizes PXI Trigger Bus[0..7] as multi-module synchronization interface. The interconnected bus provided by PXI Trigger Bus supports easy synchronization of multiple modules.

When configured as input, the PXIe-9834 serves as a slave module and will wait to commence signal acquisition until receiving a trigger from the PXI Trigger Bus. When configured as output, the PXIe-9834 serves as a master module and can output trigger to one of the PXI Trigger Bus. Each signal can be routed from one of the PXI Trigger Bus[0..7] by software programming.

# 3.3.5 PXI Star

When PXI STAR is selected as trigger source, the PXIe-9834 can accept a TTL-compatible digital signal as a trigger signal. The trigger occurs when a rising edge or falling edge is detected at PXI STAR. This utility can configure the trigger polarity. The minimum pulse width requirement of this digital trigger signal is 20ns.

# 3.3.6 PXIe Differential Trigger

PXle-9834 also features a trigger source from PXle differential trigger pin PXle\_DSTARB. The PXle\_DSTARB is a differential signal distributed from the PXle system timing slot, with timing skew between any peripheral slots less than 150ps. This low slot-to-slot skew makes it ideal for transferring synchronization triggers. The trigger occurs when a rising edge or falling edge is detected at PXle\_DSTARB. Software can configure trigger polarity. Minimum pulse width requirement of this digital trigger signal is 20ns.

# 3.4 Trigger Modes

Trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs. The following trigger mode descriptions are applied to analog input function.

# 3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown. When the operation starts, PXIe-9834 waits for a trigger event. Once the trigger signal is received, acquisition begins. Data is generated from ADC and transferred to system memory continuously. The acquisition stops once the total data amount reaches a predefined value.

![This image is a timing diagram illustrating the relationship between time, a trigger signal, and data acquisition. It is organized into three main sections:\n\n**Timeline and Events (Top):**\n*   A horizontal line with an arrow pointing to the right serves as the time axis, labeled **'Time'** at the far right.\n*   Three downward-pointing arrows indicate specific moments on this timeline:\n    *   The first arrow is labeled **'Operation Start'**.\n    *   The second arrow is labeled with stacked text: **'Trigger Event Occurs'** and **'Acquisition Start'**.\n    *   The third arrow is labeled **'Acquisition Stop'**.\n\n**Trigger Signal (Middle):**\n*   The row is labeled **'Trigger'** on the left.\n*   It displays a signal line that remains low until a square pulse occurs shortly after the 'Trigger Event Occurs' mark.\n\n**Data Acquisition (Bottom):**\n*   The row is labeled **'Data'** on the left.\n*   It shows a signal line where a specific segment is bracketed. Inside this bracket, the text **'N Samples'** is written.\n*   The data collection ('N Samples') begins at the rising edge of the Trigger pulse and ends at the 'Acquisition Stop' mark on the timeline.](.pxie-9834-50-17057-1000-10/622220b2c1b3c4b67eb80031225af141bdccf7d9db54b3b922f3e18c198bbd8d.jpg)

Figure 3-7: Post-Trigger Acquisition

# 3.4.2 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown. When the PXIe-9834 receives a trigger event, a time delay is implemented before commencing acquisition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of TIMEBASE X ( $2^{16}$ ), and the minimum is the timebase period.

![This diagram illustrates a timing sequence involving a trigger and data acquisition.\n\n**Labeled Blocks and Elements:**\n*   **Timeline:** A horizontal arrow pointing right is labeled 'Time'.\n*   **Timeline Markers:** Four vertical arrows point down to the timeline, labeled from left to right: 'Operation Start', 'Trigger Event Occurs', 'Acquisition Start', and 'Acquisition Stop'.\n*   **Delay Interval:** A horizontal line with arrows at both ends connects 'Trigger Event Occurs' and 'Acquisition Start' and is labeled 'Delay Time'.\n*   **Trigger Signal:** A signal line on the left is labeled 'Trigger' and shows a square pulse aligned with 'Trigger Event Occurs'.\n*   **Data Signal:** A signal line on the left is labeled 'Data'. It features a segment containing a hexagonal box labeled 'N Samples'.\n\n**Connections and Alignment:**\n*   The 'Trigger' pulse aligns vertically with the 'Trigger Event Occurs' marker on the timeline.\n*   The 'Data' segment (containing 'N Samples') aligns vertically with the time period between 'Acquisition Start' and 'Acquisition Stop' on the timeline.](.pxie-9834-50-17057-1000-10/19973db72083f679ef717ce5200d86b50a773ed571859475b4769d075b5fd9bb.jpg)

Figure 3-8: Delayed Trigger Mode Acquisition

# 3.4.3 Pre-Trigger Mode

Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system stores only data preceding the trigger event by a specified amount, as follows.

![**Blocks and Labels:**\n*   **Timeline:** A horizontal arrow pointing right labeled 'Time'.\n*   **Top Annotations:**\n    *   'Operation start Acquisition start'\n    *   'Trigger signals occuring before the specified amount of data has been acquired are ignored' (Note: 'occuring' contains a typo).\n    *   'Trigger Event Occurs Acquisition stop Data transfer to system begins'\n*   **Middle Waveform:** Labeled 'Trigger'.\n*   **Bottom Waveform:** Labeled 'Data'.\n*   **Data Sections:**\n    *   A hatched (striped) section on the left.\n    *   A white rectangular section on the right labeled 'N samples'.\n*   **Bottom Annotation:** 'X samples have been acquired before trigger occurs, where X(N'\n\n**Connections:**\n*   **Timeline:** The 'Time' arrow serves as the primary axis.\n*   **Start:** The text 'Operation start Acquisition start' has an arrow pointing to the beginning of the 'Time' arrow and the start of the 'Data' waveform.\n*   **Ignored Trigger:** The text 'Trigger signals occuring...' has an arrow pointing to a dotted vertical line on the 'Time' arrow. This aligns with the first rectangular pulse on the 'Trigger' waveform.\n*   **Valid Trigger:** The text 'Trigger Event Occurs...' has an arrow pointing to the second rectangular pulse on the 'Trigger' waveform.\n*   **Data Acquisition:**\n    *   The 'Data' waveform is a continuous bar. The left portion is hatched, and the right portion is labeled 'N samples'.\n    *   A bracket under the hatched section connects to the text 'X samples have been acquired before trigger occurs, where X(N'.\n    *   The hatched section of the 'Data' waveform ends at the exact vertical alignment of the second 'Trigger' pulse (the 'Trigger Event').\n    *   The 'N samples' section begins immediately after the second 'Trigger' pulse.](.pxie-9834-50-17057-1000-10/f35d8a4ae391cf45f3fbd9b409a97c90bbac75e0e8a7d76b1749d208e011765c.jpg)

Figure 3-9: Pre-Trigger Mode Acquisition

# 3.4.4 Middle Trigger Mode

Collects data before and after the trigger event, with the amount to be collected set individually (M and N samples), as follows

![Based on the provided image, here is a concise description of the timing diagram:\n\n**Overview**\nThe diagram illustrates a timeline with three synchronized tracks: a main time axis, a trigger signal, and a data acquisition sequence.\n\n**Labeled Blocks and Connections**\n\n1.  **Time Axis (Top Row)**\n    *   A horizontal line with an arrowhead pointing right is labeled **'Time'**.\n    *   An arrow labeled **'Operation start Acquisition start'** points to the beginning of the timeline.\n    *   An arrow labeled **'Trigger event occurs'** points to a specific point on the timeline.\n    *   An arrow labeled **'Acquisition stop Data transfer to system begins'** points to a point further along the timeline.\n\n2.  **Trigger Signal (Middle Row)**\n    *   A horizontal line labeled **'Trigger'** runs below the time axis.\n    *   It shows a brief positive pulse (square wave) that aligns vertically exactly with the **'Trigger event occurs'** arrow.\n\n3.  **Data Signal (Bottom Row)**\n    *   A horizontal line labeled **'Data'** runs below the trigger signal. It is divided into three distinct rectangular segments:\n        *   **Hatched Block:** The leftmost segment is a box filled with diagonal stripes. It starts at the beginning of the timeline (aligned with 'Operation start') and ends exactly where the **'Trigger event occurs'** arrow points.\n        *   **M samples:** The middle segment is a box labeled **'M samples'**. It begins at the 'Trigger event occurs' point.\n        *   **N samples:** The rightmost segment is a box labeled **'N samples'**. It follows the 'M samples' block and ends exactly where the **'Acquisition stop Data transfer to system begins'** arrow points.](.pxie-9834-50-17057-1000-10/ada4ab8edd31d1da7379a3cff4b6271212abb1240694d6722ef15e3b8a59baf5.jpg)

Figure 3-10: Middle Trigger Mode Acquisition

# 3.4.5 Acquisition with Re-Triggering

A digitizer acquires a trace of N samples/channel for a single acquisition. Re-Trigger mode can also be set to automatically acquire R traces, containing N\*R samples/channel of data, without additional software intervention.

The Re-Trigger setting can be used for Post-Trigger and Delayed-Trigger modes, with different limitations on the spacing between trigger events in each mode. Trigger events arriving too close to the previous instance will be ignored by the digitizer.

▶ In Post-Trigger mode, the minimum spacing between trigger events is N+1
▶ In Delayed-Trigger mode, the minimum spacing between trigger events is $(N+D)+1$ , where D is the number of the delayed setting
▶ If R is set to zero, it means infinite re-trigger.

![This image is a timing diagram illustrating the relationship between time, triggers, and data acquisition.\n\n**Top Section (Timeline & Events):**\n*   A horizontal black arrow points to the right, labeled **'Time'** at the far right end.\n*   Above this timeline, there are three text labels with downward-pointing arrows indicating specific moments:\n    *   **'Operation Start'**\n    *   **'1st Trigger Event Occurs'** (aligned with the start of the first pulse)\n    *   **'2nd Trigger Event Occurs'** (aligned with the start of the second pulse)\n\n**Middle Section (Trigger Signal):**\n*   A horizontal line labeled **'Trigger'** on the left.\n*   It features two rectangular pulses.\n    *   The first pulse aligns vertically with the text **'1st Trigger Event Occurs'**.\n    *   The second pulse aligns vertically with the text **'2nd Trigger Event Occurs'**.\n\n**Bottom Section (Data Signal):**\n*   A horizontal line labeled **'Data'** on the left.\n*   It features two rectangular blocks representing data acquisition windows.\n    *   The first block is labeled **'N Samples'** and begins shortly after the first trigger pulse.\n    *   The second block is labeled **'N Samples'** and begins shortly after the second trigger pulse.](.pxie-9834-50-17057-1000-10/a9101c7b358249371235736361955134cd4023725988a262fe30c7883c7363f7.jpg)

Figure 3-11: Re-Trigger Mode Acquisition

# 3.5 Timebase

![The flowchart depicts a signal routing and buffering system with the following labeled blocks and connections:\n\n**Blocks:**\n*   **Onboard Oscillator** (Top left source)\n*   **PXI_CLK10** (Bottom left input)\n*   **MUX** (Small trapezoid on the left)\n*   **Phase Lock Loop** (Rectangle in the center)\n*   **MUX** (Large trapezoid in the center)\n*   **Buffer** (Stack of four triangles on the right)\n\n**Connections:**\n1.  **Onboard Oscillator** routes signals to three locations:\n    *   Directly to the top input of the large **MUX**.\n    *   Directly to the second input of the large **MUX**.\n    *   Downward to the top input of the small **MUX**.\n2.  **PXI_CLK10** connects to the bottom input of the small **MUX**.\n3.  The output of the small **MUX** connects to the input of the **Phase Lock Loop**.\n4.  The output of the **Phase Lock Loop** connects to the bottom input of the large **MUX**.\n5.  The output of the large **MUX** connects to the input of the **Buffer**.\n6.  The four outputs of the **Buffer** connect to the labels **ADC 0**, **ADC 1**, **ADC 2**, and **ADC 3**.](.pxie-9834-50-17057-1000-10/ebc0afefbf7116040edb337d5b2850501dc9e97ba0d3d4ed28524fa6a92310ac.jpg)

Figure 3-12: Timebase Architecture

# 3.5.1 Internal Sampling Clock

The PXIe-9834 internal 80MHz crystal oscillator acts as a sampling clock for ADC.

# 3.5.2 External Sampling Clock

For different frequency sampling clock settings, the PXIe-9834 provides external clock input from front panel SMA connector (CLK IN). When an external sampling clock is selected, the ADC sampling frequency switches to external clock source, with clock source frequency available from 10MHz to 20MHz. IT should be noted that if the frequency of the external sample clock is changed, the ADC needs to be re-configured synchronously. AI configuration via software API is thus necessary. For example, in C/C++ API, API function WD\_AI\_Config() must be called.

# 3.5.3 External Reference Clock

The onboard phase-lock loop (PLL) circuit allows the PXIe-9834 to synch to an external 10MHz reference, in situation where multi-module synchronization in the timebase is needed. By software command, the CLK IN will route external 10MHz clock to the PLL synthesizer and generate a precise 80MHz clock for ADC.

As an added benefit from the PXIe platform, the chassis also provides reference 10MHz clock to each peripheral PXIe slot. The PXIe-9834 also routes this 10MHz to internal PLL circuit, enabling synchronization of multiple PXIe-9834 modules in a single chassis with no external cabling requirement.

# 3.6 Acquisition Timing Control

The PXIe-9834 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger, analog trigger, PXI\_STAR, PXI Trigger Bus, or PXIe\_DSTARB. Trigger mode allows collection of data when the trigger event occurs, depending trigger mode type. timebase provides an essential timing clock for ADC operation. To achieve different acquisition timing, more configurations may be required.

Using Post-Trigger mode as an example, as shown in the following figure, when a trigger is accepted by the digitizer, the acquisition engine commences acquisition of data from ADC and stores the sampled data to onboard memory. When onboard memory is not empty, data will be transferred to system memory automatically via the DMA (Direct Memory Access) engine. The sampled data is generated continuously at the rising edge of timebase according to the scan interval counter (ScanIntrv) setting. When sampled data reaches a specified value (DataCnt), acquisition is complete.

![This diagram illustrates a timing relationship between a trigger signal, a timebase, and data samples across three different scan intervals.\n\n**Labeled Blocks and Signals:**\n*   **Trigger**: A square wave signal at the very top.\n*   **Timebase**: A square wave signal immediately below the trigger.\n*   **DATA sampled**: A label bracketing the three rows of data blocks below the timebase.\n*   **Acquisition In Progress**: Text at the bottom left.\n\n**Connections and Data Rows:**\nUnder the **DATA sampled** bracket, there are three rows corresponding to different scan intervals:\n\n1.  **ScanIntrv = 1**: A continuous row of hexagonal blocks aligned with the **Timebase** pulses. The blocks are labeled sequentially: **D1**, **D2**, **D3**, **D4**, **D5**, **D6**, **D7**, **D8**, **D9**, **D10**.\n2.  **ScanIntrv = 2**: A row of blocks spaced further apart (every other timebase slot). The blocks are labeled: **D1**, **D2**, **D3**, **D4**, **D5**, **D6**.\n3.  **ScanIntrv = 3**: A row of blocks spaced even further apart. The blocks are labeled: **D1**, **D2**, **D3**, **D5** (note that D4 is skipped).\n\n**Bottom Annotation:**\n*   An arrow points from **Acquisition In Progress** to the second pulse of the **Timebase** signal.\n*   Text next to the arrow reads: **Acquisition starts right after this clock edge**.](.pxie-9834-50-17057-1000-10/23433821cd1a32dfcdfa0a51377b265f36490326b576b7f98b1275cbf0f48c21.jpg)

Figure 3-13: Varying Sampling Rates via Scan Interval Counter

To achieve sampling rates other than 80MS/s, the scan interval counter (ScanIntrv) needs to be specified. For example, if the scan interval counter is set to 2, the equivalent sampling rate is 80MS/s/2=40MS/s. If 3, the equivalent sampling rate is 80MS/s/3=26.66MS/s, and vice versa. The scan interval counter is 16 bits in width, therefore the lowest sampling rate is 1.121KS/s (80MS/s/65535).

<table><tr><td>Counter</td><td>Function</td><td>Length</td><td>Valid Value</td><td>Comment</td></tr><tr><td>ScanIntrv</td><td>Scan Interval Counter</td><td>16-bit</td><td>1-65535</td><td>Timebase divider to achieve equivalent sampling rate of the digitizer, when sampling rate=timebase/ ScanIntrv</td></tr><tr><td>DataCnt</td><td>Data Counter</td><td>31-bit</td><td>1-2147483647</td><td>Specifies the amount of data to be acquired; invalid when double buffer mode (infinite data number) is selected for continuous data sampling</td></tr><tr><td>trigDelayTicks</td><td>Delay Trigger Counter</td><td>16-bit</td><td>1-65535</td><td>Indicates time between a trigger event and commencement of acquisition, where unit of a delay counter is the period of the timebase (See “Delayed Trigger Mode” on page 32.)</td></tr><tr><td>ReTrgCnt</td><td>Re-Trigger Counter</td><td>31-bit</td><td>1-2147483647</td><td>Enables re-trigger to accept multiple triggers (See “Acquisition with Re-Triggering” on page 34.)</td></tr></table>

Table 3-4: Counter Parameters and Description

# 3.7 Synchronizing Multiple Modules

Analog input channels on a single module, sharing the same time-base and trigger signals, are automatically synchronized. When synchronizing analog input channels between modules, however, correct module configuration and timebase and trigger signal wiring are critical for optimum synchronization.

Digitizer modules such as the PXle-9834 support trigger synchronization and timebase synchronization.

Trigger synchronization implements a signal that initiates acquisition, and timebase synchronization provides the fundamental clock for AD operation.

As shown in the following, two digitizer modules operating at diverse onboard clock and trigger signals (free run) result in not only trigger time difference, but also clock phase error.

![The diagram is labeled **Digitizer Module #1** at the bottom right. It contains the following labeled blocks and connections:\n\n**Labeled Blocks:**\n*   **CLK#1**: A circular block containing a clock symbol.\n*   **ADC**: Four vertically stacked blocks.\n*   **Trigger Decision**: A rectangular block.\n*   **Digitizer Controller**: A large rectangular block.\n\n**Connections:**\n*   Four input circles on the far left connect to the left side of the four **ADC** blocks.\n*   A green line originates from **CLK#1**, goes right, and then down to connect to the four **ADC** blocks.\n*   Four lines connect the right side of the **ADC** blocks to the left side of the **Digitizer Controller**.\n*   An orange line labeled **TRG#1** connects the **Trigger Decision** block to the top of the **Digitizer Controller**.](.pxie-9834-50-17057-1000-10/75892b36a94b08dc52292526aee96810fb103be909f0bd6a7680914be7a2f190.jpg)

![Based on the provided image, here is the description of the flowchart/block diagram:\n\n**Labeled Blocks and Text:**\n*   **CLK#2** (green text inside a circle containing a square wave symbol)\n*   **ADC** (black text repeated four times inside stacked trapezoidal blocks)\n*   **Trigger Decision** (orange text inside an orange rectangular box)\n*   **TRG#2** (orange text next to the output line of the Trigger Decision box)\n*   **Digitizer Controller** (black text inside a large square box)\n*   **Digitizer Module #2** (black text below the Digitizer Controller box)\n\n**Connections:**\n*   Four input circles on the far left connect to the four **ADC** blocks.\n*   A green line connects the **CLK#2** source to the top section of the **ADC** stack.\n*   Lines extend from the right side of the **ADC** blocks; a thick black line connects the **ADC** stack to the left side of the **Digitizer Controller**.\n*   An orange line labeled **TRG#2** connects the **Trigger Decision** block to the top of the **Digitizer Controller**.](.pxie-9834-50-17057-1000-10/b632b0d422435cb116509745fcdad301ad0e1a34ed6936ee11e387b4be7a5e4c.jpg)

![| Channel | Trigger Delay | Clock Phase Error |\n|---------|---------------|-------------------|\n| TRG#1   | High          | Low               |\n| CLK#1   | Low           | High              |\n| TRG#2   | High          | Low               |\n| CLK#2   | Low           | High              |](.pxie-9834-50-17057-1000-10/4a380c7c47a17529ca2dae3bfbb2136a2b7f29597392325718251b92b73c31b6.jpg)

Figure 3-14: Non-synched Digitizer Modules

With appropriate configuration of digitizer modules and effective instrument support, however, trigger or timebase synchronization, or both can be achieved, commensurate with application requirements.

As shown in the following, in a simple synchronization architecture, two digitizer modules receive trigger and timebase from a function generator. With required buffering of trigger and timebase signals and equal wiring length between the function generator and digitizers, trigger and timebase synchronization are possible. In this scenario, the function generator is a master device that outputs trigger and timebase, and the two digitizers are slave devices sharing the same trigger and timebase.

![The image displays a block diagram illustrating the connection between a function generator and two digitizers.\n\n**Labeled Blocks:**\n*   **Function Generator (Master):** A device on the left with a screen displaying a sine wave. It features buttons labeled 'Sine', 'Square', 'Ramp', 'Pulse', and 'Noise'. On its right side, there are two BNC connectors labeled 'Sync' (top) and 'Output' (middle).\n*   **Digitizer #1 (Slave):** A rectangular block on the top right. It has two inputs labeled 'TRG IN' (top) and 'CLK IN' (middle).\n*   **Digitizer #2:** A rectangular block on the bottom right. It has two inputs labeled 'TRG IN' (top) and 'CLK IN' (middle).\n\n**Connections:**\n*   **Orange Line:** Connects the 'Sync' port on the Function Generator to the 'TRG IN' port on Digitizer #1 and the 'TRG IN' port on Digitizer #2.\n*   **Green Line:** Connects the 'Output' port on the Function Generator to the 'TRG IN' port on Digitizer #2 and the 'CLK IN' port on Digitizer #1.](.pxie-9834-50-17057-1000-10/d328fe88205215c52fb52c4cc506b293e52203862aa1939755489d4fdc5c68d2.jpg)

(Slave)

![| Digitizer | Signal Type | Value |\n| --------- | ----------- | ----- |\n| TRG#1     | TRG#1       | 0     |\n| TRG#1     | CLK#1       | 0     |\n| TRG#2     | TRG#2       | 0     |\n| TRG#2     | CLK#2       | 0     |](.pxie-9834-50-17057-1000-10/a1505dbe278ad9b925c1bf9ba58ce43f3a263e8a9fa8b3584d34dcea61e2b62e.jpg)

Figure 3-15: External Instrument Synchronization

Some digitizer modules provide advanced features that can output trigger or timebase to external devices, enabling multi-module synchronization as well. As shown in the following, digitizer #1 acts as a master device and transmits trigger/timebase to the two slave digitizers.

![The flowchart depicts a digitizer system with a master module and two slave modules.\n\n**Top Section (Digitizer Module #1):**\n*   **Blocks:**\n    *   'TRG OUT' (circle with a plus sign)\n    *   'CLK OUT' (circle with a plus sign)\n    *   'CLK#1' (circle with a square wave symbol, green text)\n    *   'Trigger Decision' (rectangular box)\n    *   'TRG#1' (orange text label)\n    *   'Digitizer Controller' (rectangular box)\n    *   'ADC' (four stacked rectangular blocks)\n    *   'Digitizer Module #1' (text label below the ADCs)\n*   **Connections:**\n    *   A line from 'TRG OUT' connects to 'Trigger Decision'.\n    *   'TRG OUT' is also connected to a vertical orange line running down the far left side.\n    *   'Trigger Decision' outputs 'TRG#1', which connects to the vertical orange line.\n    *   The vertical orange line connects to 'TRG IN' for 'Digitizer #2' and 'Digitizer #3'.\n    *   'CLK OUT' connects to a vertical green line running down the far left side.\n    *   'CLK#1' connects to four input circles.\n    *   These four input circles connect to the 'ADC' blocks.\n    *   The 'ADC' blocks have outputs connecting to both 'Digitizer Controller' and 'Trigger Decision'.\n\n**Middle and Bottom Sections (Slaves):**\n*   **Blocks:**\n    *   'Digitizer #2' (rectangular box) with '(Slave)' text next to it.\n    *   'Digitizer #3' (rectangular box) with '(Slave)' text next to it.\n*   **Connections:**\n    *   'Digitizer #2' has inputs labeled 'TRG IN' (connected to the vertical orange line) and 'CLK IN' (connected to the vertical green line).\n    *   'Digitizer #3' has inputs labeled 'TRG IN' (connected to the vertical orange line) and 'CLK IN' (connected to the vertical green line).](.pxie-9834-50-17057-1000-10/e86ac1aed98574ec560602bbf0a9e4b4b20a2dcc397da66954b9c63fe47ce962.jpg)

Figure 3-16: Module-based Synchronization

In the scenarios described, trigger and timebase signal buffering is required, with one or multiple signal buffering modules necessary to maximize signal quality. Moreover, signal wiring must be precisely deployed to minimize timing skew.

The PXIe-9834, based on PXI Express HW & SW specifications, enables trigger and clock signals to be fully leveraged and benefits from the routing architecture of the PXI Express chassis. The PXI Express chassis provides additional timing and synchronization capabilities for more accurate measurement and improved new application management. Overall PXI Express chassis instrumentation signals are as follows.

![Based on the provided flowchart, here are the labeled blocks and their connections:\n\n**Labeled Blocks**\n*   **Legend:** 'PXI', 'PXI Express'\n*   **Timing/Clock Blocks:** '100 MHz Differential CLK', 'SYNC100', '10 MHz CLK'\n*   **Controller/Peripheral Blocks:** 'PXI Express System Controller', 'PXI Express System Timing Controller', 'PXI Express Peripheral', 'Hybrid Peripheral', 'PXI Peripheral'\n*   **Bus Block:** 'PXI Trigger Bus (8 TTL Triggers)'\n\n**Connections**\n*   **Star Trigger:** Cyan lines connect 'PXI Express System Controller' to 'PXI Express System Timing Controller', 'PXI Express Peripheral', 'Hybrid Peripheral', and 'PXI Peripheral'.\n*   **Differential Star Triggers:** Orange lines connect 'PXI Express System Timing Controller' to 'PXI Express Peripheral', 'Hybrid Peripheral', and 'PXI Peripheral'.\n*   **100 MHz Differential CLK:** Orange lines connect to 'PXI Express System Timing Controller', 'PXI Express Peripheral', 'Hybrid Peripheral', and 'PXI Peripheral'.\n*   **SYNC100:** Orange lines connect to 'PXI Express System Timing Controller', 'PXI Express Peripheral', and 'Hybrid Peripheral'.\n*   **10 MHz CLK:** Cyan lines connect to 'PXI Express System Timing Controller', 'PXI Express Peripheral', 'Hybrid Peripheral', and 'PXI Peripheral'.\n*   **PXI Trigger Bus (8 TTL Triggers):** Vertical arrows connect 'PXI Express System Controller', 'PXI Express System Timing Controller', 'PXI Express Peripheral', 'Hybrid Peripheral', and 'PXI Peripheral' to the bus.](.pxie-9834-50-17057-1000-10/e1a83894b8112a3de12476a3febd4cabb2055910853051bd8a1075e6a09b3a36.jpg)

Figure reprinted courtesy of PXI Express Specification Tutorial.pdf from PXI System Alliance website (www.pxisa.org).
Figure 3-17: PXIe Instrumentation Signals

In the PXIe chassis, a system timing slot distributes trigger signals through PXI\_STAR and PXIe differential star triggers. The 8-bit parallel PXI Trigger Bus provides additional channels for transmitting and receiving triggers between peripheral slots. The PXIe chassis further provides 10MHz (PXI\_CLK10) clock options distributed to each peripheral slot with minimal clock skew.

# 3.7.1 Multi-module Synchronization Interfaces

As shown in the following, four trigger input channels on the PXIe-9834 can receive triggers from a master device. The external digital trigger input is on the front panel, and the PXI Trigger Bus, PXI\_STAR, and PXIe\_DSTARB are from the PXIe chassis. When the PXIe-9834 acts as a master device, its trigger signal is output to one bit of the PXI Trigger Bus, as determined by software selection.

![The flowchart depicts a signal routing process starting with seven input labels on the left: **Software Trigger**, **External Digital Trigger**, **Analog Trigger**, **PXI Trigger Bus**, **PXI_STAR**, and **PXle_DSTARB**. Arrows from each of these labels point into a large trapezoidal block labeled **MUX**.\n\nA single arrow connects the right side of the **MUX** block to the left side of a square block labeled **Trigger Decision**.\n\nFrom the right side of the **Trigger Decision** block, the line extends and splits into two outputs:\n*   One arrow points to the text **To internal FPGA**.\n*   Another arrow points to the text **PXI Trigger Bus**.](.pxie-9834-50-17057-1000-10/a5768306097cec8e3aa77c03385bd6d23f6db08d2e76f19edf99fdc2cc84b013.jpg)

Figure 3-18: Trigger Architecture

For timebase synchronization, the PXIe-9834 acts as a slave device, receiving external sampling clock or 10MHz reference clock from the front panel CLK IN or PXI\_CLK10 from the PXIe chassis.

![Based on the provided block diagram, here is an accurate and concise description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   **Onboard Oscillator** (Top left)\n*   **PXI_CLK10** (Bottom left)\n*   **MUX** (Left side, trapezoid shape)\n*   **Phase Lock Loop** (Center, rectangle)\n*   **MUX** (Center, large trapezoid shape)\n*   **Buffer** (Right side, group of four triangles)\n\n**Outputs/Labels:**\n*   **ADC 0**, **ADC 1**, **ADC 2**, **ADC 3** (Far right)\n\n**Connections:**\n1.  **Onboard Oscillator**: A line extends from this label to the top input of the large central **MUX**. From this same line, a vertical branch drops down and splits into two paths:\n    *   One horizontal path goes to the middle input of the large central **MUX**.\n    *   One vertical path goes down to the top input of the left-side **MUX**.\n2.  **PXI_CLK10**: An arrow connects this label to the bottom input of the left-side **MUX**.\n3.  **Left-side MUX**: Its output connects to the **Phase Lock Loop**.\n4.  **Phase Lock Loop**: Its output connects to the bottom input of the large central **MUX**.\n5.  **Large Central MUX**: Its single output line splits into four separate lines entering the **Buffer** block.\n6.  **Buffer**: The four triangular shapes within this block each have an output arrow pointing to the right, labeled sequentially as **ADC 0**, **ADC 1**, **ADC 2**, and **ADC 3**.](.pxie-9834-50-17057-1000-10/0aa698e64616e029579fa72209a8ef491478789721b71c6290864e3f65648686.jpg)

Figure 3-19: PXI\_CLK10 as 10MHz Reference

# Appendix A Calibration

This chapter introduces the calibration process to minimize analog input measurement errors.

# A.1 Calibration Constant

The PXIe-9834 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PXIe-9834 driver loads these calibration constants, such that analog input path errors are minimized. ADLINK provides a software API for calibrating the PXIe-9834.

The onboard EEPROM provides two banks for calibration constant storage. Bank 0, the default bank, records the factory calibrated constants, providing written protection preventing erroneous auto-calibration. Bank 1 is user-defined space, provided for storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to Bank 1.

When PXle-9834 boots, the driver accesses the calibration constants and is automatically set to hardware. In the absence of user assignment, the driver loads constants stored in bank 0. If constants from Bank 1 are to be loaded, the preferred bank can be designated as boot bank by software. Following re-assignment of the bank, the driver will load the desired constants on system reboot. This setting is recorded to EEPROM and is retained until reconfiguration.

# A.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, re-calibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PXIe-9834 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Before initializing auto-calibration, it is recommended to warm up the PXIe-9834 for at least 20 minutes and remove connected cables.

![The image displays a simple icon of a document. It features a white rectangular sheet of paper with a folded top-left corner. Faint horizontal lines run across the lower portion of the paper. Overlaid on top of the document is a large, bold red checkmark that angles upward from left to right.](.pxie-9834-50-17057-1000-10/9956d6f6a86d00c2711776f35d02d34adc470a949d5591649f38b24b7841dc60.jpg)
NOTE:

It is not necessary to manually factor delay into applications, as the PXIe-9834 driver automatically adds the compensation time.

![The diagram illustrates the signal processing architecture for the **PXIe-9834**.\n\n**Labeled Blocks:**\n*   **PXIe-9834** (top right corner)\n*   **Onboard Calibration Source** (a circle with '+' and '-' terminals)\n*   **Switch** (two rectangular boxes)\n*   **Signal Path / Internal Calibration Source** (text below the switches)\n*   **Analog Front End** (two triangles)\n*   **ADC** (a hexagonal block)\n\n**Connections:**\n*   **Inputs:** Two cylindrical blocks on the left represent input channels. Dashed lines indicate additional channels.\n*   **Switching Stage:**\n    *   The signal line from the top cylindrical block connects to a black junction dot. From this dot, lines branch to the right (to the top input of the top **Switch**), up (to the **Onboard Calibration Source**), and down (to a vertical line).\n    *   This vertical line connects to the bottom input of the bottom **Switch** and the bottom input of the top **Switch**.\n    *   The signal line from the bottom cylindrical block connects to the top input of the bottom **Switch**.\n    *   The **Onboard Calibration Source** circle also has a line extending to the right with an arrow.\n*   **Amplification:** The outputs of the two **Switch** blocks connect to the inputs of the two **Analog Front End** triangles.\n*   **Conversion:** The outputs of the **Analog Front End** triangles connect to the **ADC**.](.pxie-9834-50-17057-1000-10/596dbfda622b2a16c770e67726960baa3c95ac53a81a69a3ef660ae846a05fa5.jpg)

Figure A-1: Auto-Calibration Block Diagram

![The flowchart illustrates an auto-calibration process divided into two main sections: offset compensation and gain compensation.\n\n**Labeled Blocks:**\n*   Auto-calibration start\n*   Set analog front end input to onboard calibration source\n*   Set calibration source to ground\n*   Capture data and calculate offset compensation parameters\n*   Are all channels and all ranges complete?\n*   Set calibration source to calibration voltage\n*   Capture data and calculate gain compensation parameters\n*   Are all channels and all ranges complete?\n*   Set analog front end input to SMB connector\n*   Auto-calibration complete\n\n**Connections:**\n1.  **Auto-calibration start** connects downward to **Set analog front end input to onboard calibration source**.\n2.  This block connects downward to **Set calibration source to ground**.\n3.  This block connects downward to **Capture data and calculate offset compensation parameters**.\n4.  This block connects downward to the first decision diamond: **Are all channels and all ranges complete?**.\n    *   The **No** path loops back upward to **Capture data and calculate offset compensation parameters**.\n    *   The **Yes** path goes downward, turns right, then upward to connect to the right-hand column's first block: **Set calibration source to calibration voltage**.\n5.  **Set calibration source to calibration voltage** connects downward to **Capture data and calculate gain compensation parameters**.\n6.  This block connects downward to the second decision diamond: **Are all channels and all ranges complete?**.\n    *   The **No** path loops back upward to **Capture data and calculate gain compensation parameters**.\n    *   The **Yes** path connects downward to **Set analog front end input to SMB connector**.\n7.  This block connects downward to the final block: **Auto-calibration complete**.](.pxie-9834-50-17057-1000-10/721f7bc6c85bb6be73f066c40f9c1b1bf40a479c28a67c657ce29032d3fd5dc8.jpg)

Figure A-2: Auto-Calibration Flow

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# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil, pour éviter des blessures ou des dommages.

▶ Read these safety instructions carefully
- Keep the User’s Manual for future reference
▶ Read the Specifications section of this manual for detailed information on the recommended operating environment
▶ The device can be operated at an ambient temperature of $50^{\circ}$ C
- When installing/mounting or uninstalling/removing device; or when removal of a chassis cover is required for user servicing:

▷ Turn off power and unplug any power cords/cables
▷ Reinstall all chassis covers before restoring power

▶ To avoid electrical shock and/or damage to device:

▷ Keep device away from water or liquid sources
▷ Keep device away from high heat or humidity
▷ Keep device properly ventilated (do not block or cover ventilation openings)
▶ Always use recommended voltage and power source settings
▶ Always install and operate device near an easily accessible electrical outlet
▷ Secure the power cord (do not place any object on/over the power cord)
▶ Only install/attach and operate device on stable surfaces and/or recommended mountings

▶ If the device will not be used for long periods of time, turn off and unplug from its power source

▶ Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools
▶ A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![This image displays a standard warning sign. It features a yellow triangle with a black border containing a large black exclamation point. Below the triangle, the word 'CAUTION' appears in black, capital letters.](.pxie-9834-50-17057-1000-10/d0489ed7d3ef1869730065a9e9e306842e113f95751d74e6fa335b8ad7c58120.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

Risque d'explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

▶ The device must be serviced by authorized technicians when:

The power cord or plug is damaged
▷ Liquid has entered the device interior
The device has been exposed to high humidity and/or moisture
The device is not functioning or does not function according to the User's Manual
The device has been dropped and/or damaged and/or shows obvious signs of breakage

▶ Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up

It is recommended that the device be installed only in a server room or computer room where access is:

▶ Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required

▶ Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.pxie-9834-50-17057-1000-10/3adbb5de26c9e73eef1219c854cb650f627caf987e1108c3536d075ab6edfbec.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures.

Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

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# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

9F, No.166 Jian Yi Road, Zhonghe District

New Taipei City 235, Taiwan

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

5215 Hellyer Avenue, #110

San Jose, CA 95138, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.pxie-9834-50-17057-1000-10/pxie-9834-50-17057-1000-10.pdf)