# PXIe-9848

8-CH 14Bit 100 MS/s High-Speed PXI Express Digitizer

User's Manual

![Exterior view of a ADLINK Technology Inc. device with gold connectors and a green circuit board (no readable text or symbols beyond branding)](.pxie-9848-50-17040-1010-201-en/98bc754e3c9b56535772fc17612cadd4054cba4740493f84baf3df7192cdbde9.jpg)

Manual Rev.: 2.01

Revision Date: Jan. 15, 2013

Part No: 50-17040-1010

![Circular black-and-white recycling symbol with three white arrows forming a triangle (no text or symbols)](.pxie-9848-50-17040-1010-201-en/5576e1aa0ac504fb844cfedbbb8d8592a12cb8f544818dee3158f1a6b0808a55.jpg)

Recycled Paper

# Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>2.00</td><td>2012/10/26</td><td>Initial Release</td></tr><tr><td>2.01</td><td>2013/01/15</td><td>Graphic labeling corrected</td></tr></table>

# Preface

# Copyright 2013 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image shows a white document icon featuring a folded top-left corner and faint horizontal gray lines. A large, bold red checkmark is superimposed over the center of the paper.](.pxie-9848-50-17040-1010-201-en/66669cd72f4baae47ae141ad16bef7fdb881721935c1585819f387130cfca663.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign containing a large black exclamation point in the center. A thin black horizontal line runs across the very top of the image, intersecting the upper corner of the triangle against a white background.](.pxie-9848-50-17040-1010-201-en/3cbb19d28da6eb37ca9f3ce7b3ec856d2f51a78d25793ff69e7c5caa16b0aff2.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![This image features a red triangular warning sign with a large white exclamation mark centered inside.](.pxie-9848-50-17040-1010-201-en/3e18ab3192a3c110bc4ac88201e3673793fdf6253dd402b8cb41aa9ce9a14ae8.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Preface .... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Features.... 1
1.2 Applications 2
1.3 Specifications.... 2

1.3.1 Analog Input 2
1.3.2 Timebase 3
1.3.3 Triggers 4
1.3.4 General Specifications....4

1.4 Software Support 5

1.4.1 SDK 5
1.4.2 WD-DASK....6

1.5 Device Layout and I/O Array.... 7

# 2 ...... Getting Started 9

2.1 Installation Environment 9
2.2 Installing the module.... 10

# 3 Operations 13

3.1 Functional Block Diagram.... 13
3.2 Analog Input Channel 13

3.2.1 Analog Input Front-End Configuration 13
3.2.2 Input Range and Data Format 15
3.2.3 FIFO and DMA Transfer For Analog Input 16

3.3 Trigger Source and Trigger Modes.... 18

3.3.1 Trigger Sources 18

# 3.4 Trigger Modes.... 22

3.4.1 Post Trigger Mode 23
3.4.2 Pre-trigger Mode 23
3.4.3 Middle-trigger Mode....24
3.4.4 Delayed Trigger Mode 24
3.4.5 Post-Trigger or Delayed-Trigger Acquisition with Re-Trig-
gering....25

# 3.5 ADC Timing Control 25

3.5.1 Timebase Architecture....25
3.5.2 Basic Acquisition Timing....26

# 4 Calibration 29

4.1 Calibration Constant 29
4.2 Auto-Calibration 29

# Important Safety Instructions.... 31

# Getting Service 33

# List of Figures

Figure 1-1: Analog Input Channel Bandwidth, ±2 V Input Range 20MHz3

Figure 1-2: Analog Input Channel Bandwidth, ±2 V Input Range 100MHz3

Figure 1-3: PXIe-9848 Dimensions....7

Figure 1-4: PXIe-9848 I/O Array 8

Figure 3-1: Analog Input Architecture of the PXIe-9848 ...... 13

Figure 3-2: Linked List of PCI Address DMA Descriptors ..... 17

Figure 3-3: Trigger Architecture of the PXIe-9848 18

Figure 3-4: External Digital Trigger 19

Figure 3-5: External Digital Trigger Configuration....20

Figure 3-6: Analog Trigger Conditions 21

Figure 3-7: Post-Trigger Acquisition 23

Figure 3-8: Pre-trigger Acquisition 23

Figure 3-9: Middle-trigger Acquisition 24

Figure 3-10: Delayed Trigger Mode Acquisition....24

Figure 3-11: Re-Trigger Mode Acquisition 25

Figure 3-12: PXIe-9848 Timebase Architecture....25

Figure 3-13: Basic Digitizer Acquisition Timing....27

Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval Counter27

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# List of Tables

Table 1-1: Channel Characteristics....2
Table 1-2: Analog Input Bandwidth....2
Table 1-3: Timebase....3
Table 1-4: Trigger Source & Mode......4
Table 1-5: Digital Trigger Input 4
Table 1-6: PXIe-9848 I/O Array 8
Table 3-1: Input Range and Data Format 15
Table 3-2: Input Range FSR and -FSR Values....15
Table 3-3: Input Range Midscale Values....15
Table 3-4: Ideal Transfer Characteristics for Analog Triggers ..... 22
Table 3-5: Counter Parameters and Description ...... 28

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# 1 Introduction

The PXIe-9848 high-speed 8CH 14-bit 100 MS/s digitizer is specifically designed for applications such as PSU (power supply unit) testing, LIDAR testing, and radar signal acquisition. Analog inputs with 100 MHz bandwidth can receive ±2V high-speed signals with 50Ω impedance. With a simplified front-end design and highly stable onboard reference, the PXIe-9848 provides not only highly accurate measurement results but also superior dynamic performance.

For applications requiring real-time data acquisition and transfer, PXIe-9848 is based on the PXI Express x4 bus interface. When signals are converted from analog to digital, data is continuously transferred to host system memory thanks to maximized PCI Express bandwidth.

PXle-9848's auto-calibration is performed with onboard reference circuitry that calibrates the offset and gain errors of analog input. Once complete, the calibration constant is stored in EEPROM, to be loaded and used as needed by the board. Because all calibration is executed automatically by software command, no manual calibration of the module is required.

# 1.1 Features

▶ PXI Express hardware specification Rev. 1.0 compliant
▶ Up to 100 MS/s sampling rate
▶ High resolution 14-Bit ADC
▶ 100 MHz bandwidth for analog input
▶ 512 MB onboard storage memory
▶ Scatter-Gather DMA data transfer for high-speed data streaming
▶ One external digital trigger input
▶ Full auto-calibration

# 1.2 Applications

▶ Radar signal acquisition
▶ IF signal spectrum monitoring
▶ Optical fiber testing
▶ Power supply unit (PSU) testing
▶ Cable fault location and partial discharge monitoring for power applications

# 1.3 Specifications

# 1.3.1 Analog Input

<table><tr><td colspan="2">Channel Characteristics</td></tr><tr><td>Channels</td><td>8 single-ended channels</td></tr><tr><td>Connector type</td><td>SMB screw type</td></tr><tr><td>Input coupling</td><td>AC or DC, software selectable</td></tr><tr><td>ADC resolution</td><td>14-Bit</td></tr><tr><td>Input signal range</td><td>±2.0 V or ±0.2 V</td></tr><tr><td>Overvoltage</td><td>±5 V</td></tr><tr><td>Input impedance</td><td>50 Ω or 1 MΩ, software selectable</td></tr><tr><td>Offset error</td><td>±1 mV</td></tr><tr><td>Gain error</td><td>±0.5%</td></tr></table>

Table 1-1: Channel Characteristics

<table><tr><td colspan="2">Analog Input Bandwidth (-3 dB)</td></tr><tr><td>±2.0 V input</td><td>100 MHz or 20 MHz, software selectable</td></tr></table>

Table 1-2: Analog Input Bandwidth

![| Frequency (MHz) | Bandwidth (dB) |\n| --------------- | -------------- |\n| 1               | 0              |\n| 10              | -1             |\n| )10             | -8             |](.pxie-9848-50-17040-1010-201-en/366abe45ba0c9b75f6962c9b4441f92a42714a962f74f3176ab4e3a6c3de8302.jpg)

Figure 1-1: Analog Input Channel Bandwidth, ±2 V Input Range 20MHz

![| Frequency (MHz) | Impedence (dB) |\n| --------------- | -------------- |\n| 1               | 0.0            |\n| 10              | -0.2           |\n| 100             | -3.8           |](.pxie-9848-50-17040-1010-201-en/b8043882aabae0b843610b80ed751b2267cd262aec2be06310ad06fa7a1f0dbb.jpg)

Figure 1-2: Analog Input Channel Bandwidth, ±2 V Input Range 100MHz

# 1.3.2 Timebase

<table><tr><td>Sample clock source</td><td>Internal: onboard clock (oscillator)</td></tr><tr><td>Sample clock source</td><td>Internal: onboard clock (oscillator)External: PXI_CLK10, PXIe_CLK100</td></tr><tr><td>Timebase frequency</td><td>100 MHz</td></tr><tr><td>Sampling rate</td><td>100 MS/s ~ 1025.9 S/s</td></tr><tr><td>Internal Timebase Accuracy</td><td>&lt; ±25 ppm</td></tr></table>

Table 1-3: Timebase

# 1.3.3 Triggers

<table><tr><td colspan="2">Trigger Source &amp; Mode</td></tr><tr><td>Trigger source</td><td>Software command, external digital trigger, analog inputs, PXI trigger bus [0..7], and PXIe_DSTARB and PXI_STAR</td></tr><tr><td>Trigger mode</td><td>Post-trigger, pre-trigger, middle trigger, and delay trigger, re-trigger for all trigger modes</td></tr></table>

Table 1-4: Trigger Source & Mode

<table><tr><td colspan="2">Digital Trigger Input</td></tr><tr><td>Sources</td><td>Front panel SMB connector</td></tr><tr><td>Configurable threshold</td><td>0.8 mV ~ 3.3 V, default 1.67 V</td></tr><tr><td>Adjustable step</td><td>0.8 mV, 3.3 V with 12-bit resolution</td></tr><tr><td>Maximum input overload</td><td>-0.5 V ~ +5.5 V</td></tr><tr><td>Trigger polarity</td><td>Rising or falling edge</td></tr><tr><td>Pulse width</td><td>20 ns minimum</td></tr></table>

Table 1-5: Digital Trigger Input

# 1.3.4 General Specifications

<table><tr><td colspan="2">Specifications</td></tr><tr><td>Physical dimensions</td><td>160 W x 100 H mm (6.3 x 3.94 in.)</td></tr><tr><td>Bus</td><td></td></tr><tr><td>Bus interface</td><td>PXI Express, PXI hybrid compatible</td></tr><tr><td>PCIe signaling</td><td>PCI Express x 4, Gen 1</td></tr><tr><td colspan="2">Environmental tolerance</td></tr><tr><td>Operating</td><td>Temperature: 0°C - 50°CRelative humidity: 5% - 95%, non-condensing</td></tr><tr><td>Storage</td><td>Temperature: -20°C - +80°CRelative humidity: 5% - 95%, non-condensing</td></tr><tr><td colspan="2">Calibration</td></tr><tr><td>Onboard reference</td><td>+2.5 V</td></tr><tr><td>Temperature coefficient</td><td> $\le \pm 5$  ppm/ $^{\circ}C$ </td></tr><tr><td>Warm-up time</td><td>15 minutes</td></tr></table>

<table><tr><td colspan="3">Power Consumption</td></tr><tr><td>Power Rail</td><td>Standby Current (mA)</td><td>Full Load (mA)</td></tr><tr><td>+3.3 V</td><td>5350</td><td>5900</td></tr><tr><td>+12 V</td><td>470</td><td>500</td></tr></table>

# 1.4 Software Support

ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from programming libraries, such as DLLs, for most Windows-based systems, ADLINK also provides drivers for other application environments such as LabVIEW $^{®}$ .

All software options are included in the ADLINK All-in-One CD. Commercial software drivers are protected with licensing codes. Without the code, you may install and run the demo version for trial/demonstration purposes for only up to two hours. Contact your ADLINK dealer to purchase the software license.

# 1.4.1 SDK

For customers who want to write their own programs, ADLINK provides the following software development kits.

> DAQPilot for Windows, compatible with various application environments, such as VB.NET, VC.NET, VB/VC++, BCB, and Delphi
▶ DAQPilot for LabVIEW
▶ Toolbox adapter for MATLAB

# 1.4.2 WD-DASK

WD-DASK includes device drivers and DLL for Windows 2000/XP/Vista/7. DLL is binary compatible across Windows 2000/XP/Vista/7. This means all applications developed with WD-DASK are compatible with these Windows operating systems. The development environment may be VB, VB.NET, VC++, BCB, and Delphi, or any Windows programming language that allows calls to a DLL. The WD-DASK user and function reference manu-als are on the ADLINK All-in-One CD.

# 1.5 Device Layout and I/O Array

![The image shows an icon of a white document or checklist with a folded top-left corner and horizontal lines representing text. A large, red checkmark is drawn diagonally across the center of the document.](.pxie-9848-50-17040-1010-201-en/642fe99eeea082c3b00b7a7de64d81f9a82e31c51f426e3f8f11c043c065f0ce.jpg)
NOTE:

All dimensions are in mm

![165.04\n162.54\nADLINK\nTECHNOLOGY INC.\n210.032\n100](.pxie-9848-50-17040-1010-201-en/302f0e2c153552b6017f99d929916e6e8e6a482775b71676ce131e828892e761.jpg)

Figure 1-3: PXle-9848 Dimensions

The PXle-9848 I/O array is labeled to indicate connectivity, as shown.

![ADLINK\nPXIe-9648\nTRG IN\nCH0\nCH1\nCH2\nCH3\nCH4\nCH5\nCH6\nCH7](.pxie-9848-50-17040-1010-201-en/67f8e72faab6ee38deee66b8dc2073d9fe32ae749b787b032f6be1f929cd004f.jpg)

Figure 1-4: PXIe-9848 I/O Array

<table><tr><td>Name</td><td>Faceplate Legend</td><td>Type</td><td>Remark</td></tr><tr><td>Ext. Digital Trigger Input</td><td>TRG IN</td><td rowspan="2">SMB screw type</td><td>External digital trigger input, receiving trigger signal from external instrument and initiating acquisition</td></tr><tr><td>Analog Input Channel (x8)</td><td>CH0 to CH7</td><td>Analog input channel</td></tr></table>

Table 1-6: PXIe-9848 I/O Array

# 2 Getting Started

This chapter describes proper installation environment, installation procedures, package contents and basic information users should be aware of regarding the PXIe-9848.

![The image displays a line drawing icon of a document or piece of paper. It features a black outline with horizontal lines suggesting text or a list. A large, bold red checkmark is superimposed over the left side of the paper, indicating approval or completion. The background is white.](.pxie-9848-50-17040-1010-201-en/aefc634bd45a21084deac388acbebbf7bd84b67c15f188d80fb7a785879c2312.jpg)
NOTE:

Diagrams and illustrated equipment are for reference only. Actual system configuration and specifications may vary.

# 2.1 Installation Environment

When unpacking and preparing to install, please refer to Important Safety Instructions.

Only install equipment in well-lit areas on flat, sturdy surfaces with access to basic tools such as flat- and cross-head screwdrivers, preferably with magnetic heads as screws and standoffs are small and easily misplaced.

Recommended Installation Tools

▶ Phillips (cross-head) screwdriver
▶ Flat-head screwdriver
Anti-static wrist strap
▶ Antistatic mat

ADLINK PXIe-9848 DAQ modules are electrostatically sensitive and can be easily damaged by static electricity. The module must be handled on a grounded anti-static mat. The operator must wear an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the carton and packaging for damage. Shipping and handling could cause damage to the equipment inside. Make sure that the equipment and its associated components have no damage before installation.

![A yellow triangular warning sign with a black border features a black exclamation point in the center. Below the triangle, the word 'CAUTION:' is printed in black capital letters.](.pxie-9848-50-17040-1010-201-en/c8ca381ce3b44aa926b3dbeec1a19d923987b3b0f9e8d629278ae541e79ce230.jpg)

The equipment must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing.

▶ Package Contents
▶ PXIe-9848 high-speed digitizer
▶ ADLINK All-in-one compact disc
▶ PXIe-9848 User's Manual

If any of these items are missing or damaged, contact the dealer

![The image displays a maroon triangle containing a white exclamation point. Below the triangle, the text 'WARNING' appears in black capital letters.](.pxie-9848-50-17040-1010-201-en/df0353cc626d764d6575d2fbc92587118a05840c676a4c28cb71b7c7395a87cf.jpg)

Do not install or apply power to equipment that is damaged or missing components. Retain the shipping carton and packing materials for inspection. Please contact your ADLINK dealer/vendor immediately for assistance and obtain authorization before returning any product.

# 2.2 Installing the module

1. Turn off the PXI system/chassis and connect the power cable from the power source.

![The image displays an icon of a white document sheet with a folded top-left corner and faint horizontal lines running across it. A large, bold red checkmark is drawn diagonally across the document, slanting from the bottom left to the top right.](.pxie-9848-50-17040-1010-201-en/92f5f03db44f0f8bb030f9125757329d14be83bc2efcdcf4962498e5a522fbc6.jpg)
NOTE:

Connection of the power cable provides grounding to prevent hazardous ESD (electrostatic discharge).

2. Align the module's edge with the module guide in the PXI chassis.
3. Slide the module into the chassis until resistance is felt from the PXI connector.
4. Push the ejector latch upwards and fully insert the module into the chassis.

5. Once the module is fully seated, a "click" can be heard from the ejector latch.

6. Tighten the screw on the front panel.

7. Power up the PXI system/chassis.

![The image displays a simple graphic icon featuring a white document or page with a folded top-right corner. Faint grey horizontal lines run across the page, resembling text. A large, bold red checkmark is superimposed over the center of the document.](.pxie-9848-50-17040-1010-201-en/ae2862a6fb129b2c51c59c7d1bbb3d3bfba39c96d32b8805407555185d00aec0.jpg)
NOTE:

The red ejector latch lock must be depressed before the module can be uninstalled.

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# 3 Operations

This chapter contains information regarding analog input, analog output, triggering and timing for the PXIe-9848, as well as data transfer and multiple module synchronization functions.

# 3.1 Functional Block Diagram

![This diagram illustrates a signal processing architecture, likely for a data acquisition system. The flow moves generally from left to right.\n\n**Input Stage (Left):**\n*   **Inputs:** Eight channels labeled **CH0** through **CH7** feed into the first stage.\n*   **Signal Chain:** These inputs enter a block labeled **JFET OP Buffer** (which contains smaller triangles labeled **BLK**).\n*   **Amplification:** The signal then passes through a **High Speed VGA** block (containing triangles labeled **VGA**).\n*   **Digitization:** The signal enters a block labeled **Quad 14bit 100MSps ADC** (containing trapezoids labeled **ADC**).\n*   **Secondary Chain:** Below this, a second set of inputs (**CH4** through **CH7**) mirrors the process through another **JFET OP Buffer**, **High Speed VGA**, and a **Quad 14bit 1000Sps ADC**.\n*   **Calibration:** A block labeled **Reference & Calibration** is connected to the upper signal chain.\n*   **Trigger:** An input labeled **TRG IN** feeds into an **Input Control** block.\n\n**Clock and Power (Center/Bottom):**\n*   A block labeled **PLL CLK Synthesizer** generates a signal labeled **CLK100pin** and connects to a line labeled **PXI CLK10**.\n*   A block labeled **DC-DC, LDO** provides power connections labeled **3.3V, 5V, 12V**.\n\n**Processing and Interface (Right):**\n*   **Board Interface:** The ADC outputs connect to a thick black bar labeled **Board to Board Conn x2**. Bidirectional arrows connect the ADCs to this bus, labeled **8-bit / 200MHz** and **SPI**.\n*   **FPGA:** The **Board to Board Conn x2** connects to a large block labeled **FPGA**. Inside the FPGA are three sub-blocks:\n    *   **PCIe Controller**\n    *   **ADC Control Trigger Control Data Processing**\n    *   **DDR2 512MB Memory**\n*   **Peripheral Slot:** The FPGA connects to a thick black bar on the far right labeled **PXIe Hybrid Peripheral Slot**.\n    *   The connection is labeled **PCIe Gen1 x4**.\n    *   The **Input Control** block connects to the FPGA.\n    *   The **PLL CLK Synthesizer** connects to the FPGA via **PXI CLK10**.\n    *   The **Board to Board Conn x2** connects to the slot via an **ADC BUS** line and power lines labeled **3.3V, 5V, 12V**.\n*   **External Connectors:** The **PXIe Hybrid Peripheral Slot** connects to two small blocks labeled **XJ4** and **XJ3**. Lines connecting them include **PXI_CLK10**, **Geographical Address (5:4)**, **Trigger Bus (3:0)**, **PXI_STAR**, **PXI_CLK100**, and **PXIe_DATA8Byte**.](.pxie-9848-50-17040-1010-201-en/c6923f0a4d76b4619feb10cf0b457a384502c3d07a5494d027a600d959e1744b.jpg)

# 3.2 Analog Input Channel

# 3.2.1 Analog Input Front-End Configuration

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   CH0\n*   Relay (appears four times)\n*   50ohm\n*   1Gohm\n*   1Mohm\n*   JFET OP Buffer\n*   High Speed VGA\n*   Quad 14bit 100MSps ADC\n*   Board to Board Bus\n*   +2.5V Reference & Calibration\n*   CLK GEN AD9523\n*   10 MHz\n\n**Connections:**\n*   **CH0** connects to the first **Relay**.\n*   The first **Relay** connects to a second **Relay** (depicted as a vertical switch).\n*   The second **Relay** connects to a **50ohm** resistor (connected to ground).\n*   The second **Relay** connects via a capacitor symbol to a third **Relay** (depicted as a horizontal switch).\n*   The third **Relay** connects to a **1Gohm** resistor (connected to ground).\n*   The third **Relay** connects to a **1Mohm** resistor (connected to ground).\n*   The third **Relay** connects to the **JFET OP Buffer**.\n*   The **JFET OP Buffer** connects to the **High Speed VGA**.\n*   The **High Speed VGA** connects to a **Relay** (depicted as a variable resistor symbol).\n*   This **Relay** connects to the **Quad 14bit 100MSps ADC**.\n*   The **Quad 14bit 100MSps ADC** connects to the **Board to Board Bus**.\n*   The **10 MHz** block connects to the **CLK GEN AD9523**.\n*   The **CLK GEN AD9523** connects to the **Quad 14bit 100MSps ADC**.\n*   The **CLK GEN AD9523** and the **+2.5V Reference & Calibration** blocks connect to the first **Relay**.](.pxie-9848-50-17040-1010-201-en/f2360dd9eb93b8e0efcf0975d69375a3da46cdc17dd202f5a1d0013af701645a.jpg)

Figure 3-1: Analog Input Architecture of the PXIe-9848

As shown, in the signal channel analog input path of a digitizer, each path provides 50 Ω input impedance or high impedance and DC couple or AC couple. The gain amplifier is optimized for each input range with low noise and high dynamic range. An anti-aliasing filter with a choice of 100MHz or 20MHz further eliminates high frequency noise. The 14-bit ADC provides not only accurate DC performance but also high signal-to-noise ratio and high non-spurious dynamic range.

For auto-calibration, internal calibration provides stable and accurate reference voltage to the AI.

# Input Impedance Configuration

When acquiring high frequency signals (of at least MHz frequency), to prevent reflection from the line, set “Characteristic Impedance” to equal 50Ω from the signal source, such as a high speed function generator, transmission line, such as a coaxial cable, to the digitizer input. For this application, 50Ω impedance switch is provided, matching the Characteristic Impedance from the connector, PCB trace and input of the gain amplifier equaling 50Ω.

If the signal source is not terminated with low impedance and the transmission line is short, PXIe-9848 provides overall high impedance of $1\mathrm{M}\Omega$ .

# AC and DC Input Coupling

With DC coupling, DC offset present in the input signal is passed to ADC, and is indicated if the signal source has a low level of offset voltage or if DC content of the signal is important.

In AC coupling, the DC offset present in the input signal is erased, and is indicated if the DC content of the input signals is to be rejected. AC coupling enables a high pass R-C filter through the input signal path. Corner frequency (-3dB) is about 10Hz.

# 100MHz and 20MHz Bandwidth

For applications that require lower bandwidth for low frequency input signals, PXIe-9848 provides a bandwidth limit of 20MHz to eliminate high frequency noise and raise the SNR ratio.

# 3.2.2 Input Range and Data Format

A/D acquisition is initiated by a trigger source, which must be predetermined. Data acquisition will commence once the trigger condition is established. Following completion of A/D conversion, A/D data is buffered in a Data FIFO, and can then be transferred to PC memory for further processing.

Data format of the PXIe-9848 is 2's complement. The ADC data of the PXIe-9848 is on the 14 MSB of the 16-bit A/D data. The 2 LSB of the 16-bit A/D data should be truncated by software. A/D data structure is as follows.

<table><tr><td>D15</td><td>D14</td><td>D13</td><td>D12</td><td>....</td><td>D3</td><td>D2</td><td>D1</td><td>D0</td></tr><tr><td colspan="9">D15 ~ D2 bits represent the data from ADC CHx (2&#x27;s complement)D1, D0 bits are identical to D2 bit and should be truncated.</td></tr></table>

Table 3-1: Input Range and Data Format

<table><tr><td>Description</td><td>Full-scale range</td><td>Least significant bit</td><td>FSR-1LSB</td><td>-FSR</td></tr><tr><td rowspan="2">Bipolar Analog Input</td><td>±2 V</td><td>244.14 μV</td><td>1.999756 V</td><td>-2 V</td></tr><tr><td>±0.2V</td><td>24.41 μV</td><td>0.199975 V</td><td>-0.2 V</td></tr><tr><td>Digital Code</td><td>N/A</td><td>N/A</td><td>7FFF</td><td>8000</td></tr></table>

Table 3-2: Input Range FSR and -FSR Values

<table><tr><td>Description</td><td>Midscale +1LSB</td><td>Midscale</td><td>Midscale -1LSB</td></tr><tr><td rowspan="2">Bipolar Analog Input</td><td>244μV</td><td>0 V</td><td>-244μV</td></tr><tr><td>24.41 μV</td><td>0 V</td><td>-24.41 μV</td></tr><tr><td>Digital Code</td><td>0001</td><td>0000</td><td>FFFF</td></tr></table>

Table 3-3: Input Range Midscale Values

# 3.2.3 FIFO and DMA Transfer For Analog Input

# FIFO

One FIFO is implemented on the PXIe-9848 for analog input data storage. FIFO depth is 32M samples/ per channel and is not shared between all AI channels.

# Bus-Mastering DMA Data Transfer

PCI Express offers dedicated bandwidth of up to 250MB/s. Unlike the PCI bus, having parallel bus architecture dividing bandwidth among all devices on the bus, PCI Express features peer-to-peer architecture with dedicated data pipelining. Data can be transferred at 2.5Gb/s, which enables a theoretical 250MB/s bandwidth per lane. With PCI Express, data bandwidth is dramatically improved compared to the PCI bus, allowing data to be streamed to the system faster with minimum onboard memory required.

One of the most important features of the PXIe-9848 is the PCI Express Gen 1 x 4 interface. The PXIe-9848 is equipped with eight 100MS/s high sampling rate ADCs, generating data rates up to 1.6 GByte/s. When streaming this data from ADCs to system memory, bandwidth remains insufficient. Data bandwidth is 1.6 GByte/s while the PCI Express Gen 1 X4 is only up to 1 GByte/s. Reducing the number of acquired channels or decreasing the sampling rate enables unlimited streaming, making it useful to have a high bandwidth bus interface when streaming data from ADC to system memory.

Actual data throughput for a PC system depends on system topology, data transfer between other devices in the system, and other components in the system. For example, data transfer between digitizers and host memory usually travels through a PCIe switch before transfer to the host system. All digitizers share the bandwidth available on the link between PCIe switch and the host system.

To provide efficient data transfer, a PCI bus-mastering DMA is essential for continuous data streaming, as it helps to achieve full potential PCI Express bus bandwidth. The bus-mastering controller releases the burden on the host CPU since data is directly transferred to the host memory without intervention. Once analog input operation begins, the DMA returns control of the program. During DMA transfer, the hardware temporarily stores acquired data in the onboard AD Data FIFO, and then transfers the data to a user-defined DMA buffer in the computer.

Using a high-level programming library for high speed DMA data acquisition, the sampling period and the number of conversions needs simply to be assigned into specified counters. After the AD trigger condition is met, the data will be transferred to the system memory by the bus-mastering DMA.

In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult to allocate a large continuous memory block. Therefore, the bus controller provides DMA transfer with scatter-gather function to link non-contiguous memory blocks into a linked list enabling transfer of large amounts of data without memory limitations. In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8 MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size aside from the physical storage capacity of the system.

Users can also link descriptor nodes circularly to achieve a multi-buffered DMA. In the following linked list, comprising three DMA descriptors, each descriptor contains a PCI address, PCI dual address, transfer size, and pointer to the next descriptor.

PCI address and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of address space.

![Based on the provided image, here is the accurate and concise description of the flowchart:\n\n**Labeled Blocks:**\n*   **Local Memory (FIFO)**\n*   **PCI Express Bus**\n*   **Left Column:** First PCI Address, First Dual Address, Transfer Size, Next Descriptor\n*   **Middle Column:** PCI Address, Dual Address, Transfer Size, Next Descriptor\n*   **Right Column:** PCI Address, Dual Address, Transfer Size, Next Descriptor\n\n**Connections:**\n*   An arrow points upward from **Local Memory (FIFO)** to **PCI Express Bus**.\n*   An arrow points upward from **PCI Express Bus** to the **Middle Column**.\n*   An arrow points from the **Left Column** to the **Middle Column**.\n*   An arrow points from the **Middle Column** to the **Right Column**.](.pxie-9848-50-17040-1010-201-en/6a902e93e9907ce30992bb7c106e48789fb7419f9d41003deeb1c0caeeae5b17.jpg)

Figure 3-2: Linked List of PCI Address DMA Descriptors

# 3.3 Trigger Source and Trigger Modes

This section details PXIe-9848 triggering operations. All eight AI channels share the same trigger source. Each of five types of trigger source cooperates with five trigger modes to accommodate various data acquisition applications. For more details on programming the PXIe-9848, please refer to the software operation manual.

# 3.3.1 Trigger Sources

![Based on the provided flowchart, here is the accurate description of the labeled blocks and their connections:\n\n**Labeled Blocks:**\n*   TRG IN SMB Connector\n*   Analog Trigger Selection\n*   Trigger Source Mux\n*   Trigger Decision\n*   Trigger Output Mux\n*   PXI Interface (indicated by vertical double-headed arrows on the far left and far right)\n\n**Connections:**\n1.  **Inputs to the Trigger Source Mux:**\n    *   'TRG IN SMB Connector' connects via 'Digital Trigger Input'.\n    *   'Software Trigger' connects directly.\n    *   'Analog Trigger Selection' receives inputs labeled 'Analog CH0' through 'Analog CH7'. Its output, 'Analog Trigger', connects to the 'Trigger Source Mux'.\n    *   The bottom-left 'PXI Interface' provides inputs 'PXI_STAR', 'PXIe_DSTARB', and 'PXI Trigger Bus(0:7)' to the 'Trigger Source Mux'.\n2.  **Processing Path:**\n    *   The 'Trigger Source Mux' outputs to the 'Trigger Decision' block.\n    *   From 'Trigger Decision', a branch goes 'To Internal Circuit'.\n    *   The main signal continues, labeled 'SSI_TRIG1', 'SSI_TRIG2', and 'SSI_START_OP', into the 'Trigger Output Mux'.\n3.  **Final Output:**\n    *   The 'Trigger Output Mux' outputs 'PXI Trigger Bus(0:7)', which connects to the far-right 'PXI Interface'.](.pxie-9848-50-17040-1010-201-en/37edb8b24460b7851c95afb16bd6cf0e9aec5cfaa6d59561ffa0e2ffbc70d8af.jpg)

Figure 3-3: Trigger Architecture of the PXIe-9848

The PXIe-9848 requires a trigger to implement acquisition of data. Configuration of triggers requires identification of trigger source. The PXIe-9848 supports internal software trigger, external digital trigger, PXI\_STAR trigger, PXI Express STAR trigger (PXIe\_DSTARB), and PXI Trigger Bus [0.7].

# Software Trigger

The software trigger, generated by software command, is asserted immediately following execution of specified function calls to begin the operation.

# External Digital Trigger

An external digital trigger is generated when a TTL edge or equivalent wave slope is detected at the SMB connector on the front panel. As shown, trigger polarity can be selected by software. Note that minimum TTL pulse width is 20 ns and maximum input wave frequency is 25 MHz.

![The image displays two side-by-side diagrams illustrating trigger events using square wave pulses.\n\nOn the left, a square wave pulse is shown with an upward-pointing arrow on the rising edge and a horizontal double-headed arrow indicating the pulse duration. The text above reads 'Pulse Width ) 20ns' and the text below reads 'Rising Edge Trigger Event'.\n\nOn the right, a similar square wave pulse is shown with a downward-pointing arrow on the falling edge and a horizontal double-headed arrow indicating the pulse duration. The text above reads 'Pulse Width ) 20ns' and the text below reads 'Falling Edge Trigger Event'.](.pxie-9848-50-17040-1010-201-en/f573f64d3e0a90d04b9af6c00f764011544314a4791cd03253a5db73cba6c28e.jpg)
Figure 3-4: External Digital Trigger

Signal level of the external digital trigger signal can be configured by onboard potentiometer as follows. The adjustable range is 0.8mV to 3.3V and the adjustable step 0.8mV (3.3V with 12bit resolution). The default voltage level is 1.67V.

![Based on the provided block diagram, here is the accurate and concise description of the labeled blocks and connections:\n\n**Labeled Blocks and Inputs:**\n*   On the far left, a square wave and a sine wave are separated by the text **'OR'**, indicating input signal types.\n*   A connector labeled **'Trigger IN'**.\n*   A rectangular block labeled **'Protection Circuit'**.\n*   A DC voltage source labeled **'3.3VDC'**.\n*   A triangle component (containing a resistor symbol) in the lower section.\n*   A large triangle labeled **'High Speed Comparator'**.\n*   The text **'Trigger Threshold Adjustment'** located below the lower section.\n\n**Connections:**\n*   The **'Trigger IN'** connector connects to the **'Protection Circuit'**.\n*   The output of the **'Protection Circuit'** connects to the top input of the **'High Speed Comparator'**.\n*   A line branches downward from the connection between the **'Protection Circuit'** and the **'High Speed Comparator'**. This vertical line connects to the positive terminal of the **'3.3VDC'** source and the input of the bottom triangle component.\n*   The output of the bottom triangle component connects to the bottom input of the **'High Speed Comparator'**.\n*   Both the **'3.3VDC'** source and the bottom triangle component connect to a ground symbol at the bottom.\n*   The output of the **'High Speed Comparator'** connects to a square wave waveform on the right.](.pxie-9848-50-17040-1010-201-en/b342bd50a7d9ad11e457f8cb73ff34ff7af62e2632f8dfa75be6472e5e18f4eb.jpg)

Figure 3-5: External Digital Trigger Configuration

# PXI STAR Trigger

When PXI STAR is selected as the trigger source, the PXIe-9848 accepts a TTL-compatible digital signal as a trigger signal. Triggering occurs when a rising edge or falling edge is detected at PXI STAR, with trigger polarity configurable by software. The minimum pulse width requirement of this digital trigger signal is 20 ns.

# PXle\_DSTARB Trigger

The PXIe\_DSTARB signal, a differential signal transmitted via the PXI Express Chassis backplane, distributes high-speed, high-quality trigger signals. When PXIe\_DSTARB is selected as the trigger source, the PXIe-9848 accepts a fast-switching LVDS digital signal as a trigger signal. Triggering occurs when a rising edge or falling edge is detected at PXIe\_DSTARB, with trigger polarity configurable by software, with minimum pulse width requirement of 20 ns.

# PXI Trigger Bus

The PXIe-9848 utilizes PXI Trigger Bus Numbers 0 through 7 to act as a System Synchronization Interface (SSI). With the interconnected bus provided by PXI Trigger Bus, multiple modules are easily synched. When configured as input, the PXIe-9848 serves as a slave module and can accept trigger signals from one of buses 0 through 7. When configured as output, the PXIe-9848 serves as a master module and can output trigger signals to the PXI Trigger Bus Numbers 0 through 7.

# Analog Trigger

PXle-9848 analog trigger circuitry can be configured to monitor one analog input channel from which data is acquired. Selection of an analog input channel as the analog trigger channel does not influence input channel acquisition. The analog trigger circuit generates an internal digital trigger signal based on the condition between the analog signal and the defined trigger level.

Analog trigger conditions are either positive-slope trigger, in which the trigger event occurs when the analog input signal changes from a voltage lower than the specified trigger level to a voltage exceeding the specified trigger level, or negative-slope trigger, in which the trigger event occurs when the analog input signal changes from a voltage exceeding the specified trigger level to a voltage lower than the specified trigger level.

![| Trigger Level | Event Occurrence |\n| ------------- | ---------------- |\n| Low           | Analog Signal    |\n| High          | Positive-Slope Trigger Event Occurs |\n| Mid           | Negative-Slope Trigger Event Occurs |](.pxie-9848-50-17040-1010-201-en/206c82ab47d3f320fde685cc1a858b3a3c2d87c608cc48e254be80cdd1fbeb8c.jpg)

Figure 3-6: Analog Trigger Conditions

The trigger signal can be chosen from among CH0, CH1, CH2, CH3, CH4, CH5, CH6 and CH7 while using an external analog trigger source. The trigger level can be set by software with 14-bit resolution, with characteristics as follows.

<table><tr><td>Trigger Level Setting (Hex)</td><td>Trigger Voltage (-2V to +2V)</td><td>Trigger Voltage (-0.2V to +0.2V)</td></tr><tr><td>7FFF</td><td>1.999756V</td><td>0.199975V</td></tr><tr><td>7FFE</td><td>1.999512V</td><td>0.199951V</td></tr><tr><td></td><td></td><td></td></tr><tr><td>1</td><td>244.14uV</td><td>24.41uV</td></tr><tr><td>0</td><td>0V</td><td>0V</td></tr><tr><td>FFFF</td><td>-244.14uV</td><td>-24.41uV</td></tr><tr><td></td><td></td><td></td></tr><tr><td>8001</td><td>-1.999756V</td><td>-0.199975V</td></tr><tr><td>8000</td><td>-2V</td><td>-0.2V</td></tr></table>

Table 3-4: Ideal Transfer Characteristics for Analog Triggers

# Trigger Export

The PXIe-9848 can export trigger signals to PXI Trigger Bus Numbers 0 through 7. The Trigger Bus can be programmed to output the trigger signal when the trigger source is generated by software, PXI STAR, or PXI Trigger Bus Numbers 0 through 7. The PXIe-9848 utilizes PXI Trigger Bus Numbers 0 through 7 to act as the System Synchronization Interface. When configured as the output, the PXIe-9848 serves as a master module and can output trigger signals to synchronize the slave modules. The trigger signal can be routed to any of the seven PXI Trigger Bus Numbers via software.

# 3.4 Trigger Modes

Two trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs. The following trigger mode descriptions are applied to analog input and analog output functions.

# 3.4.1 Post Trigger Mode

Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown. When the operation starts, PXIe-9848 waits for a trigger event. Once the trigger signal is received, acquisition begins. Data is generated from ADC and transferred to system memory continuously. The acquisition stops once the total data amount reaches a predefined value.

![This is a timing diagram illustrating an acquisition process.\n\n**Labeled Blocks:**\n*   **'Operation start'**\n*   **'Trigger Event Occurs Acquisition start'**\n*   **'Acquisition stop Begin to transfer data to system'**\n*   **'Time'**\n*   **'Trigger'**\n*   **'Data'**\n*   **'N samples'**\n\n**Connections and Layout:**\n*   A horizontal arrow labeled **'Time'** serves as the main axis.\n*   Three text blocks are positioned above the timeline, each with a downward-pointing arrow connecting it to a specific moment on the axis:\n    1.  The leftmost arrow points from **'Operation start'**.\n    2.  The middle arrow points from **'Trigger Event Occurs Acquisition start'**.\n    3.  The rightmost arrow points from **'Acquisition stop Begin to transfer data to system'**.\n*   Below the timeline, a row labeled **'Trigger'** displays a single positive pulse (a rectangular wave) aligned vertically with the middle arrow.\n*   Below the trigger row, a row labeled **'Data'** features a long horizontal bracket containing the text **'N samples'**. This bracket visually spans the duration starting from the trigger pulse and ending at the point indicated by the 'Acquisition stop' arrow.](.pxie-9848-50-17040-1010-201-en/2ccc4ffc5a0e67e56ff7b32438605f507f52f1d032fb1b57107d7ccd65f14548.jpg)

Figure 3-7: Post-Trigger Acquisition

# 3.4.2 Pre-trigger Mode

Collects data before the trigger event, starting once specified function calls are executed to begin the pre-trigger operation, and stopping when the trigger event occurs. If the trigger event occurs after the specified amount of data has been acquired, the system stores only data preceding the trigger event by a specified amount, as follows.

![Based on the provided image, here is the accurate description of the flowchart and its components:\n\n**Timeline and Events**\n*   A horizontal arrow pointing right is labeled **'Time'**.\n*   An arrow points to the beginning of the timeline labeled:\n    *   **'Operation start'**\n    *   **'Acquisition start'**\n*   An arrow points further along the timeline labeled:\n    *   **'Trigger Event occurs'**\n    *   **'Acquisition stop'**\n    *   **'Data transfer to system begins'**\n\n**Signals and Data**\n*   A horizontal line labeled **'Trigger'** displays a single square pulse aligned with the 'Trigger Event occurs' point on the timeline.\n*   A horizontal line labeled **'Data'** displays a long bar divided into two sections:\n    *   A white section labeled **'X samples'**.\n    *   A hatched (diagonal lines) section immediately following the white section.\n\n**Measurements and Explanations**\n*   Below the data bar, a long bracket spanning the entire length (white and hatched sections) is labeled:\n    *   **'Specified amount of data, (N samples)'**\n*   Below the data bar, a shorter bracket spanning only the white section indicates the length of the 'X samples'.\n*   At the very bottom, a text block explains the scenario:\n    *   **'X samples acquired'**\n    *   **'Despite acquired samples not reaching N, acquisition stop and X samples in memory are returned to system.'**](.pxie-9848-50-17040-1010-201-en/044568f959ef58a0aa4aa550159920a05c2c9c08549d09c85be0fde0a245ebb9.jpg)

Figure 3-8: Pre-trigger Acquisition

# 3.4.3 Middle-trigger Mode

Used to collect data before and after the trigger event. The amount of stored data before and after trigger event can be set individually (M and N samples), as follows.

![The diagram illustrates a timeline of a data acquisition process, organized into three synchronized rows:\n\n**1. Timeline (Top Row)**\nA horizontal arrow labeled **'Time'** points to the right. Three downward arrows mark specific events along this timeline:\n*   **Left:** **'Operation start'** and **'Acquisition start'**\n*   **Center:** **'Trigger Event occurs'**\n*   **Right:** **'Acquisition stop'** and **'Data transfer to system begins'**\n\n**2. Trigger (Middle Row)**\nLabeled **'Trigger'** on the left, a signal line displays a rectangular pulse. This pulse aligns vertically with the **'Trigger Event occurs'** marker above it.\n\n**3. Data (Bottom Row)**\nLabeled **'Data'** on the left, a horizontal bar represents data recording, divided into sections that align with the timeline above:\n*   The first section is a hatched/shaded region that begins at **'Acquisition start'**.\n*   The second section is labeled **'M samples'** and begins exactly when the trigger pulse starts.\n*   The third section is labeled **'N samples'** and ends at the **'Acquisition stop'** point.](.pxie-9848-50-17040-1010-201-en/455bb6d47717262af5b2252e9577f7f43e35a06abd74c82056671fa7bad40bc0.jpg)

Figure 3-9: Middle-trigger Acquisition

![The image shows a white document icon with a folded top-left corner. Horizontal grey lines appear near the bottom of the page, and a large red checkmark is drawn diagonally across the center.](.pxie-9848-50-17040-1010-201-en/031c903d4cee7597a0164c9c3b1974073d92a38f6ac0d3b412cbf19350c53f5d.jpg)
NOTE:

Trigger events can only be accepted when the specified amount of data has been acquired (M samples) since operation start. If the sampled data is insufficient, the trigger event will be ignored.

# 3.4.4 Delayed Trigger Mode

Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown. When PXIe-9848 receives a trigger event, a time delay is implemented before commencing acquisition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of TIMEBASE X ( $2^{32}$ ), and the minimum is the Timebase period.

![This diagram illustrates a timeline of events and corresponding signal waveforms.\n\n**Timeline and Events:**\n*   A horizontal arrow pointing right serves as the axis, labeled **'Time'**.\n*   Four downward-pointing arrows mark specific moments on the timeline in chronological order:\n    1.  **'Operation start'**\n    2.  **'Trigger Event Occurs'**\n    3.  **'Acquisition start'**\n    4.  **'Acquisition stop'**\n*   Connecting the 'Trigger Event Occurs' point to the 'Acquisition start' point is a horizontal line segment labeled **'Delay Time'**.\n\n**Signal Waveforms:**\n*   Below the timeline, a row labeled **'Trigger'** displays a signal line featuring a single rectangular pulse (a short spike) that aligns vertically with the 'Trigger Event Occurs' timestamp.\n*   Below the trigger row, a row labeled **'Data'** displays a signal line. A large bracket highlights a specific segment of this line, aligned vertically with the period between 'Acquisition start' and 'Acquisition stop'. Inside this bracket is the text **'N samples'**.](.pxie-9848-50-17040-1010-201-en/30ec8fddb6e09e7f78ef766efc9bd904958d18c1eb6ac38e7faa6ebbd6fc2f45.jpg)

Figure 3-10: Delayed Trigger Mode Acquisition

# 3.4.5 Post-Trigger or Delayed-Trigger Acquisition with Re-Triggering

Post-trigger or delayed trigger acquisition with re-triggering are applicable to collect data after several trigger events, as shown. Once the number of triggers has been programmed, the digitizer acquires a specific data sample each time a trigger is accepted. The time between a previous sample and subsequent trigger event can only be one Timebase clock period. Following initial setup, the process requires no additional software intervention.

![This is a timing diagram illustrating the synchronization of events, triggers, and data collection.\n\n**Top Section (Timeline):**\n*   A horizontal arrow pointing right represents the axis labeled **'Time'**.\n*   Three vertical arrows point down to this axis, labeled:\n    *   **'Operation start'**\n    *   **'1st Trigger Event Occurs'**\n    *   **'2nd Trigger Event Occurs'**\n\n**Middle Section (Trigger):**\n*   Labeled **'Trigger'** on the left, this row shows two rectangular pulses (high signals).\n*   The first pulse aligns vertically with the **'1st Trigger Event Occurs'** arrow.\n*   The second pulse aligns vertically with the **'2nd Trigger Event Occurs'** arrow.\n\n**Bottom Section (Data):**\n*   Labeled **'Data'** on the left, this row shows two elongated blocks (resembling hexagons).\n*   Both blocks are labeled **'N samples'**.\n*   The first block begins aligned with the first trigger pulse.\n*   The second block begins aligned with the second trigger pulse.](.pxie-9848-50-17040-1010-201-en/f097ecf9539b552b9719db4b0f93d4978352546c69188e7b0a373d4d8c0ce408.jpg)

Figure 3-11: Re-Trigger Mode Acquisition

# 3.5 ADC Timing Control

# 3.5.1 Timebase Architecture

![This block diagram illustrates a clock signal processing chain with the following labeled blocks and connections:\n\n**Labeled Blocks:**\n*   **PXIe Interface** (represented as a vertical double-headed arrow)\n*   **Onboard Oscillator 10M** (rounded rectangle)\n*   **Timebase Clock Switch** (trapezoidal shape)\n*   **Multiplier PLL Synthesizer** (square)\n*   **VCXO 100M** (rounded rectangle)\n*   **ADC0** and **ADC1** (text labels)\n\n**Connections:**\n*   Signals labeled **PXIe_CLK100** and **PXI_CLK10** originate from the **PXIe Interface** and connect to the **Timebase Clock Switch**.\n*   The **Onboard Oscillator 10M** connects to the **Timebase Clock Switch**.\n*   An arrow connects the **Timebase Clock Switch** to the **Multiplier PLL Synthesizer**.\n*   Bidirectional arrows (one pointing up, one pointing down) connect the **Multiplier PLL Synthesizer** and the **VCXO 100M**.\n*   Arrows extend from the right side of the **Multiplier PLL Synthesizer** to the outputs labeled **ADC0** and **ADC1**.](.pxie-9848-50-17040-1010-201-en/e1b5fc73831f70e4c459e2e1ece071d49555615ae9fe2f42a6c70e58be857870.jpg)

Figure 3-12: PXle-9848 Timebase Architecture

The PXIe-9848 supports the following timebase sources for analog input conversion.

# Internal Oscillator

The PXIe-9848 is equipped with a stable, low jitter reference oscillator for ADCs, at 10 MHz.

# PXI\_CLK10 Clock

The PXIe-9848 can receive the timebase from the PXI\_CLK10 clock, the signal of which originates at the PXI Express chassis backplane, matched in propagation delay within 1 ns.

# PXle\_CLK100 Clock

The PXIe-9848 can receive the timebase from the PXIe\_CLK100 clock, the signal of which originates at the PXI Express chassis backplane, matched in propagation delay within 200 ps.

# 3.5.2 Basic Acquisition Timing

The PXIe-9848 commences acquisition upon receipt of a trigger event originating with software command, external digital trigger, or the PXI Trigger Bus. The Timebase is a clock provided to the ADC and acquisition engine for essential timing. The Timebase is from an onboard 100MHz oscillator. To achieve different sampling rates, a scan interval counter is used.

Using the post-trigger mode as an example, as shown, when a trigger is accepted by the digitizer, the acquisition engine commences acquisition of data from ADC, and stores the sampled data to the onboard FIFO. When FIFO is not empty, data will be transferred to system memory immediately through the DMA engine. The sampled data is generated continuously at the rising edge of Timebase according to the scan interval counter setting. When sampled data reaches a specified value, in this example 256, acquisition ends.

![The diagram illustrates a timing sequence across five vertically stacked rows.\n\n**Labeled Blocks:**\n*   **Analog signal**\n*   **TIMEBASE**\n*   **Trigger**\n*   **Acquisition In Progress**\n*   **DATA**\n*   **D1**, **D2**, **D3**, **D4**, **D253**, **D254**, **D255**, **D256** (inside hexagonal blocks)\n*   'Acquisition starts right after this clock edge' (annotation text)\n\n**Connections and Relationships:**\n*   **Analog signal** and **TIMEBASE**: The 'TIMEBASE' is a square wave where the rising edges align vertically with the black dots on the 'Analog signal' wave.\n*   **TIMEBASE** and **Trigger**: The 'Trigger' signal is a pulse that goes high during the gap in the 'TIMEBASE' signal (indicated by a series of circles 'o o o o').\n*   **TIMEBASE**, **Trigger**, and **Acquisition In Progress**: The 'Acquisition In Progress' signal goes high immediately following the first rising edge of the 'TIMEBASE' wave after the gap. An annotation points to this edge, reading: 'Acquisition starts right after this clock edge'.\n*   **Acquisition In Progress** and **DATA**: The 'DATA' row consists of a sequence of hexagonal blocks ('D1' through 'D4', followed by circles, then 'D253' through 'D256') aligned horizontally underneath the 'Acquisition In Progress' signal.](.pxie-9848-50-17040-1010-201-en/0d5afb5f98a67cbd4a38e4df310da817e3fb38897cf8dd8261c1847e5207ef30.jpg)

Trigger mode = post-trigger, DataCnt = 256, ScanIntrv = 1

Figure 3-13: Basic Digitizer Acquisition Timing

To achieve sampling rates other than 100MS/s, a number for scan interval counter needs only be specified. For example, if the scan interval counter is set as 2, the equivalent sampling rate is 100MS/s / 2 = 50MS/s. If as 3, the equivalent sampling rate is 100MS/s / 3 = 33.33MS/s, and vice versa. The scan interval counter is 16 bits in width, therefore the lowest sampling rate is 1.025KS/s (100MS/s / 65535).

![This diagram illustrates a timing sequence involving triggers, clocks, and data acquisition intervals.\n\n**Labeled Blocks and Signals:**\n*   **Trigger:** A signal line at the top showing a high pulse.\n*   **TIMEBASE:** A signal line below 'Trigger' displaying a continuous square wave clock signal.\n*   **DATA:** A vertical curly brace grouping three rows of data intervals.\n    *   **ScanIntrv = 1:** A row containing a sequence of connected hexagonal blocks labeled: **D1**, **D2**, **D3**, **D4**, **D5**, **D6**, **D7**, **D8**, **D9**, **D10**. These blocks occur sequentially during the high duration of the 'Trigger' pulse.\n    *   **ScanIntrv = 2:** A row containing a sequence of connected hexagonal blocks labeled: **D1**, **D2**, **D3**, **D4**, **D5**, **D6**. These blocks are spaced further apart than the row above.\n    *   **ScanIntrv = 3:** A row containing a sequence of connected hexagonal blocks labeled: **D1**, **D2**, **D3**, **D4**. These blocks are spaced even further apart.\n*   **Acquisition In Progress:** A signal line at the bottom.\n*   **Acquisition is initiated following this clock edge:** Blue text annotation with an arrow pointing from the 'Acquisition In Progress' line up to a specific rising edge on the 'TIMEBASE' signal.](.pxie-9848-50-17040-1010-201-en/25f90764eab00716b0e933c5f144e1688f24d3e2e2986313e76bce3fbae7b191.jpg)

Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval Counter

<table><tr><td>Counter Name</td><td>Length</td><td>Valid Value</td><td>Description</td></tr><tr><td>ScanIntrv</td><td>16-bit</td><td>1 - 65535</td><td>Timebase divider to achieve equivalent sampling rate of the digitizer, where Sampling rate = Timebase / ScanIntrv</td></tr><tr><td>DataCnt</td><td>32-bit</td><td>1 - 536870911</td><td>Specifies the amount of data to be acquired</td></tr><tr><td>trigDelayTicks</td><td>16-bit</td><td>1 -65535</td><td>Indicates time between a trigger event and commencement of acquisition. The unit of a delay count is the period of the Timebase.</td></tr><tr><td>ReTrgCnt</td><td>32-bit</td><td>1 -536870911</td><td>Enables re-trigger to accept multiple triggers. Please see Section 3.4.5: Post-Trigger or Delayed-Trigger Acquisition with Re-Triggering for more details.</td></tr></table>

Table 3-5: Counter Parameters and Description

# 4 Calibration

This chapter introduces the calibration process to minimize analog input measurement errors and analog output errors.

# 4.1 Calibration Constant

The PXIe-9848 is factory calibrated before shipment, with associated calibration constants written to the onboard EEPROM. At system boot, the PXIe-9848 driver loads these calibration constants, such that analog input path and analog output circuit errors are minimized. ADLINK provides a software API for calibrating the PXIe-9848.

The onboard EEPROM provides three banks for calibration constant storage. Bank 0, the default bank, records the factory calibrated constants, providing written protection preventing erroneous auto-calibration. Bank 1 is user-defined space, provided for storage of self-calibration constants. Upon execution of auto-calibration, the calibration constants are recorded to bank 1.

When PXIe-9848 boots, the driver accesses the calibration constants and is automatically set to hardware. The driver loads constants stored in bank 1 by default. Constants from bank 0 can be loaded, with the preferred bank designated as boot bank by software. Following re-assignment of the bank, the driver will load the desired constants on system re-boot. This setting is recorded to EEPROM and is retained until re-configuration.

# 4.2 Auto-Calibration

Because errors in measurement and outputs will vary with time and temperature, re-calibration is recommended when the module is installed. Auto-calibration can measure and minimize errors without external signal connections, reference voltages, or measurement devices.

The PXIe-9848 has an on-board calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured on the production line and recorded in the on-board EEPROM.

Before initializing auto-calibration, it is recommended to warm up the PXIe-9848 for at least 20 minutes and remove connected cables.

![The image displays a graphic icon of a white document or sheet of paper. The top-right corner is folded down. Faint gray horizontal lines run across the lower portion of the paper. A large, bold red checkmark is superimposed over the center of the document.](.pxie-9848-50-17040-1010-201-en/0f1b36c1f748d2b15cb830c115890dccf19ee5c028ba1789b48c680346897823.jpg)
NOTE:

It is not necessary to manually factor delay into applications, as the PXIe-9848 driver automatically adds the compensation time.

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
- When installing/mounting or uninstalling/removing equipment:

▷ Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);

▶ Make sure to use recommended voltage and power source settings;

▶ Always install and operate equipment near an easily accessible electrical socket-outlet;

▷ Secure the power cord (do not place any object on/over the power cord);

▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
▶ A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a standard warning symbol. It features an upright triangle with a black border. The interior of the triangle is divided into two shades of red, with a lighter red on the top half and a darker red on the bottom half. Centered within the triangle is a white exclamation point. Below the triangle is a white rectangular background containing the word 'WARNING' in black, uppercase letters.](.pxie-9848-50-17040-1010-201-en/35f196271e43c1ebe017a663f3125516de0744b274a32dc88602c7bb6719f612.jpg)

Risk of explosion if battery is replaced with an incorrect type; please dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Contact us should you require any service or assistance.

# ADLINK Technology, Inc.

Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
新北市中和區建一路 166 號 9 樓

Tel: +886-2-8226-5877

Fax: +886-2-8226-5717

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

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Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-360-0222

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# ADLINK Technology (China) Co., Ltd.

Address: 上海市浦东新区张江高科技园区芳春路 300 号 (201203)
300 Fang Chun Rd., Zhangjiang Hi-Tech Park,
Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology Beijing

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Tel: +86-10-5885-8666

Fax: +86-10-5885-8625

Email: market@adlinktech.com

# ADLINK Technology Shenzhen

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A1 栋 2 楼 C 区 (518057)

2F, C Block, Bldg. A1, Cyber-Tech Zone, Gao Xin Ave. Sec. 7, High-Tech Industrial Park S., Shenzhen, 518054 China

Tel: +86-755-2643-4858

Fax: +86-755-2664-6353

Email: market@adlinktech.com

# ADLINK Technology (Europe) GmbH

Address: Nord Carree 3, 40477 Duesseldorf, Germany

Tel: +49-211-495-5552

Fax: +49-211-495-5557

Email: emea@adlinktech.com

# ADLINK Technology, Inc. (French Liaison Office)

Address: 15 rue Emile Baudot, 91300 Massy CEDEX, France

Tel: +33 (0) 1 60 12 35 66

Fax: +33 (0) 1 60 12 35 66

Email: france@adlinktech.com

# ADLINK Technology Japan Corporation

Address: 〒101-0045 東京都千代田区神田鍛冶町 3-7-4

神田 374 ビル 4F

KANDA374 Bldg. 4F, 3-7-4 Kanda Kajicho,

Chiyoda-ku, Tokyo 101-0045, Japan

Tel: +81-3-4455-3722

Fax: +81-3-5209-6013

Email: japan@adlinktech.com

# ADLINK Technology, Inc. (Korean Liaison Office)

Address: 서울시 서초구 서초동 1675-12 모인터빌딩 8 층

8F Mointer B/D,1675-12, Seocho-Dong, Seocho-Gu,

Seoul 137-070, Korea

Tel: +82-2-2057-0565

Fax: +82-2-2057-0563

Email: korea@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd.

Address: 84 Genting Lane #07-02A, Cityneon Design Centre, Singapore 349584

Tel: +65-6844-2261

Fax: +65-6844-2263

Email: singapore@adlinktech.com

# ADLINK Technology Singapore Pte. Ltd. (Indian Liaison Office)

Address: 1st Floor, #50-56 (Between 16th/17th Cross) Margosa Plaza, Margosa Main Road, Malleswaram, Bangalore-560055, India

Tel: +91-80-65605817, +91-80-42246107

Fax: +91-80-23464606

Email: india@adlinktech.com

# ADLINK Technology, Inc. (Israeli Liaison Office)

Address: 6 Hasadna St., Kfar Saba 44424, Israel

Tel: +972-9-7446541

Fax: +972-9-7446542

Email: israel@adlinktech.com