# PXIS-2630 series

3U 8-Slot PXI Chassis and Accessories

User's Manual

@Copyright 2003 ADLINK Technology Inc. All Rights Reserved.

Manual Rev. 1.00: December 12, 2003
Part No. 50-17004-100

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Trademarks

The product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Getting Service from ADLINK

Customer Satisfaction is top priority for ADLINK TECHNOLOGY INC. If you need any help or service, please contact us.

<table><tr><td colspan="4">ADLINK TECHNOLOGY INC.</td></tr><tr><td>Web Site</td><td colspan="3">http://www.adlinktech.com</td></tr><tr><td>Sales &amp; Service</td><td colspan="3">Service@adlinktech.com</td></tr><tr><td>TEL</td><td>+886-2-82265877</td><td>FAX</td><td>+886-2-82265717</td></tr><tr><td>Address</td><td colspan="3">9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan</td></tr></table>

Please email or FAX your detailed information for prompt, satisfactory, and consistent service.

<table><tr><td colspan="4">Detailed Company Information</td></tr><tr><td>Company/Organization</td><td colspan="3"></td></tr><tr><td>Contact Person</td><td colspan="3"></td></tr><tr><td>E-mail Address</td><td colspan="3"></td></tr><tr><td>Address</td><td colspan="3"></td></tr><tr><td>Country</td><td colspan="3"></td></tr><tr><td>TEL</td><td></td><td>FAX</td><td></td></tr><tr><td>Web Site</td><td colspan="3"></td></tr><tr><td colspan="4">Questions</td></tr><tr><td>Product Model</td><td colspan="3"></td></tr><tr><td>Environment</td><td colspan="3">OS:Computer Brand:M/B: CPU:Chipset: BIOS:Video Card:NIC:Other:</td></tr><tr><td>Detail Description</td><td colspan="3"></td></tr><tr><td>Suggestions for ADLINK</td><td colspan="3"></td></tr></table>

# Table of Contents

# Introduction ...... 1

1.1 Unpacking Checklist....2
1.2 Features 2
1.3 OEM options 4

1.3.1 Backplane 4

1.3.2 Power Supply Unit.... 4

1.3.3 Chassis Color and Logo 4

# Installation....5

2.1 Power Budget Consideration.... 5
2.2 Step for Installation.... 5
2.3 System monitoring....6
2.4 Grounding on the Mounting Holes 7

# Backplane Overview....9

3.1 Interoperability with CompactPCI....9
3.2 System Controller Slot....9
3.3 Star Trigger Slot 9
3.4 Peripheral Slots.... 10
3.5 Local Bus 10
3.6 Trigger Bus 11
3.7 System Reference Clock 11

# Troubleshooting and Preventative Maintenance..... 13

4.1 Troubleshooting the PXIS-2630 series.... 13
4.2 Cleaning 14
4.2.1 Interior Cleaning.... 14
4.2.2 Exterior Cleaning.... 14
4.3 Temperature Detect 14

4.4 Fan Hot-Swap Replacement.... 14

# Specifications 17

A.1 General 17
A.2 APS-940XA PSU Specifications.... 20

# Backplane Drawing and Pin Assignments .... 23

B.1 Backplane Drawing 23
B.2 Backplane XBP-3008L Connectors Pin Assignments ..... 24
B.2.1 PXI Connectors Pin Assignments.... 24
B.2.2 Miscellaneous Connectors Pin Assignments.... 28

SAFETY INSTRUCTIONS......31

Warranty Policy....33

![1](.pxis-2630series-manual-1/174be2c1f68a11eb0fa7b01aad93097371713cc550b38ac86f886334fcd498e1.jpg)

# Introduction

ADLINK PXIS-2630 series is a 19" 3U PXI chassis providing 7 PXI peripheral slots in a system. These chassis are compliant with PXI and CompactPCI specifications. Both PXI and CompactPCI modules can be used in the chassis. Compliant with PXI specifications, the internal 10MHz reference clock is available on all of the 7 PXI slots, as well as the star trigger functions, PXI trigger bus, and PXI local bus.

The PXIS-2630 series is equipped with an industrial grade 400W ATX power supply to provide reliable and cost effective power to the system. The status of system power supply, temperature, and cooling fans are monitored by the alarm module assembled in the chassis. Once a failure is detected, a LED and buzzer will be actuated. The failure fans can be removed from the front panel and are hot swappable, which effectively reduces MTTR (Mean-Time-To-Repair).

The PXI-3710 (3-slot version, without floppy disk drive) and PXI-3710F (4-slot version, with floppy disk drive) are designed to fit in the PXIS-2630 series chassis. With its powerful design, the PXIS-2630 series chassis is ideal for high performance and medium size applications.

# 1.1 Unpacking Checklist

Check the shipping carton for any damage. If the shipping carton and contents are damaged, notify the local dealer or sales for a replacement. Retain the shipping carton and packing material for inspection by the dealer.

Check for the following items in the package. If there are any missing items, contact your local dealer or sales.

- PXIS-2630: 8-slot 3U PXI/CompactPCI instrument chassis with APS-925AX power supply unit
This User's Manual
Power Cord

Note: The package of the PXI-2630 series OEM version (non-standard configuration, functionality, or package) may vary according to custom requests. The assigned controller or peripheral modules may be pre-installed and shipped with the chassis. Please check with the dealer for more options.

# 1.2 Features

• Accepts both 3U PXI and CompactPCI modules
• One system slot and 7 PXI/CompactPCI peripheral slots
• PXI specifications Rev. 2.0 compliant
• IEEE 1101.10 mechanical packaging compliant
- Filtered, forced-air cooling
- 400W ATX power
• Temperature, voltage, and fan monitoring LED
• 4U high rackmount and benchtop installation

Figure 1-1, 1-2 show some of the feature, and components of the PXIS-2630 series chassis. Figure 1-1 shows the front view of the PXIS-2630. Figure 1-2 shows the rear view of the PXIS-2630.

![Technical diagram of an electronic device with numbered components and labeled ports](.pxis-2630series-manual-1/252a3ed0eabac10409eb4299de4921606f06801b9cc2b06241541f4051cecc74.jpg)

1. Power On/Off Switch

6. Fan LED

11. Removable Fan Cover

2. Power LED

7. Controller Expansion Slots

12. Removable Feet

3. Temp. LED

8. System Controller Slot

13. Mounting Brackets

4. Alarm LED

9. Star Trigger Slot

14. Backplane Connector

5. Alarm RST

10. Peripheral Slots

Figure 1-1 Front View of the PXIS-2630 Chassis
![Technical diagram of a mechanical or electrical enclosure with internal components and mounting brackets (no text or symbols)](.pxis-2630series-manual-1/56b9a8e4e942494d27d082eff20c6e342c7b9b1157906a866c4653561bae9dd6.jpg)

1. Power Fan

2. Universal AC Input

Figure 1-2 Rear View of the PXIS-2630 Chassis

# 1.3 OEM options

The standard PXIS-2630 series chassis includes backplanes and a power supply unit in addition to the enclosure metal parts. The following sections depict the standard parts used in the PXIS-2630 series.

# 1.3.1 Backplane

The PXIS-2630 series has 8-slot PXI backplane XBP-3008L inside. Users can choose the following power backplane to use redundant power:

- cBP-3061: Backplane for one 47-pin 3U CompactPCI modular with one ATX DC output power supply unit.
- cBP-3062A: Backplane for one 47-pin 3U CompactPCI modular with two ATX DC output power supply unit.

ADLINK provides custom design and manufacturing service. Please contact us for more details.

# 1.3.2 Power Supply Unit

PXIS-2630 series equips the APS-940XA, a 400W ATX power supply unit that is complaint with PICMG 2.11, the ATX Power Supply Specifications. Please refer to Appendix A.2 for detail specifications.

Various models that accommodate different AC or DC input are available. This makes PXIS-2630 series suitable for wide variety of applications such as telecom signal analysis and transportation computer, which require 24V/48V DC input power supply. Please contact us for other power supply options that fit your applications.

# 1.3.3 Chassis Color and Logo

The standard color of PXI-2630 series is beige. ADLINK provides custom chassis color or paint specific logo for OEMs, with minimum order requirement. Please contact us for more details.

# 2

# Installation

The chapter depicts the procedure of installation PXIS-2630 series chassis.

# 2.1 Power Budget Consideration

Prior to installing any modules into the PXIS-2630 series chassis, please calculate the system power requirement. The power budget for every DC power sources shall also be checked, including +5V, +3.3V, +12V, -12V supply rail. Please refer to Appendix A.2 for the maximum usable power.

# 2.2 Step for Installation

Follow the step to power on the chassis.

1. Make sure the power switch is in the OFF position.
2. Plug in the AC power cord.
3. Install your controller. Please check the ejector/injector handle is pushed down. Align the controller edge to the "RED" card guide, sliding in to the rear of the chassis. Push up on the ejector/injector handle to fully inject the card into the chassis. Secure the screws on the module's front panel.
4. Install peripheral modules if any.
5. Press the power switch on the front panel to power on the chassis.
6. Check the LED to make sure the power input is ready. There are four Green LED indicators (3.3V, 5V, +12V, and -12V). The four LEDs will light when power turn on. The fans should become operational as well.

Note: If the chassis does not power on, see Chapter 4, Troubleshooting and Preventative Maintenance.

# 2.3 System monitoring

There are LEDs on the front panel for system monitoring, including powers, temperature, and fans. Please refer to following for the detail meaning of display status on LEDs.

# System Monitoring

■ Power LED (Voltage : 3.3V, 5V, +12V, -12V)

○ Color: Green
- ON while supplied

■ Temperature LED

○ Color: Amber
- ON for normal condition
- Flashes if exceeds temperature

Fan LED

○ Color: Green
- ON while normal fan speed
- Flashes if abnormal fan speed

\- Alarm LED

○ Color: Red
- ON while normal condition
- Flashes if alarm occurs

The Alarm Buzzer beeps continuously if any alarm occurs. When the Alarm Buzzer beeps, users can check the LED on the front panel to find out which kind of alarm occurs.

There is a black button labeled Alarm RST near by the Alarm LED on the front panel. When the Alarm LED flashes and the Alarm Buzzer continues beeping, you can push Alarm RST button to stop beeping.

Users can further refer to Chapter 4 for Troubleshooting.

# 2.4 Grounding on the Mounting Holes

There are two kinds of grounding for the mounting holes of the backplane. The mounting holes labeled as “GND” with “circle soldering mask” connected to the logic ground plane of the backplane. The mounting holes labeled as “FGND” with “square soldering mask” not connected to the ground plane therefore providing isolation between the logic ground and the chassis ground.

The backplane is mounted on the PXIS-2630 series through all mounting holes by default, therefore the chassis ground is shorted to the logic ground. For applications that require isolation between the logic ground and the chassis ground, users can remove the screws on the GND mounting holes.

# 3

# Backplane Overview

# 3.1 Interoperability with CompactPCI

The PXIS-2630 series backplane XBP-3008L can use both PXI-compatible products and standard CompactPCI products.

The signals on the P1 connector of the backplane meet the requirements of the CompactPCI specification for both the peripheral and system modules.

The PXI-specific signals are located on P2. Only the signals that are reserved or not used in the CompactPCI 64-bit specification are found on PXI-specific signals. Therefore, all modules that meet the requirements of the CompactPCI 64-bit specification will function in the PXIS-2630 series.

# 3.2 System Controller Slot

The System Controller slot is Slot 1 of the chassis as defined by the PXI specification. It has three controller expansion slots, which are used for system controller modules that are wider than one slot. As defined in the PXI specification, these slots allow the controller to expand to the left to prevent the controller from using up peripheral slots.

# 3.3 Star Trigger Slot

The Star Trigger (ST) slot is Slot 2. This slot has a dedicated trigger line between itself and slots 3-8 is intended for modules with ST functionality that can provide individual triggers to the peripherals.

# 3.4 Peripheral Slots

There are 7 peripheral slots including the Star Trigger controller slot.

![This block diagram illustrates the trigger and bus architecture of a PXI system.\n\n**Labeled Blocks:**\n*   **Clock 10 MHz Buffer Circuitry** (Top center)\n*   **System Controller** (Far left vertical block, labeled '1')\n*   **Star Trigger Controller** (Second vertical block, labeled '2')\n*   **Peripheral slot** (Six vertical blocks labeled '3' through '8')\n*   **PXI Trigger Bus Segment and PCI Bus Segment** (Bottom horizontal bar)\n\n**Connections:**\n*   **PXI Star Triggers:** A bundle of lines labeled 'PXI Star Triggers' originates from the **Clock 10 MHz Buffer Circuitry** and connects to the **Star Trigger Controller** and all six **Peripheral slot** blocks.\n*   **System Controller to Star Trigger Controller:** Bidirectional arrows connect the **System Controller** to the **Star Trigger Controller**.\n*   **Local Connections:** Bidirectional arrows labeled 'Local' connect the **Star Trigger Controller** to the first **Peripheral slot**, and connect each adjacent **Peripheral slot** to its neighbor (e.g., slot 3 to 4, 4 to 5, etc.).\n*   **Bus Connections:** Bidirectional arrows connect the bottom of every vertical block (1 through 8) to the **PXI Trigger Bus Segment and PCI Bus Segment** at the bottom.](.pxis-2630series-manual-1/31ceff4070b72df3670422381bd931f5ed03ad2392a43bf14188ef5fbf3f1761.jpg)

Figure 3.1 PXI Local Bus and Star Trigger Routing

# 3.5 Local Bus

The local bus of PXI backplane XBP-3008L is a daisy-chained bus that connects each peripheral slot with its adjacent peripheral slots to the left and right. Each local bus is 13 lines wide and can pass analog signals between modules or provide a high-speed side-band communication path that does not affect the PXI bandwidth.

In accordance with the PXI specification, the local bus connections between all slots except slots 1 and 2.

# 3.6 Trigger Bus

ADLINK PXIS-2630 series has PXI trigger bus. Users can use triggers to synchronize the operation of several different PXI peripheral modules, or use one module to control carefully timed sequences of operations performed on other modules in the system. Modules can pass triggers to one another through trigger bus, allowing precisely timed responses to asynchronous external events the system is monitoring or controlling.

# 3.7 System Reference Clock

The PXIS-2630 series supplies the PXI 10MHz system clock signal (PXI\_CLK10) independently to every peripheral slot. An independent buffer (having a source impedance matched to the backplane and a skew of less than 1ns between slots) drives the clock signal to each peripheral slot. Users can use this common reference clock signal to synchronize multiple modules in a measurement or control system or drive PXI\_CLK10 from an external source through the PXI\_CLK10\_IN pin on the P2 connector of the star trigger slot.

Users can select the internal or external clock by setting the jumper JP2 and JP3 in the back of the backplane.

JP2 JP3: PXI Reference Clock Control

<table><tr><td>JP2</td><td>JP3</td><td>Pin 1-2</td><td>Description</td></tr><tr><td>[S26T]</td><td>[S24S]</td><td>Open JP2Short JP3</td><td>External clock through the PXI_CLK10_INon star trigger slot</td></tr><tr><td>[X3H5]</td><td>[T1H1]</td><td>Short JP2Open JP3(default)</td><td>Internal 10MHz system clock PXI_CLK10</td></tr></table>

# 4

# Troubleshooting and Preventative Maintenance

# 4.1 Troubleshooting the PXIS-2630 series

Please refer to Table 4.1 to troubleshoot the PXIS-2630 series chassis. The table lists possible causes for power failure and recommends ways to correct the problem.

Table 4.1 Troubleshooting

<table><tr><td>Possible Cause</td><td>What to Do</td></tr><tr><td>PXIS-2630 series is not connected to power source.</td><td>Make sure that the PXIS-2630 series is connected to a live electrical outlet. Try operating another piece of equipment from this outlet.</td></tr><tr><td>Power switch is not switched on.</td><td>Make sure the power switch is set to the ON position.</td></tr><tr><td>Power supply has failed.</td><td>Contact ADLINK for repair.</td></tr><tr><td>The Alarm Buzzer is beeping</td><td>Push Alarm RST button to stop beeping and refer to Chapter 2.3 to find out which alarm occurs.Temperature LED flashes:Cool down the PXIS-2630 system under 50°C.Fan LED flashes:Refer to Chapter 4.4 for the fan hot-swap replacement.</td></tr></table>

# 4.2 Cleaning

Cleaning procedures consist of two parts: interior and exterior cleaning of the chassis. Refer to your module user documentation for information about cleaning the individual CompactPCI or PXI modules.

Note: Always power-off the chassis and disconnect the power cord before cleaning of servicing the chassis.

# 4.2.1 Interior Cleaning

Use a dry, low-velocity stream of air for cleaning the interior of the chassis. Clean around components with a soft-bristle brush. If you must use a liquid for minor interior cleaning, use a 75% isopropyl alcohol solution and rinse with deionized water.

# 4.2.2 Exterior Cleaning

Use a dry lint-free cloth or a soft-bristle brush to clean the exterior surfaces of the chassis. If any dirt remains, moisten a cloth to wipe the exterior surfaces of the chassis in a mild soap solution. Wiping with a cloth moistened with clear water to remove any soap residue. Do not use abrasive compounds on any part of the chassis.

# 4.3 Temperature Detect

If the system overheats, an Amber Temp LED flashes and a buzzer beeps continuously. There are three values of temperature setting, 50°C, 60°C, and 70°C. The default is 50°C. Contact ADLINK if you need to change setting.

# 4.4 Fan Hot-Swap Replacement

There is a LED for each fan for system monitoring. When any one of the fans is defective, the corresponding LED flashes and the alarm buzzer keeps beeping. Please refer to the following for the fan hot-swap replacement.

# Fan Hot-Swap Replacement Procedure

1. Press the Alarm RST button on the front panel to stop the beeping.
2. Remove the front panel cover of fans.
3. Pull out the defective fan.
4. Replace with a new fan.
5. Cover back the fans panel cover.

# Specifications

# A.1 General

Complies with PXI specifications and accepts modules compliant with CompactPCI, PICMG 2.0 specifications.

# Electrical

AC Power Supply (Please refer to A.2 for the detail specifications)

■ APS-940 XA, ATX power supply
■ Input voltage: 90-132V $_{AC}$ or 190-260V $_{AC}$ , auto ranged
■ Input frequency: 50Hz to 60Hz ±5%
Output

Maximum usable power: 400W

<table><tr><td>VDC</td><td>Typical</td></tr><tr><td>+5V</td><td>25.0 – 30.0A</td></tr><tr><td>+12V</td><td>14A</td></tr><tr><td>-5V</td><td>1A</td></tr><tr><td>-12V</td><td>1A</td></tr><tr><td>+3.3V</td><td>20.0 - 28.0A</td></tr><tr><td>+5Vsb</td><td>1.5A</td></tr></table>

# System Monitoring

- Power LED
• Voltage : +3.3V, +5V, +12V, -12V
- Color : Green
• ON while power supplied Temperature LED
• Temperature setting: 50°C, 60°C, 70°C

• Color: Amber
• ON for normal condition
• FLASH if exceeds temperature

\- Fan LED

• Fan speed monitoring
- Color: Green
• ON while normal fan speed
• FLASH while abnormal fan speed

\- Alarm LED

- Color: Red
• ON while normal condition
• FLASH if any alarm occurs

\- Alarm Buzzer

\- Beep if any alarm occurs

\- Alarm reset button

\- Reset the alarm monitor system

# Cooling

# Fans

• Front-access hot swappable fan trays
- Five 31CFM fans trays at the bottom of the chassis
• Fan speed: 2900 ± 300RPM
• Power: 12 V $_{DC}$ @ 0.17 A each fan
- Noise: 36dB(A)
• Air filter: removable from the bottom of the chassis

# Physical

• Number of PXI/CompactPCI slots: 8 (1 controller, 7 peripherals)
• Number of controller expansion slots: 3 (left of controller slot)
- Dimensions:
○ 258mm x 448.4mm x 177.8 mm (L x W x H, w/o handle)
- Weight
○ 11 Kg

![448.4\n258\n2\nTOP VIEW\n482.6\n38.91\n177.8\nFRONT VIEW\n15.8](.pxis-2630series-manual-1/b2576a846e812bb32a1b2778cebe85958188c67f0b62dc9051d302befb7f89e0.jpg)

Figure A-1 PXIS-2630 Dimensions

# Operating Environment

• Ambient temperature range: 0 to 50°C
• Relative humidity: 10 to 90%, noncondensing

# Storage Environment Temperature

• Ambient temperature range: -20 to 70°C
• Relative humidity: 5 to 95%, noncondensing

# Backplane

• Backplane bare-board material: UL 94V-0 rated
- Backplane connectors: Conforms to IEC-917 and IEC 1076-4-101, UL 94V-0 rated

• Number of PXI/CompactPCI slots: 8 (1 controller, 7 peripherals)

# Shock and Vibration

• Shock: 15 G peak-to-peak, 11 ms duration, non-operation
• Random Vibration

○ Operating: 5 to 500 Hz, 0.5 G $_{RMS}$ , each axis

○ Nonoperating: 5 to 500 Hz, 1.88 G $_{RMS}$ , each axis

# Safety and EMC/EMI Compliance

EMC/EMI: CE, FCC Class A

# A.2 APS-940XA PSU Specifications

# AC Input Characteristics

• VOLTAGE: 90 \~ 240 VAC FULL RANGE.
• FREQUENCY: 47 \~ 63 HZ.
- INPUT CURRENT: 8.0 A (RMS) FOR 115VAC, 4.0 A (RMS) FOR 230VAC.
- INRUSH CURRENT: 65A MAX. FOR 115 VAC, 125A MAX. FOR 230 VAC.

AC Input voltage is switching automatically according to AC input voltage. The acceptable input voltage range is as following table.

<table><tr><td>Voltage</td><td>Frequency</td><td>Minimum</td><td>Maximum</td><td>Input Current</td></tr><tr><td>115 VAC</td><td>47 - 63Hz</td><td>90 VAC</td><td>130 VAC</td><td>8.0A (300W)</td></tr><tr><td>230 VAC</td><td>47 - 63Hz</td><td>180 VAC</td><td>260 VAC</td><td>4.0A (300W)</td></tr></table>

DC Output Characteristics

<table><tr><td>VDC</td><td>Minimum</td><td>Maximum</td><td>Ripple and Noise Max</td><td>Load Regulation</td><td>Line Regulation</td></tr><tr><td>+5V</td><td>3.0A</td><td>35A</td><td>50mV</td><td>±5%</td><td>±1%</td></tr><tr><td>+12V</td><td>2.0A</td><td>30A</td><td>120mV</td><td>+7%/-5%</td><td>±1%</td></tr><tr><td>-5V</td><td>0A</td><td>0.8A</td><td>150mV</td><td>±5%</td><td>±1%</td></tr><tr><td>-12V</td><td>0A</td><td>1.0A</td><td>150mV</td><td>±5%</td><td>±1%</td></tr><tr><td>+3.3V</td><td>1.0A</td><td>25A</td><td>50mV</td><td>±5%</td><td>±1%</td></tr><tr><td>+5Vsb</td><td>0.1A</td><td>2A</td><td>50mV</td><td>±5%</td><td>±1%</td></tr></table>

REMARK: THE OUTPUT CURRENT OF 5V & 3.3V SHOULD NOT EXCEED 45A.

# SPECIFICATIONS:

• Temperature range: Operating 0°C to 40°C.
- Hold up time: 16ms MINIMUM at full load & normal input voltage.
- Dielectric Withstand: Input / Output 1500 VAC for 1 second. Input to Frame Ground 1500 VAC for 1 second.
• Efficiency: 68% Typical.
• Power good signal: ON DELAY 100 ms to 500 ms, OFF DELAY 1 ms.
• Over load protection: 130 +/- 20%.
• Over voltage protection: +5V → 5.7V \~ 6.5V, 3.3V → 3.9 \~ 4.3V, 12V → 13.6 \~ 15V.
• Short circuit protection: +5V, -5V, +12V, -12V, +3.3V.
• EMI noise filter: FCC Class B, CISPR22 Class B.
• Safety: UL 1950, CSA 22.2 NO/ 950, TÜV IEC 950.
- Remote ON / OFF control. The unit shall accept a logic open collector level which will disable/enable all output voltages (exclude +5V standby), As logic level is low, outputs voltage were enable, as logic level is high, outputs voltage was disable.
• 3.3V/5V Remote Sensing.
• Cooling: one 80mm ball bearing DC FAN.
• Dimension: 140 (D) x150 (W) x 86 (H) mm (PS/2).
• Active power factor correction meets IEC-1000-3-2 Class D.
- Advance thermal & acoustics control features.

![B](.pxis-2630series-manual-1/c74668bd40d747c80505cfd462d66e145d40fdde1f9e099f87befa2d74a82361.jpg)

# Backplane Drawing and Pin Assignments

# B.1 Backplane Drawing

The following figures show the two parts of the backplanes and Mechanical Drawing.

![Diagram showing geometric shapes (triangle, diamond, circle) above vertical bars with circles below, likely representing a pattern or counting system.](.pxis-2630series-manual-1/056b9bb041ad84711635549198097f8b497384e01e04e76279bfeebc7aa91f30.jpg)

Figure A.1 XBP-3008L front view Drawing

![Based on the visual elements of the diagram, here is the description:\n\n**Top Row:** A sequence of seven circles, followed by a diamond shape inside a square, followed by a single circle.\n\n**Central Area:** Eight vertical rectangular blocks with dashed borders arranged in a row. Each block is divided horizontally near the middle.\n\n**Right Sidebar:** A vertical stack of elements including:\n*   A horizontal rectangle divided into three segments.\n*   Three circles stacked vertically.\n*   Three squares stacked vertically.\n*   A grid of twelve small squares (arranged 3 columns by 4 rows).\n\n**Bottom Row:** Five circles arranged horizontally.\n\n**Connections:** There are no explicit connecting lines. The elements are arranged in a grid-like layout suggesting a channel strip interface, where the top row elements correspond to the vertical columns, the right sidebar acts as a master section, and the bottom row elements align with the lower section of the central columns.](.pxis-2630series-manual-1/a941c3259e0e8f8908978c62f961377eb7ce443ac5094ef40e3c46a21bfd1942.jpg)

Figure A.2 XBP-3008L rear view Drawing

# B.2 Backplane XBP-3008L Connectors Pin Assignments

# B.2.1 PXI Connectors Pin Assignments

System Slot (Slot #1) P1 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>+5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>AD[4]</td><td>AD[3]</td><td>+5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>+3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>AD[9]</td><td>AD[8]</td><td>GND</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>+3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>GND</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td> $\text{REQ\#}^{(1)}$ </td><td>GND</td><td>+3.3V</td><td> $\text{CLK}^{(1)}$ </td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>PCIRST#</td><td>GND</td><td> $\text{GNT\#}^{(1)}$ </td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>GND</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td> $\text{INTA\#}^{(1)}$ </td><td> $\text{INTB\#}^{(1)}$ </td><td> $\text{INTC\#}^{(1)}$ </td><td>+5V</td><td> $\text{INTD\#}^{(1)}$ </td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>+5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

System Slot (Slot #1) P2 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>PXI_BRSVA22</td><td>PXI_BRSVB22</td><td>PXI_BRSVC22</td><td>PXI_BRSVD22</td><td>PXI_BRSVE22</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>CLK6</td><td>GND</td><td>NC</td><td>NC</td><td>NC</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>CLK5</td><td>GND</td><td>NC</td><td>GND</td><td>NC</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>GND</td><td>GND</td><td>SMBDATA</td><td>SMBCLK</td><td>SMBALERT-</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>PRST#</td><td>REQ6#</td><td>GNT6#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>DEG#</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>FAL#</td><td>REQ5#</td><td>GNT5#</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]\#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]\#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]\#</td><td>GND</td><td>C/BE[6]\#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>CLK4</td><td>GND</td><td>GNT3#</td><td>REQ4#</td><td>GNT4#</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>CLK2</td><td>CLK3</td><td>GND (SYS#)</td><td>GNT2#</td><td>REQ3#</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>CLK1</td><td>GND</td><td>REQ1#</td><td>GNT1#</td><td>REQ2#</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Star Trigger Slot (Slot #2) P1 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>+5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>AD[4]</td><td>AD[3]</td><td>+5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>+3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>+3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL(1)</td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ#(1)</td><td>GND</td><td>+3.3V</td><td>CLK(1)</td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>PCIRST#</td><td>GND</td><td>GNT#(1)</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>GND</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA#(1)</td><td>INTB#(1)</td><td>INTC#(1)</td><td>+5V</td><td>INTD#(1)</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>+5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Star Trigger Slot (Slot #2) P2 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>PXI_BRSVA22</td><td>PXI_BRSVB22</td><td>PXI_BRSVC22</td><td>PXI_BRSVD22</td><td>PXI_BRSVE22</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>GND</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td> $PXI\_STAR0^{(2)}$ </td><td>GND</td><td> $PXI\_STAR1^{(2)}$ </td><td>GND</td></tr><tr><td>19</td><td>GND</td><td> $PXI\_STAR2^{(2)}$ </td><td>GND</td><td> $PXI\_STAR3^{(2)}$ </td><td>PXI_STAR4</td><td>PXI_STAR5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>N/C</td><td>PXI_CLK10_IN</td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>N/C</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>N/C</td><td>PXI_STAR6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]\#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]\#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]\#</td><td>GND</td><td>C/BE[6]\#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>N.C (SYS\#)</td><td>PXI_STAR7</td><td>PXI_STAR8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_STAR9</td><td>GND</td><td>PXI_STAR10</td><td>PXI_STAR11</td><td>PXI_STAR12</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

General Peripheral Slot (Slot #3\~#6) P1 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>25</td><td>GND</td><td>+5V</td><td>REQ64#</td><td>ENUM#</td><td>+3.3V</td><td>+5V</td><td>GND</td></tr><tr><td>24</td><td>GND</td><td>AD[1]</td><td>+5V</td><td>V(I/O)</td><td>AD[0]</td><td>ACK64#</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>+3.3V</td><td>AD[4]</td><td>AD[3]</td><td>+5V</td><td>AD[2]</td><td>GND</td></tr><tr><td>22</td><td>GND</td><td>AD[7]</td><td>GND</td><td>+3.3V</td><td>AD[6]</td><td>AD[5]</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>+3.3V</td><td>AD[9]</td><td>AD[8]</td><td>M66EN</td><td>C/BE[0]#</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>AD[12]</td><td>GND</td><td>V(I/O)</td><td>AD[11]</td><td>AD[10]</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>+3.3V</td><td>AD[15]</td><td>AD[14]</td><td>GND</td><td>AD[13]</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>SERR#</td><td>GND</td><td>+3.3V</td><td>PAR</td><td>C/BE[1]#</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>+3.3V</td><td>IPMB_SCL</td><td>IPMB_SDA</td><td>GND</td><td>PERR#</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>DEVSEL#</td><td>GND</td><td>V(I/O)</td><td>STOP#</td><td>LOCK#</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>+3.3V</td><td>FRAME#</td><td>IRDY#</td><td>GND</td><td>TRDY#</td><td>GND</td></tr><tr><td>12-14</td><td colspan="7">Key</td></tr><tr><td>11</td><td>GND</td><td>AD[18]</td><td>AD[17]</td><td>AD[16]</td><td>GND</td><td>C/BE[2]#</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[21]</td><td>GND</td><td>+3.3V</td><td>AD[20]</td><td>AD[19]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>C/BE[3]#</td><td>IDSEL $^{(1)}$ </td><td>AD[23]</td><td>GND</td><td>AD[22]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[26]</td><td>GND</td><td>V(I/O)</td><td>AD[25]</td><td>AD[24]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[30]</td><td>AD[29]</td><td>AD[28]</td><td>GND</td><td>AD[27]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>REQ# $^{(1)}$ </td><td>GND</td><td>+3.3V</td><td>CLK $^{(1)}$ </td><td>AD[31]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>BRSVP1A5</td><td>BRSVP1B5</td><td>PCIRST#</td><td>GND</td><td>GNT# $^{(1)}$ </td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>IPMB_PWR</td><td>GND</td><td>V(I/O)</td><td>INTP</td><td>INTS</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>INTA# $^{(1)}$ </td><td>INTB# $^{(1)}$ </td><td>INTC# $^{(1)}$ </td><td>+5V</td><td>INTD# $^{(1)}$ </td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>TCK</td><td>+5V</td><td>TMS</td><td>TDO</td><td>TDI</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>+5V</td><td>-12V</td><td>TRST#</td><td>+12V</td><td>+5V</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

General Peripheral Slot (Slot #3\~#6) P2 Pin Assignment

<table><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>22</td><td>GND</td><td>PXI_BRSVA22</td><td>PXI_BRSVB22</td><td>PXI_BRSVC22</td><td>PXI_BRSVD22</td><td>PXI_BRSVE22</td><td>GND</td></tr><tr><td>21</td><td>GND</td><td>PXI_LBR0</td><td>GND</td><td>PXI_LBR1</td><td>PXI_LBR2</td><td>PXI_LBR3</td><td>GND</td></tr><tr><td>20</td><td>GND</td><td>PXI_LBR4</td><td>PXI_LBR5</td><td>PXI_LBL0</td><td>GND</td><td>PXI_LBL1</td><td>GND</td></tr><tr><td>19</td><td>GND</td><td>PXI_LBL2</td><td>GND</td><td>PXI_LBL3</td><td>PXI_LBL4</td><td>PXI_LBL5</td><td>GND</td></tr><tr><td>18</td><td>GND</td><td>PXI_TRIG3</td><td>PXI_TRIG4</td><td>PXI_TRIG5</td><td>GND</td><td>PXI_TRIG6</td><td>GND</td></tr><tr><td>17</td><td>GND</td><td>PXI_TRIG2</td><td>GND</td><td>N/C</td><td> $PXI\_STAR^{(2)}$ </td><td>PXI_CLK10</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>PXI_TRIG1</td><td>PXI_TRIG0</td><td>N/C</td><td>GND</td><td>PXI_TRIG7</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>PXI_BRSVA15</td><td>GND</td><td>N/C</td><td>PXI_LBL6</td><td>PXI_LBR6</td><td>GND</td></tr><tr><td>14</td><td>GND</td><td>AD[35]</td><td>AD[34]</td><td>AD[33]</td><td>GND</td><td>AD[32]</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>AD[38]</td><td>GND</td><td>V(I/O)</td><td>AD[37]</td><td>AD[36]</td><td>GND</td></tr><tr><td>12</td><td>GND</td><td>AD[42]</td><td>AD[41]</td><td>AD[40]</td><td>GND</td><td>AD[39]</td><td>GND</td></tr><tr><td>11</td><td>GND</td><td>AD[45]</td><td>GND</td><td>V(I/O)</td><td>AD[44]</td><td>AD[43]</td><td>GND</td></tr><tr><td>10</td><td>GND</td><td>AD[49]</td><td>AD[48]</td><td>AD[47]</td><td>GND</td><td>AD[46]</td><td>GND</td></tr><tr><td>9</td><td>GND</td><td>AD[52]</td><td>GND</td><td>V(I/O)</td><td>AD[51]</td><td>AD[50]</td><td>GND</td></tr><tr><td>8</td><td>GND</td><td>AD[56]</td><td>AD[55]</td><td>AD[54]</td><td>GND</td><td>AD[53]</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>AD[59]</td><td>GND</td><td>V(I/O)</td><td>AD[58]</td><td>AD[57]</td><td>GND</td></tr><tr><td>6</td><td>GND</td><td>AD[63]</td><td>AD[62]</td><td>AD[61]</td><td>GND</td><td>AD[60]</td><td>GND</td></tr><tr><td>5</td><td>GND</td><td>C/BE[5]\#</td><td>GND</td><td>V(I/O)</td><td>C/BE[4]\#</td><td>PAR64</td><td>GND</td></tr><tr><td>4</td><td>GND</td><td>V(I/O)</td><td>PXI_BRSVB4</td><td>C/BE[7]\#</td><td>GND</td><td>C/BE[6]\#</td><td>GND</td></tr><tr><td>3</td><td>GND</td><td>PXI_LBR7</td><td>GND</td><td>PXI_LBR8</td><td>PXI_LBR9</td><td>PXI_LBR10</td><td>GND</td></tr><tr><td>2</td><td>GND</td><td>PXI_LBR11</td><td>PXI_LBR12</td><td>N/C (SYS\#)</td><td>PXI_LBL7</td><td>PXI_LBL8</td><td>GND</td></tr><tr><td>1</td><td>GND</td><td>PXI_LBL9</td><td>GND</td><td>PXI_LBL10</td><td>PXI_LBL11</td><td>PXI_LBL12</td><td>GND</td></tr><tr><td>Pin</td><td>Z</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr></table>

Note 1: Please refer the following table for the routing of the Bus Mastering (REQ/GNT), IDSEL, PCI CLK, and Interrupt signals.

<table><tr><td></td><td>IDSEL</td><td>REQ#/GNT#</td><td>PCI CLK</td><td>PXI P1 Pin A3</td><td>PXI P1 Pin B3</td><td>PXI P1 Pin C3</td><td>PXI P1 Pin E3</td></tr><tr><td>Slot 1(SYS)</td><td>-</td><td>-</td><td>-</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>INTD#</td></tr><tr><td>Slot 2</td><td>AD31</td><td>0</td><td>6</td><td>INTD#</td><td>INTA#</td><td>INTB#</td><td>INTC#</td></tr><tr><td>Slot 3</td><td>AD30</td><td>1</td><td>5</td><td>INTC#</td><td>INTD#</td><td>INTA#</td><td>INTB#</td></tr><tr><td>Slot 4</td><td>AD29</td><td>2</td><td>1</td><td>INTB#</td><td>INTC#</td><td>INTD#</td><td>INTA#</td></tr><tr><td>Slot 5</td><td>AD28</td><td>3</td><td>2</td><td>INTA#</td><td>INTB#</td><td>INTC#</td><td>INTD#</td></tr><tr><td>Slot 6</td><td>AD27</td><td>4</td><td>3</td><td>INTD#</td><td>INTA#</td><td>INTB#</td><td>INTC#</td></tr><tr><td>Slot 7</td><td>AD26</td><td>5</td><td>4</td><td>INTC#</td><td>INTD#</td><td>INTA#</td><td>INTB#</td></tr><tr><td>Slot 8</td><td>AD25</td><td>6</td><td>0</td><td>INTB#</td><td>INTC#</td><td>INTB#</td><td>INTA#</td></tr></table>

Note 2: Please refer the following table for the routing of the PXI\_STAR addressing signals from the trigger slot to peripheral slots.

<table><tr><td>Physical Slot Number</td><td>PXI_STAR(P2-D17)</td></tr><tr><td>Slot 2(Star Trigger Slot)</td><td>PXI_STAR0~ PXI_STAR5</td></tr><tr><td>Slot 3</td><td>PXI_STAR0</td></tr><tr><td>Slot 4</td><td>PXI_STAR1</td></tr><tr><td>Slot 5</td><td>PXI_STAR2</td></tr><tr><td>Slot 6</td><td>PXI_STAR3</td></tr><tr><td>Slot 7</td><td>PXI_STAR4</td></tr><tr><td>Slot 8</td><td>PXI_STAR5</td></tr></table>

# B.2.2 Miscellaneous Connectors Pin Assignments

CN3: ATX-like DC Power input connectors

<table><tr><td>Signal Name</td><td>Pin #</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>V2SENSE</td><td>1</td><td>11</td><td>V2 (+3.3V)</td></tr><tr><td>V2 (+3.3V)</td><td>2</td><td>12</td><td>V4 (-12V)</td></tr><tr><td>GND</td><td>3</td><td>13</td><td>GND</td></tr><tr><td>V1 (+5V)</td><td>4</td><td>14</td><td>INH#</td></tr><tr><td>GND</td><td>5</td><td>15</td><td>GND</td></tr><tr><td>V1 (+5V)</td><td>6</td><td>16</td><td>SRTN</td></tr><tr><td>GND</td><td>7</td><td>17</td><td>GND</td></tr><tr><td>FAL#1</td><td>8*</td><td>18*</td><td>V3SENSE</td></tr><tr><td>DEG#1</td><td>9*</td><td>19</td><td>V1SENSE</td></tr><tr><td>V3 (+12V)</td><td>10</td><td>20</td><td>V1 (+5V)</td></tr></table>

Note 1: Pin #8, #9, and #18 are not standard ATX power definition.

General Purpose screw terminals
![The image displays two black geometric outlines on a white background, arranged vertically. The top outline is a square containing a single circle. Below it is a taller rectangular outline containing two circles stacked vertically, one in the upper half and one in the lower half.](.pxis-2630series-manual-1/c6ee102b20688ce67ffd8afa92d234b53d94c72b1f8b6b20c22c61a83c1cf064.jpg)

<table><tr><td>Position</td><td>Signal Name</td></tr><tr><td>J4</td><td>+3.3V</td></tr><tr><td>J6</td><td>V(I/O)</td></tr><tr><td>J7</td><td>+5V</td></tr></table>

Note that the V(I/O) must be shorted to either +3.3V or +5V. The default factory setting is to short V(I/O) to +5V.

J3 INH#: DC power inhibit signal

<table><tr><td rowspan="3">J3&lt;img src="images/64d15cd1caf04781104f3fb518663d1c4189ede12c97af0c6086059d4a252cbf.jpg"/&gt;</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>INH#</td></tr><tr><td>2</td><td>GND</td></tr></table>

J2 PRST#: System reset signal

<table><tr><td>J2</td><td>Pin #</td><td>Signal Name</td></tr><tr><td rowspan="2">&lt;img src="images/3c8bbb0a0cf6d8d1b249571f7eb47cdc53698342bd0d33a13b19343d693c0340.jpg"/&gt;</td><td>1</td><td>RST#</td></tr><tr><td>2</td><td>GND</td></tr></table>

J1 FAL#: Power supply fail input

<table><tr><td rowspan="3">J1&lt;img src="images/9e674e11f53d226b5433de888ed093fd2cb352ba85c922e027375088bb254b0d.jpg"/&gt;</td><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>FAL#</td></tr><tr><td>2</td><td>GND</td></tr></table>

J8: Connector for LED power status

<table><tr><td rowspan="5">J8&lt;img src="images/5f9d4e602c36cbe2efec0e55329946c976ad08059f30d710660da133deaaf77c.jpg"/&gt;</td><td>Name</td><td>Pin #</td><td>Pin #</td><td>Name</td></tr><tr><td>GND</td><td>8</td><td>7</td><td>+3.3V</td></tr><tr><td>GND</td><td>6</td><td>5</td><td>+5V</td></tr><tr><td>GND</td><td>4</td><td>3</td><td>-12V</td></tr><tr><td>GND</td><td>2</td><td>1</td><td>+12V</td></tr></table>

J5: SMB (system managing bus) connector

<table><tr><td rowspan="6">J5</td><td>Pin #</td><td>Name</td></tr><tr><td>1</td><td>SMCLK</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>SMDATA</td></tr><tr><td>4</td><td>V(I/O)</td></tr><tr><td>5</td><td>ALERT</td></tr></table>

The SMB is connected to the P2 of the system slot.

JP1: PXI Bus Speed Control

<table><tr><td></td><td>Pin 1-2</td><td>Description</td></tr><tr><td>System1</td><td>Short</td><td>Short M66EN to ground to force PCI bus run 33MHz</td></tr><tr><td>Tout43</td><td>Open (default)</td><td>PCI bus speed defined by M66EN on the PXI bus</td></tr></table>

JP2 JP3: PXI 10MHz Reference Clock Control

<table><tr><td>JP2</td><td>JP3</td><td>Pin 1-2</td><td>Description</td></tr><tr><td>[WEIZ]</td><td>[WEID]</td><td>Open JP2Short JP3</td><td>External clock through the PXI_CLK10_INon star trigger slot</td></tr><tr><td>[WCCK]</td><td>&lt;img src="images/9d20accd7ceaa43209379d594c312496ca60d7f3dd1e4394077bd2d2aa0cbf44.jpg"/&gt;</td><td>Short JP2Open JP3(default)</td><td>Internal 10MHz system clock PXI_CLK10</td></tr></table>

# SAFETY INSTRUCTIONS

1. Please read these safety instructions carefully.
2. Please keep this User's Manual for later reference.
3. One AC Inlet provided and service as Disconnect Devices, disconnect the equipment from the AC outlet use the AC Inlet before servicing or clearing. Use moisture sheet or cloth for cleaning.
4. For pluggable equipment, that the socket-outlet shall be installed near the equipment and shall be easily accessible.
5. Please keep this equipment from humidity.
6. Lay this equipment on a reliable surface when install. A drop or fall could cause injury.
7. Make sure the voltage of the power source when connect the equipment to the power outlet.
8. Place the power cord such a way that people can not step on it. Do not place anything over the power cord.
9. All cautions and warnings on the equipment should be noted.
10. If the equipment is not use for long time, disconnect the equipment from mains to avoid being damaged by transient overvoltage.
11. Never pour any liquid into opening, this could cause fire or electrical shock.
12. Never open the equipment. For safety reason, the equipment should only be opened by qualified service personnel.
13. If one of the following situations arises, get the equipment checked by a service personnel:

a. The Power cord or plug is damaged.
b. Liquid has penetrated into the equipment.
c. The equipment has been exposed to moisture.
d. The equipment has not work well or you can not get it work according to user's manual.
e. The equipment has dropped and damaged.
f. If the equipment has obvious sign of breakage.

1. The equipment can be operated at an ambient temperature of $50^{\circ}$ C.
2. Lithium Battery provided (real time clock battery), contact ADLINK for replacing,

CAUTION – Risk of explosion if battery is replaced by an incorrect type. Dispose of used batteries according to the instructions.

# Warranty Policy

Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully:

1. Before using ADLINK's products please read the user manual and follow the instructions exactly.
2. When sending in damaged products for repair, please attach an RMA application form.
3. All ADLINK products come with a two-year guarantee, repaired free of charge.

- The warranty period starts from the product's shipment date from ADLINK's factory.
- Peripherals and third-party products not manufactured by ADLINK will be covered by the original manufacturers' warranty.
- End users requiring maintenance services should contact their local dealers. Local warranty conditions will depend on local dealers.

4. This warranty will not cover repair costs due to:

• Damage caused by not following instructions.
- Damage caused by carelessness on the users' part during product transportation.
- Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.
- Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals.
• Damage caused by leakage of battery fluid.
• Damage from improper repair by unauthorized technicians.
- Products with altered and/or damaged serial numbers.
- Other categories not protected under our guarantees.

5. Customers are responsible for shipping costs to transport damaged products to our company or sales office.

6. To ensure the speed and quality of product repair, please use the RMA form attached in next page or you can download the form from our company website: http://www.adlinktech.com/news/Company/RMA.doc. Damaged products with attached RMA forms receive priority.

For further questions, please contact our FAE staff.

ADLINK: service@adlinktech.com

# RMA Request & Confirmation Form

Dear Customer,

Please fill out and fax back this form to obtain the RMA number for your returned or repaired product. Thank you very much!

<table><tr><td colspan="2">Your Company Name :</td><td colspan="3"></td></tr><tr><td colspan="2">Your Name :</td><td colspan="3"></td></tr><tr><td colspan="2">Invoice No. :</td><td colspan="3"></td></tr><tr><td>Part No.</td><td>Qty.</td><td>Serial No.</td><td>The reason of defect</td><td>Received Qty.by ADLINK</td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td></tr></table>

# Note:

1. Please give specific details of the defect. Do not give general reasons like, "not working, error, dead, etc."
2. Please ship prepaid by Speed post (EMS) (If items are shipped via freight forwarder, we will not cover the extra handing charges)
3. Please show a value of US\$10 for each item and include the RMA number. Also, be sure to write on shipping invoice, “for repair, no commercial value” for customs. (Please note that the amount must be under US\$200 for customs purposes only)
4. Enclose this form (page 1 & 2) in the package for fast identification.
5. Please sign this form (page 1 & 2) and fax it back to us for confirmation within three days. Otherwise, we will process your request according the stated on the RMA Request Form.
6. We will charge for items no longer under warranty.

Please let us know your preferred shipping method for returning reworked items to you.

□ Ship with your next shipment

□ Ship separately by air parcel

(Note: we do not accept liability for items shipped by air parcel)

□ Other

<table><tr><td>ADLINK Technology Inc.</td><td></td><td>Accepted &amp; Confirmed by</td></tr><tr><td></td><td></td><td></td></tr></table>
[🔗 Link to the original document](.pxis-2630series-manual-1/pxis-2630series-manual-1.pdf)