# Q7-EL

User’s Guide

intel

![Close-up of an Intel ATOM CPU board with various integrated circuits and chips (no readable text or symbols beyond product labels)](.q7-el-manual-50m-76005-1000-10/58e267c44bc96f96478eca62da15b2510348e5d9f50832c8f8b7325548a4cacb.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2024-09-02</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard yellow triangular warning sign with a thick black border. Inside the triangle, centered, is a black exclamation point. There is no text present.](.q7-el-manual-50m-76005-1000-10/ce8b5de515150bb464d53770d36469a9918efd9f8a92175052094e67c49fb797.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black and white line drawing of a wheeled waste bin with a lid. A large 'X' is superimposed over the bin. Below the bin, there is a solid black rectangular block.](.q7-el-manual-50m-76005-1000-10/56943c105064886f26196dc0a79bdb9a38a7832ef9a0feb7d137280c03429c71.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2024 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information.

![This image features a red icon of a document or page. It consists of a thick red outline forming a rectangle with a folded bottom-right corner. Inside the outline are two horizontal red lines. There is no text in the image.](.q7-el-manual-50m-76005-1000-10/9949ad02c0a9ef3d355d391277b426d4ccef002b62ec22d31bbb62e3859baab7.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a low-resolution, pixelated yellow triangle containing a white exclamation point in its center.](.q7-el-manual-50m-76005-1000-10/a15c54dd9ae1f1ef2b8b61139cff139972fe83b1da0fe5a47923b59f12ea6541.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image shows a red, upward-pointing triangle containing a centered white exclamation point, set against a white background.](.q7-el-manual-50m-76005-1000-10/8879ff32f58016af93327dd9c67fb36f3bf395d62cce773908d7365bfc065d02.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface .

List of Figures ... 8

1. Introduction .. C
2. Specifications.. .10

2.1. Core System... .10

2.2. Display Interface Support .. .11

2.2.1 Display Port... ..12

2.3. Audio ... ..12

2.4. Expansion Busses .. ... 13

2.5. PCI Express Bus.. ... 13

2.6. Ethernet ... ... 13

GPY 211 13

2.7. Multi I/O and Storage . ..14

2.8. BIOS ..... ... 16

... 16

2.10. Power.... ... 16

2.11. Mechanical and Environmental.. ..17

3. Block Diagram... .18
4. Pinout and Signal descriptions.... .19

4.1. Signal Terminology Definitions... ..19

4.2. Signal Description by function... ..20

4.2.1 GPIO.... ..20

4.2.2 Board to Board Connector ..... ..21

4.2.3 Debug Card Connector (DB40)... ... 26

5. Additional Features.. .29

5.1. LED Status Indicator... ..29

5.1.1 Power LED（Green LED）. ..29

5.1.2 Status LED（Blue LED） ..29

5.1.3 WDT LED（Red LED） ..29

6. Mechanical.... ..30

6.1. Module Dimensions (preliminary) .. ..30
7. Thermal Solutions... .32
7.1. Heat spreader... ..32
7.2. Low Profile Heatsink .. ..32

# List of Figures

Figure 1 – Module function diagram.. .18

Figure 2 – Module dimensions (top) .. ..30

Figure 3 – Module dimensions (bottom... ..31

# 1. Introduction

The Q7-EL is a QSeven form factor and revision 2.1 compliant computer-on-module that is fully compliant with the SGET (Standardization Group for Embedded Technologies) standards.

Qseven modules are very compact, highly integrated computers. The core of the Q7-EL is the Elkhart Lake SoC, which integrates the next generation Intel® processor core, graphics, LPDDR4 memory controller, and I/O interfaces into a single system-on-chip solution. The Q7-EL also includes contemporary high bandwidth interface such as PCI Express, USB2.0, USB3.0, 2.5 Gigabit Ethernet, SATA etc. It also features Audio, HDMI, LVDS,on board EMMC, SATA SSD, and more.

In addition, an optional fail-safe BIOS implemented to enable the user to start the module even if the original BIOS is corrupted.

# 2. Specifications

# 2.1. Core System

# CPU

Elkhart Lake SoC, chip package, size 24 x 35 mm, 10nm Compute Die and 14nm PCH Die on single package, 1493 Pin, Type 3 BGA, 0.593 mm ball pitch.

Intel Elkhart lake SOC is a 64-bit, multi-core processor built on 10-nanometer technology.

The processor supports the following technologies and interfaces:

•LPDDR4
•DDI
•PCI Express
•SATA3.0
•USB2.0/3.0
•eMMC
•SD
•SPI
•I2C
•HDA

# Memory

Memory controller supports single and dual channel LPDDR4@3200, 4267 with IBECC •4x 32-bit data bus LPDDR4 DRAM •Total memory capacity of 2GByte, 4 GByte, 8 GByte and 16 Gbyte (memory down)

The design supports following memory configuarations:

2 GByte: 2x 8Gbit (single channel)
4 GByte: 2x 16Gbit (single channel)
4 GByte: 4x 8Gbit (dual channel)
8 GByte: 4x 16Gbit (four channel)
16 GByte: 4x 32Gbit (four channel)

# Embedded BIOS

AMI EUFI with CMOS backup in 8MB SPI BIOS with Intelx2

# 2.2. Display Interface Support

eDP to LVDS(PTN3460): Via BOM option eDP to LVDS port.

The PTN3460 is the display port to LVDS converter.

• 2-Lane Display Port receiver
• 2-Port LVDS output interface

Max. resolution up to 1920x1200x60(RB), 18-bit color depth QFN-56 Pin package

# LVDS BOM option:

Primary Display

1x single or dual channel LVDS, 18/24 bit resolutions up to 1920x1080 (convert eDP with NXP transceiver PTN3460IBS)

Secondary Display

1x DisplayPort

Tertiary Display

1x DisplayPort or 1x HDMI

# eDP BOM option:

Primary Display

1x eDP

Secondary Display

1x DisplayPort

Tertiary Display

1x DisplayPort or 1x HDMI

# 2.2.1 Display Port

DisplayPort support resolutions up to 4096 × 2160@60 Hz, with SSC, max data rate 5.4 GT/s Standard Version 1.2.

# DP++ Operation Over HDMI

DP++ or DisplayPort++ (also named as Dual-mode DisplayPort) can directly output HDMI and DVI signals. The level adaptation can be implemented on the Carrier or via plug in cable adapter. In case of carrier board implementation, a level shifter adjusts the I/O voltage to HDMI/DVI compliant signal levels. A dual-mode chipset switches to DVI/HDMI mode (4-lane main DisplayPort link and AUX channel) if a DVI or HDMI passive adapter is detected (by DP0\_AUX\_SEL).

# 2.3. Audio

The Q7-EL support Intel High Definition Audio interface that supports audio codecs only. The controller communicates with the internal/external CODECs over the Intel® HD Audio serial link. The link can only operate at 3.3 V. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate of up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE levels of audio experience.

1x High-Definition Audio (HDA)

# 2.4. Expansion Busses

4x PCIe x1, including all support signals, clock, wake signal.

# 2.5. PCI Express Bus

There are four lanes and up to four PCI Express root ports, each supporting the PCI Express\* Base Specification, Rev. 3.0 at a maximum 8GT/s signaling rate. The root ports can be configured to support a diverse set of lane assignments.

# 2.6. Ethernet

# GPY 211

The Ethernet Network Connection GPY211 is a low power Ethernet PHY transceiver integrated circuit. It offers a cost-optimized solution that is wellsuited for routers, switches, and home gateways. It performs the data transmission on an Ethernet twisted pair copper cable of category CAT5e or higher. Four data rates are supported: 2500, 1000, 100, and 10 Mbit/s.

2x Ethernet PHY GPY211/GPY215 support LED signals

Q7-EL has 1 Gigabit Ethernet port which provides:

IEEE 802.3az Energy Efficient Ethernet
IEEE 1588/802.1AS precision time synchronization
IEEE 802.3Qav traffic shaper
Interrupt moderation, VLAN support, IP checksum offload
PCIe OBFF (Optimized Buffer Flush/Fill) for improved system power management

Four transmission and four reception queues
 RSS and MSI-X to lower CPU utilization in multi-core systems
ECC - error correcting memory in packet buffers
Wake-On-LAN
NC-SI for increased bandwidth passthrough
Preboot eXecution Environment (PXE) flash interface
Jumbo frame support

# 2.7. Multi I/O and Storage

# USB

• 2x USB3.1 gen2 host
• 1x USB2.0 OTG (port0)
5x USB2.0 host

USB Mapping: MXM2 connector side connected to Q7-EL SoC side

USB0 &lt;-&gt; USB2.0\_Port-0 (host)

USB1 &lt;-&gt; USB2.0\_Port-1 (host)

USB2 &lt;-&gt; USB2.0\_Port-2 (host)

# USB 3.0/2.0

The Q7-EL support six USB2.0 ports and two USB3.0 ports. USB2.0 port can be used to connect to high-speed, full-speed, and low-speed USB devices via xHCI controller. USB3.0 port has an xHCI controller and xDCI controller implemented in it.

# SATA

The Q7-EL has one integrated SATA host controller that supports DMA ports and supports data transfer rates of Gen 1 (1.5 Gb/s), Gen 2 (3 Gb/s), and SATA Gen 3 (6 Gb/s). The SATA controllers are completely software transparent with an AHCI interface, while providing a lower pin count and higher performance than the legacy parallel ATA interface.

2x SATA3 SATA III 6.0 Gb/s to carrier

# GPIO

8x interrupt capable GPIO (shared pins with LPC, non-default BOM option)

8x GPIO from BMC to MXM2 connector

Qseven standard supports 8x GPIO in total

# SD Card

1x SDIO 3.0 (4bit)

# SPI

The SPI flash controller supports running instructions at 20Mbps, 33Mbps, or 50 Mbps and can be used by BIOS code to provide chipset configuration settings, internal micro-processor code, and configurations. It also supports the Serial Flash Discoverable Parameter (SFDP) JEDEC standard, which provides a consistent way of describing the functional and feature capabilities of serial flash devices through a standard set of internal parameter tables. The SPI flash controller supports up to two SPI Flash devices using two separate chip select pins, with each SPI Flash device can be up to 16 MB.

1x SPI to MXM connector

# I2C

1x I2C to MXM

# UART

1x UART, two with 2 wire handshake

# 2.8. BIOS

AMI EUFI with CMOS backup in 8MB SPI BIOS with Intelx2

# 2.9. Debug

1x LPC connects to DB40 debug connector

# 2.10. Power

Standard Voltage Input: 4.75V - 5.25V DC

Power Management:

Power States: Supporting C1-C2, S0, S3, S4/S5 (both shutdown by SoC)

Wake S4/S5 is not supported
Wake S3 by USB / WOL / WAKE signal

ATX and AT mode and ECO mode are supported.

# 2.11. Mechanical and Environmental

# Form Factor and specification

Qseven® Standard Size Module Rev 2.1, Basic Size 70 mm x 70 mm

# Operating Temperature

<table><tr><td>Standard</td><td>0°C to 60°C</td></tr><tr><td>Extreme Rugged</td><td>-40°C to 85°C</td></tr></table>

# Humidity

5-90% RH operating, non-condensing

5-95% RH storage (operating with conformal coating).

# EMI

EN55022 Class B inside an enclosure

# Shock and Vibration

HALT testing report confirms the extended operating temperature range during and after vibration. There is a separate shock test report to MIL-STD-202F, Method 213B, Table 213-I, Condition A.

IN ADDITION: When installed on a baseboard, it shall operate under 18 saw-tooth mechanical shocks (3 shocks in each direction) with a peak acceleration of 40g for a duration of 18milliseconds each and 75g for a duration of 6milliseconds each. It is capable of supporting random vibrations: MIL-STD-202F, Method 214A, Table 214-I, Condition D. If HALT testing shows equal or better performance, a separate vibration test report is not necessary.

# MTBF

250,000 hrs. commercial 40°C ambient (according MIL calculation) based on actual calculated de-rating

# 3. Block Diagram

![The diagram illustrates the connectivity of an 'Elkhart Lake SOC' (System on Chip), labeled 'Q7 2.1', situated centrally in a large pink block.\n\n**Left-Side Connections (Inputs/Signals):**\n*   **LVDS A/eDP** connects to **DDI0**. Dashed lines branch to **eDP option** and **NXP PTN3460**.\n*   **DDI/LVDS B** connects to **DDI1**. A dashed line branches to **NXP PTN3460**.\n*   **DP++ / HDMI** connects to **DDI2**. A dashed line branches to **DP**.\n*   **USB 2,3,4,5** connects to **USB 2.0 HOST**.\n*   **USB 0,1** connects to **USB 3.1 gen 2 HOST**.\n*   **2x SATA Gen3** connects to **SATA Gen3**.\n*   **LAN0** connects via a **PHY** block to **RGMii**.\n*   **PCIe A, B, C, D** connects to **4x PCIe1Gen3**.\n*   **CAN** connects to **CAN**.\n*   **HDA** connects to **HDA Audio**.\n*   **SDIO** connects to **SDIO 4bit**.\n*   **UART** connects to **UART**.\n*   **SPI** connects to **FSPI**.\n*   **I2C** connects to **I2C**.\n*   **LPC** connects via **LPC bridge ECE1200-I/LD** to **eSPI**.\n*   **SPI bios** connects to **SPI**.\n*   **Boot select**, **FAN control**, and **8xGPIO** connect to the bottom **BMC/EC** block.\n\n**Right-Side Connections (Peripherals/Memory):**\n*   Four stacked blocks of **LPDDR4 x32**.\n*   **eMMC 16/32/64GB**.\n*   **TPM 2.0** connects via a line labeled **SPI**.\n*   **debug** connects to the bottom right.\n\n**Bottom Connections:**\n*   **eSPI** connects the SOC to the **BMC/EC** block.\n*   **BMC/EC** connects to **Power**.](.q7-el-manual-50m-76005-1000-10/cbe6344e32d7bd364506b320b9c3e58ccee36513963ef82fcb03552b96692582.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal descriptions

# 4.1. Signal Terminology Definitions

The following information provides descriptions of the terms used in the signal description table:

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the Module</td></tr><tr><td>O</td><td>Output from the Module</td></tr><tr><td>I/O</td><td>Bi-directional input / output signal</td></tr><tr><td>OD</td><td>Open drain output</td></tr><tr><td>P_+3V3_BMC_A</td><td>S5 power P_+3V3_BMC_A tolerant</td></tr><tr><td>P_+3V3_A</td><td>S5 power P_+3V3_A tolerant</td></tr><tr><td>P_+1V5_A</td><td>S5 power P_+1V5_A tolerant</td></tr><tr><td>P_+1V24_A</td><td>S5 power P_+1V24_A tolerant</td></tr><tr><td>P_+1V8_A</td><td>S5 power P_+1V8_A tolerant</td></tr><tr><td>P_+1V05_S0</td><td>S0 power P_+1V05_S0 tolerant</td></tr><tr><td>P_+3V3_S0</td><td>S0 power P_+3V3_S0 tolerant</td></tr><tr><td>P_+1V8_S0</td><td>S0 power P_+1V8_S0 tolerant</td></tr><tr><td>P</td><td>Power Input/Output</td></tr><tr><td>REF</td><td>Reference voltage output</td></tr><tr><td>PU</td><td>ADLINK implemented pull-up resistor on module</td></tr><tr><td>PD</td><td>ADLINK implemented pull-down resistor on module</td></tr><tr><td>P_+VQ7</td><td>Module power input</td></tr></table>

# 4.2. Signal Description by function

# 4.2.1 GPIO

All GPIOs are driven by the BMC according to the Qseven specification.

GPIO0-7 are multiplexed with low pin count. Low pin count is the recommended default setup.

<table><tr><td>Signal Name</td><td>Direction</td><td>Direction Preferred</td><td>Type / Tolerance</td><td>GPIO Use</td><td>Sanctioned Alternate Uses</td></tr><tr><td>GPIO0 / LPC_AD0</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO0</td><td>LPC Data 0</td></tr><tr><td>GPIO1 / LPC_AD1</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO1</td><td>LPC Data 1</td></tr><tr><td>GPIO2 / LPC_AD2</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO2</td><td>LPC Data 2</td></tr><tr><td>GPIO3 / LPC_AD3</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO3</td><td>LPC Data 3</td></tr><tr><td>GPIO4 / LPC_CLK0</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO4</td><td>LPC clock</td></tr><tr><td>GPIO5 / LPC_FRAME-L</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO5</td><td>LPC frame indicates the start of a new cycle or the termination of a broken cycle.</td></tr><tr><td>GPIO6 / LPC_SERIRQ</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO6</td><td>Serialized Interrupt.</td></tr><tr><td>GPIO7</td><td>Bi -Dir</td><td>Output</td><td>CMOS 3.3V</td><td>GPIO7</td><td>N/A</td></tr></table>

4.2.2 Board to Board Connector

<table><tr><td colspan="3">Primary side (BOTTOM)</td><td colspan="3">Secondary side (TOP)</td></tr><tr><td>Pin#</td><td>Signal</td><td>PU/PD</td><td>Pin#</td><td>Signal</td><td>PU/PD</td></tr><tr><td>1</td><td>GND</td><td></td><td>2</td><td>GND</td><td></td></tr><tr><td>3</td><td>GBE_MDI3-</td><td></td><td>4</td><td>GBE_MDI2-</td><td></td></tr><tr><td>5</td><td>GBE_MDI3+</td><td></td><td>6</td><td>GBE_MDI2+</td><td></td></tr><tr><td>7</td><td>GBE_LINK100#</td><td></td><td>8</td><td>GBE_LINK1000#</td><td></td></tr><tr><td>9</td><td>GBE_MDI1-</td><td></td><td>10</td><td>GBE_MDI0-</td><td></td></tr><tr><td>11</td><td>GBE_MDI1+</td><td></td><td>12</td><td>GBE_MDI0+</td><td></td></tr><tr><td>13</td><td>GBE_LINK#</td><td></td><td>14</td><td>GBE_ACT#</td><td></td></tr><tr><td>15</td><td>GBE_CTREF</td><td></td><td>16</td><td>SUS_S5#</td><td></td></tr><tr><td>17</td><td>WAKE#</td><td></td><td>18</td><td>SUS_S3#</td><td></td></tr><tr><td>19</td><td>GPO0</td><td></td><td>20</td><td>PWRBTN#</td><td></td></tr><tr><td>21</td><td>SLP_BTN# / GPII1</td><td></td><td>22</td><td>LID_BTN# / GPII0</td><td></td></tr><tr><td>23</td><td>GND</td><td></td><td>24</td><td>GND</td><td></td></tr><tr><td>Key</td><td></td><td></td><td>Key</td><td></td><td></td></tr><tr><td>25</td><td>GND</td><td></td><td>26</td><td>PWGIN</td><td></td></tr><tr><td>27</td><td>BATLOW#</td><td></td><td>28</td><td>RSTBTN#</td><td></td></tr><tr><td>29</td><td>SATA0_TX+</td><td></td><td>30</td><td>SATA1_TX+</td><td></td></tr><tr><td>31</td><td>SATA0_TX-</td><td></td><td>32</td><td>SATA1_TX+</td><td></td></tr><tr><td>33</td><td>SATA_ACT#</td><td></td><td>34</td><td>GND</td><td></td></tr><tr><td>35</td><td>SATA0_RX+</td><td></td><td>36</td><td>SATA1_RX+</td><td></td></tr><tr><td>37</td><td>SATA0_RX-</td><td></td><td>38</td><td>SATA1_RX-</td><td></td></tr><tr><td>39</td><td>GND</td><td></td><td>40</td><td>GND</td><td></td></tr><tr><td>41</td><td>BI-OS_DISABLE#/BOOT_ALT#</td><td></td><td>42</td><td>SDIO_CLK#</td><td></td></tr><tr><td>43</td><td>SDIO_CD#</td><td></td><td>44</td><td>SDIO_LED</td><td></td></tr><tr><td>45</td><td>SDIO_CMD</td><td></td><td>46</td><td>SDIO_WP</td><td></td></tr><tr><td>47</td><td>SDIO_PWR#</td><td></td><td>48</td><td>SDIO_DAT1</td><td></td></tr><tr><td>49</td><td>SDIO_DAT0</td><td></td><td>50</td><td>SDIO_DAT3</td><td></td></tr><tr><td>51</td><td>SDIO_DAT2</td><td></td><td>52</td><td>reserved</td><td></td></tr><tr><td>53</td><td>reserved</td><td></td><td>54</td><td>reserved</td><td></td></tr><tr><td>55</td><td>reserved</td><td></td><td>56</td><td>USB_OTG_VBUS</td><td></td></tr><tr><td>57</td><td>GND</td><td></td><td>58</td><td>GND</td><td></td></tr><tr><td>59</td><td>HDA_SYNC / I2S_WS</td><td></td><td>60</td><td>SMB_CLK/GP1_I2C_CLK</td><td></td></tr><tr><td>61</td><td>HDA_RST# / I2S_RST# /</td><td></td><td>62</td><td>SMB_DAT/GP1_I2C_DAT</td><td></td></tr><tr><td>63</td><td>HDA_BCLK / I2S_BCLK /</td><td></td><td>64</td><td>SMB_ALERT#</td><td></td></tr><tr><td>65</td><td>HDA_SDI / I2S_SDI /</td><td></td><td>66</td><td>GP0_I2C_CLK</td><td></td></tr><tr><td>67</td><td>HDA_SDO / I2S_SDO /</td><td></td><td>68</td><td>GP0_I2C_DAT</td><td></td></tr><tr><td>69</td><td>THRM#</td><td></td><td>70</td><td>WDTRIG#</td><td></td></tr><tr><td>71</td><td>THRMTRIP#</td><td></td><td>72</td><td>WDOUT</td><td></td></tr><tr><td>73</td><td>GND</td><td></td><td>74</td><td>GND</td><td></td></tr><tr><td>75</td><td>USB_P7-/USB_SSTX0-</td><td></td><td>76</td><td>USB_P6-/USB_SSRX0-</td><td></td></tr><tr><td>77</td><td>USB_P7+/USB_SSTX0+</td><td></td><td>78</td><td>USB_P6+/USB_SSRX0+</td><td></td></tr><tr><td>79</td><td>USB_6_7_OC#</td><td></td><td>80</td><td>USB_4_5_OC#</td><td></td></tr><tr><td>81</td><td>USB_P5-/USB_SSTX1-</td><td></td><td>82</td><td>USB_P4-/USB_SSRX1-</td><td></td></tr><tr><td>83</td><td>USB_P5+/USB_SSTX1+</td><td></td><td>84</td><td>USB_P4+/USB_SSRX1+</td><td></td></tr><tr><td>85</td><td>USB_2_3_OC#</td><td></td><td>86</td><td>USB_0_1_OC#</td><td></td></tr><tr><td>87</td><td>USB_P3-</td><td></td><td>88</td><td>USB_P2-</td><td></td></tr><tr><td>89</td><td>USB_P3+</td><td></td><td>90</td><td>USB_P2+</td><td></td></tr><tr><td>91</td><td>USB_CC</td><td></td><td>92</td><td>USB_ID</td><td></td></tr><tr><td>93</td><td>USB_P1-</td><td></td><td>94</td><td>USB_P0-</td><td></td></tr><tr><td>95</td><td>USB_P1+</td><td></td><td>96</td><td>USB_P0+</td><td></td></tr><tr><td>97</td><td>GND</td><td></td><td>98</td><td>GND</td><td></td></tr><tr><td>99</td><td>eDP0_TX0+ / LVDS_A0+</td><td></td><td>100</td><td>eDP1_TX0+ / LVDS_B0+</td><td></td></tr><tr><td>101</td><td>eDP0_TX0- / LVDS_A0-</td><td></td><td>102</td><td>eDP1_TX0- / LVDS_B0-</td><td></td></tr><tr><td>103</td><td>eDP0_TX1+ / LVDS_A1+</td><td>PU, 470k, V1P8S</td><td>104</td><td>eDP1_TX1+ / LVDS_B1+</td><td></td></tr><tr><td>105</td><td>eDP0_TX1- / LVDS_A1-</td><td>PU, 470k, V1P8S</td><td>106</td><td>eDP1_TX1- / LVDS_B1-</td><td></td></tr><tr><td>107</td><td>eDP0_TX2+ / LVDS_A2+</td><td>PU, 470k, V1P8S</td><td>108</td><td>eDP1_TX2+ / LVDS_B2+</td><td></td></tr><tr><td>109</td><td>eDP0_TX2- / LVDS_A2-</td><td>PU, 470k, V1P8S</td><td>110</td><td>eDP1_TX2- / LVDS_B2-</td><td></td></tr><tr><td>111</td><td>LVDS_PPEN</td><td>PU, 470k, V1P8S</td><td>112</td><td>LVDS_BLEN</td><td></td></tr><tr><td>113</td><td>eDP0_TX3+ / LVDS_A3+</td><td>PU, 470k, V1P8S</td><td>114</td><td>eDP1_TX3+ / LVDS_B3+</td><td></td></tr><tr><td>115</td><td>eDP0_TX3- / LVDS_A3-</td><td>PU, 470k, V1P8S</td><td>116</td><td>eDP1_TX3- / LVDS_B3-</td><td></td></tr><tr><td>117</td><td>GND</td><td></td><td>118</td><td>GND</td><td></td></tr><tr><td>119</td><td>eDP0_AUX+ / LVDS_A_CLK+</td><td></td><td>120</td><td>eDP1_AUX+ / LVDS_B_CLK+</td><td></td></tr><tr><td>121</td><td>eDP0_AUX- / LVDS_A_CLK-</td><td></td><td>122</td><td>eDP1_AUX- / LVDS_B_CLK-</td><td></td></tr><tr><td>123</td><td>LVDS_BLT_CTRL/GP_PWM_OUTO</td><td></td><td>124</td><td>GP_1-Wire_Bus/HDMI_CEC</td><td></td></tr><tr><td>125</td><td>GP2_I2C_DAT / LVDS_DID_DAT</td><td></td><td>126</td><td>eDP0_HPD# / LVDS_BLC_DAT</td><td></td></tr><tr><td>127</td><td>GP2_I2C_CLK / LVDS_DID_CLK</td><td></td><td>128</td><td>eDP1_HPD# / LVDS_BLC_CLK</td><td></td></tr><tr><td>129</td><td>CAN0_TX</td><td></td><td>130</td><td>CAN0_RX</td><td></td></tr><tr><td>131</td><td>DP_LANE3+ / TMDS_CLK+</td><td></td><td>132</td><td>USB_SSTX1-</td><td></td></tr><tr><td>133</td><td>DP_LANE3- / TMDS_CLK-</td><td></td><td>134</td><td>USB_SSTX1+</td><td></td></tr><tr><td>135</td><td>GND</td><td></td><td>136</td><td>GND</td><td></td></tr><tr><td>137</td><td>DP_LANE1+ / TMDS_LANE1+</td><td></td><td>138</td><td>DP_AUX+</td><td></td></tr><tr><td>139</td><td>DP_LANE1- / TMDS_LANE1-</td><td></td><td>140</td><td>DP_AUX-</td><td></td></tr><tr><td>141</td><td>GND</td><td></td><td>142</td><td>GND</td><td></td></tr><tr><td>143</td><td>DP_LANE2+ / TMDS_LANE0+</td><td></td><td>144</td><td>USB_SSRX1-</td><td></td></tr><tr><td>145</td><td>DP_LANE2- / TMDS_LANE0-</td><td></td><td>146</td><td>USB_SSRX1+</td><td></td></tr><tr><td>147</td><td>GND</td><td></td><td>148</td><td>GND</td><td></td></tr><tr><td>149</td><td>DP_LANE0+ / TMDS_LANE2+</td><td></td><td>150</td><td>HDMI_CTRL_DAT</td><td></td></tr><tr><td>151</td><td>DP_LANE0- / TMDS_LANE2-</td><td></td><td>152</td><td>HDMI_CTRL_CLK</td><td></td></tr><tr><td>153</td><td>DP_HDMI_HPD#</td><td></td><td>154</td><td>DP_HDP#</td><td></td></tr><tr><td>155</td><td>PCIE_CLK_REF+</td><td></td><td>156</td><td>PCIE_WAKE#</td><td></td></tr><tr><td>157</td><td>PCIE_CLK_REF-</td><td></td><td>158</td><td>PCIE_RST#</td><td></td></tr><tr><td>159</td><td>GND</td><td></td><td>160</td><td>GND</td><td></td></tr><tr><td>161</td><td>PCIE3_TX+</td><td></td><td>162</td><td>PCIE3_RX+</td><td></td></tr><tr><td>163</td><td>PCIE3_TX-</td><td></td><td>164</td><td>PCIE3_RX-</td><td></td></tr><tr><td>165</td><td>GND</td><td></td><td>166</td><td>GND</td><td></td></tr><tr><td>167</td><td>PCIE2_TX+</td><td></td><td>168</td><td>PCIE2_RX+</td><td></td></tr><tr><td>169</td><td>PCIE2_TX-</td><td></td><td>170</td><td>PCIE2_RX-</td><td></td></tr><tr><td>171</td><td>UART0_TX</td><td></td><td>172</td><td>UART0_RTS#</td><td></td></tr><tr><td>173</td><td>PCIE1_TX+</td><td></td><td>174</td><td>PCIE1_RX+</td><td></td></tr><tr><td>175</td><td>PCIE1_TX-</td><td></td><td>176</td><td>PCIE1_RX-</td><td></td></tr><tr><td>177</td><td>UART0_RX</td><td></td><td>178</td><td>UART0_CTS#</td><td></td></tr><tr><td>179</td><td>PCIE0_TX+</td><td></td><td>180</td><td>PCIE0_RX+</td><td></td></tr><tr><td>181</td><td>PCIE0_TX-</td><td></td><td>182</td><td>PCIE0_RX-</td><td></td></tr><tr><td>183</td><td>GND</td><td></td><td>184</td><td>GND</td><td></td></tr><tr><td>185</td><td>LPC_AD0 / GPIO0</td><td></td><td>186</td><td>LPC_AD1 / GPIO1</td><td></td></tr><tr><td>187</td><td>LPC_AD2 / GPIO2</td><td></td><td>188</td><td>LPC_AD3 / GPIO3</td><td></td></tr><tr><td>189</td><td>LPC_AD4 / GPIO4</td><td></td><td>190</td><td>LPC_FRAME# / GPIO5</td><td></td></tr><tr><td>191</td><td>SERIRQ / GPIO6</td><td></td><td>192</td><td>LPC_LDRQ# / GPIO7</td><td></td></tr><tr><td>193</td><td>VCC_RTC</td><td></td><td>194</td><td>SPKR / GP_PWM_OUT2</td><td></td></tr><tr><td>195</td><td>FAN_TACHOIN / GP_TIMER_IN</td><td></td><td>196</td><td>FAN_PWMOUT / GP_PWM_OUT1</td><td></td></tr><tr><td>197</td><td>GND</td><td></td><td>198</td><td>GND</td><td></td></tr><tr><td>199</td><td>SPI_MOSI</td><td></td><td>200</td><td>SPI_CS0#</td><td></td></tr><tr><td>201</td><td>SPI_MISO</td><td></td><td>202</td><td>SPI_CS1#</td><td></td></tr><tr><td>203</td><td>SPI_SCK</td><td></td><td>204</td><td>MFG_NC4</td><td></td></tr><tr><td>205</td><td>VCC_5V_SB</td><td></td><td>206</td><td>VCC_5V_SB</td><td></td></tr><tr><td>207</td><td>MFG_NC0</td><td></td><td>208</td><td>MFG_NC2</td><td></td></tr><tr><td>209</td><td>MFG_NC1</td><td></td><td>210</td><td>MFG_NC3</td><td></td></tr><tr><td>211</td><td>NC*</td><td></td><td>212</td><td>NC*</td><td></td></tr><tr><td>213</td><td>NC*</td><td></td><td>214</td><td>NC*</td><td></td></tr><tr><td>215</td><td>NC*</td><td></td><td>216</td><td>NC*</td><td></td></tr><tr><td>217</td><td>NC*</td><td></td><td>218</td><td>NC*</td><td></td></tr><tr><td>219</td><td>VCC</td><td></td><td>220</td><td>VCC</td><td></td></tr><tr><td>221</td><td>VCC</td><td></td><td>222</td><td>VCC</td><td></td></tr><tr><td>223</td><td>VCC</td><td></td><td>224</td><td>VCC</td><td></td></tr><tr><td>225</td><td>VCC</td><td></td><td>226</td><td>VCC</td><td></td></tr><tr><td>227</td><td>VCC</td><td></td><td>228</td><td>VCC</td><td></td></tr><tr><td>229</td><td>VCC</td><td></td><td>230</td><td>VCC</td><td></td></tr></table>

# 4.2.3 Debug Card Connector (DB40)

For information on LVDS support for a single-channel with 4 lanes, please refer to the details below:

<table><tr><td>Pin Number</td><td>Interface</td><td>Signals</td><td>Comments</td></tr><tr><td>1</td><td rowspan="7">SPI Program Interface</td><td>VCC_SPI_IN</td><td>SPI Power Input from flash tool to moduleP.S. HW need add MOS FET to switch SPI power for SPI ROM.</td></tr><tr><td>2</td><td>GND</td><td></td></tr><tr><td>3</td><td>SPI_BIOS_CS0#</td><td></td></tr><tr><td>4</td><td>SPI_BIOS_CS1#</td><td></td></tr><tr><td>5</td><td>SPI_BIOS_MISO</td><td></td></tr><tr><td>6</td><td>SPI_BIOS_MOSI</td><td></td></tr><tr><td>7</td><td>SPI_BIOS_CLK</td><td></td></tr><tr><td>8</td><td rowspan="6">LPC Debug card Interface</td><td>3V3_LPC</td><td>System power 3.3V provide from COM module</td></tr><tr><td>9</td><td>GND</td><td></td></tr><tr><td>10</td><td>BIOS_DIS0</td><td></td></tr><tr><td>11</td><td>RST#</td><td></td></tr><tr><td>12</td><td>CLK33_LPC</td><td></td></tr><tr><td>13</td><td>LPC_FRAME#</td><td></td></tr><tr><td>14</td><td rowspan="4"></td><td>LPC_AD3</td><td></td></tr><tr><td>15</td><td>LPC_AD2</td><td></td></tr><tr><td>16</td><td>LPC_AD1</td><td>always power 3.3V provide from COM module</td></tr><tr><td>17</td><td>LPC_AD0</td><td></td></tr><tr><td>18</td><td rowspan="11">SMC Program interface</td><td>3.3V_SMC</td><td>always power 3.3V provide from COM module</td></tr><tr><td>19</td><td>3.3V_A</td><td>always power 3.3V provide from COM module</td></tr><tr><td>20</td><td>GND</td><td></td></tr><tr><td>21</td><td>TXD6</td><td></td></tr><tr><td>22</td><td>RXD6</td><td></td></tr><tr><td>23</td><td>FUMD0</td><td></td></tr><tr><td>24</td><td>RESET_IN#</td><td></td></tr><tr><td>25</td><td>DATA</td><td></td></tr><tr><td>26</td><td>CLK</td><td></td></tr><tr><td>27</td><td>OCD0A</td><td>include a jumper to connect OCD0A via 1K0 pull-up to 3.3V_SMC</td></tr><tr><td>28</td><td>OCD0B</td><td>include a jumper to connect OCD0B via 1K0 pull-down to GND</td></tr><tr><td>29</td><td rowspan="7">Test point</td><td>PWRBTN#</td><td></td></tr><tr><td>30</td><td>SYS_RESET#</td><td></td></tr><tr><td>31</td><td>CB_RESET#</td><td></td></tr><tr><td>32</td><td>CB_PWROK</td><td></td></tr><tr><td>33</td><td>SUS_S3#</td><td></td></tr><tr><td>34</td><td>SUS_S4#</td><td></td></tr><tr><td>35</td><td>SUS_S5#</td><td></td></tr><tr><td>36</td><td rowspan="4">For SMC Debug</td><td>POSTWDT_DIS#</td><td>Connect to Jumper for Debug</td></tr><tr><td>37</td><td>SEL_BIOS</td><td>Connect to Jumper for Debug</td></tr><tr><td>38</td><td>BIOS_MODE</td><td>Connect to Jumper for Debug</td></tr><tr><td>39</td><td>SMC_STATUS</td><td>Connect to LED</td></tr><tr><td>40</td><td>NC</td><td>RESVD</td><td></td></tr></table>

# 5. Additional Features

# 5.1. LED Status Indicator

# 5.1.1 Power LED （Green LED）

The Power LED that is controlled by SLP\_S3# and should be light only in S0 state.

# 5.1.2 Status LED（Blue LED）

The Status LED is controlled by SEMA. The Status LED will signal system state changes and power up failures. The system state changes can be HW-Reset, SW-Reset, Power-Up, Power-Down, Reset-Button and Power-Button activity. The Status LED will light for short time. Power-Up failures can be a corrupted BIOS or failures at the onboard power supply. A blink code will be displayed in case of a failure. In S3 state, the Status LED will be displayed on by short periodic flashes for every 4sec.

# 5.1.3 WDT LED（Red LED）

The WDT LED is driven by SEMA and will light when a watchdog timeout occurs. It stays on as long till it is cleared by software or by reset button.

# 6. Mechanical

# 6.1. Module Dimensions

![70(2755.9)\n70(2755.9)\n3\n2\n1\n4\n2.32\n0.5±0.03\n0.35±0.03\n2.3±0.06\n2.33±0.05\n1.17±0.05\n54.53±0.075\n62.11±0.05\nTOP SIDE](.q7-el-manual-50m-76005-1000-10/ccdd8be4e1399d42c7b2f3d55924a8e5af8111c5ff3ae46ddd0ae1759b15b617.jpg)

Figure 2 – Module dimensions (top)

![BOTTOM SIDE\n0.35±0.03\n1.42±0.05\n2.08±0.05\n2.3±0.08\n5](.q7-el-manual-50m-76005-1000-10/04b745462f35a19a0f7032132625f40b665d8b55a3437af289ef8f202b0ce256.jpg)

Figure 3 – Module dimensions (bottom

# 7. Thermal Solutions

# 7.1. Heat spreader

One design / Dual Core / Low Power Quad Core

# 7.2. Low Profile Heatsink

Dual Core / Quad Core u pro 12W power dissipation（Top mounting with springs）