# LEC-EL

User’s Guide

intel

![Close-up of a blue printed circuit board with integrated circuits and gold contacts (no visible text or symbols)](.smarc-lec-el-50m-72513-1050-15/ed64eb8a264d37e346b6849ba2d68131080d8172f0eb39c0adbcd0c7be8a10cb.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2023-05-09</td><td>CC</td></tr><tr><td>1.1</td><td>BIOS info added</td><td>2023-10-13</td><td>CC</td></tr><tr><td>1.2</td><td>Specifications updated</td><td>2025-02-12</td><td>AL</td></tr><tr><td>1.3</td><td>Specifications updated</td><td>2025-04-07</td><td>AL</td></tr><tr><td>1.4</td><td>Pinout and signal descriptions updated</td><td>2025-05-08</td><td>AL</td></tr><tr><td>1.5</td><td>Specifications updated</td><td>2025-11-05</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border. Inside the triangle, centered, is a black exclamation point. The left edge of the image shows a vertical black bar adjacent to the triangle.](.smarc-lec-el-50m-72513-1050-15/d404c65ed21070d9546accba77478a05694d8b5909593fee8fbf08c6bcc7892a.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image shows a black outline of a wheeled waste bin with a large 'X' crossed over it, indicating that the item should not be discarded as household waste. Below this symbol is a solid black rectangular shape.](.smarc-lec-el-50m-72513-1050-15/9f99b23ef2b73fc0dd04328d7424f377344902ef530ed58f297355296d103c32.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.

Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
• Keep equipment away from water or liquid sources;
• Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![This image features a red icon on a white background. It depicts a stylized document or note with a thick red outline. The shape is roughly rectangular with a folded 'dog-ear' corner at the bottom right. Inside the outline, there are two horizontal red lines centered vertically, representing lines of text.](.smarc-lec-el-50m-72513-1050-15/7ffb88928b8d03e9cbb52c2e0c26564bf8e699b532a3cd430ec73ea94312ff1b.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![A yellow triangle with a white exclamation point in the center.](.smarc-lec-el-50m-72513-1050-15/7829f27edb83df1e8d2959a1a70991872c2036054e8f807e81a193d9485e9985.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image shows a red triangular warning symbol containing a centered white exclamation point.](.smarc-lec-el-50m-72513-1050-15/b0359a66da1dcedf995cb1da7f879e4a9af057eec9c2aa569d9f86128df1cd52.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

1. Introduction .. . 9

1.1 LEC-EL.. .
1.2 The SMARC Form Factor .. ..9

2. Specifications.. .10

2.1 Core System... .. 10
2.2 Video.... . 11
2.3 Audio .. . 11
2.4 Dual Ethernet.. .. 12
2.5 Extension busses.. . 12
2.6 System Storage .. . 14
2.7 Board Controller... . 14
2.8 SEMA® Board Management Controller . . 14
2.9 Debug Header ... ... 15
2.10 BIOS... ... 15
2.11 Power... .. 15
2.12 Mechanical and Environmental .. . 16

3. Block Diagram .. 17

4. Pinout and Signal Descriptions .... .18

4.1 Pin Summary ... . 18
4.2 Signal Terminology Descriptions.. . 17
4.3 Signal Description by function.... . 18

4.3.1 The First Display Interface.. .. 18
4.3.2 Second Display Interface.. . 21
4.3.3 MIPI Camera support.. . 23
4.3.4 HDA (Audio).. ... 23
4.3.5 USB ports... ... 24
4.3.6 PCIe Ports... .. 26
4.3.7 SATA Gen 3 Ports... .. 28
4.3.8 LAN ports .. .. 29
4.3.9 SDIO .... . 31

4.3.10 SPI & ESPI . . 32
4.3.11 SPI0 ..... . 32
4.3.12 ESPI ... ... 33

4.4 General Purpose I2C... .. 34

4.4.1 GPIO ... ... 35
4.4.2 UART .. . 36
4.4.3 CAN bus.. . 37
4.4.4 Miscellaneous.. . 37
4.4.5 Power and System Management.. ... 38
4.4.6 Boot Select... .... 40
4.4.7 Power.. . 41

4.5 SMARC pin to controller mapping.... .. 42

5. Additional Features .. .54

5.1 Module Feature Locations.. ... 54
5.2 Status LEDs.... ... 55
5.2.1 Exception Codes.. . 56

6. System Resources ....... ..57

6.1 System Memory Map... .. 57
6.2 Fixed I/O Address Range Map .. ... 59
6.3 Variable I/O Address Range Map .. .... 61
6.4 PCI Configuration Space Map.. .... 61
6.5 PCI Interrupt Routing Map ... ... 64
6.6 SMBus Address Table .. ... 65

7. BIOS Configurations .... ..66

7.1 Main ... .. 67

7.1.1 Main > BIOS Information . . 67
7.1.2 Main > System Information . . 67
7.1.3 Main > Board Information ..... ..... 68
7.1.4 Main > System Date/Time ...... ..... 68
7.1.5 Main > Access Level ... .... 69

7.2 Advanced .. ... 69

7.2.1 Advanced > CPU Configuration .. . 69
7.2.2 Advanced > Power & Performance . . 70
7.2.3 Advanced > Graphics Configuration.. . 79
7.2.4 Advanced > AMI Graphic Output Protocol Policy... . 81
7.2.5 Advanced > Power Management.. . 81
7.2.6 Advanced > System Management.. . 82

7.2.7 Advanced > Thermal Management.... . 83

7.2.8 Advanced > Watchdog Timer ..... . 85

7.2.9 Advanced > Super IO Configuration.... . 85

7.2.10 Advanced > Serial Console Redirection... . 86

7.2.11 Advanced > Miscellaneous.. . 94

7.2.12 Advanced > USB Configuration.... . 95

7.2.13 Advanced > Network Stack Configuration.. . 96

7.2.14 Advanced > Trusted Computing.. . 96

7.3 Chipset .. .. 97

7.3.1 Chipset > System Agent (SA) Configuration... . 97

7.3.2 Chipset > PCH-IO Configuration .. ....101

7.4 Security .... ...118

7.4.1 Security > Password Description . ..118

7.5 Boot .... .....119

7.5.1 Boot > Boot Configuration... ..119

7.5.2 Boot > Fixed Boot Order Priorities.. ..120

7.6 Save & Exit.... .....120

8. BIOS Checkpoints, Beep Codes .... . 121

8.1 Status Code Ranges ... .....122

8.2 Standard Status Codes.. .....123

8.2.1 SEC Phase.. ...123

8.2.2 SEC Phase > SEC Beep Codes .. ..124

8.2.3 SEC Phase > PEI Phase . ..124

8.2.4 SEC Phase > PEI Beep Codes.. ..128

8.2.5 SEC Phase > DXE Status Codes . ..128

8.2.6 SEC Phase > DXE Beep Codes... ..132

8.2.7 SEC Phase > ACPI/ASL Checkpoint. ..133

8.3 OEM-reserved Checkpoint Ranges . ...134

9. Software Support .......... . 135

9.1.1 Yocto .. ...135

9.1.2 Ubuntu .. ...135

9.1.3 Windows.. ...135

10.Mechanical... . 136

11. Thermal Solutions..... . 137

# List of Figures

Figure 1 – Module function diagram... 17
Figure 2 – Module top/botom side pin numbering ..... ...18
Figure 3 – Module feature locations (top side) ... ...54
Figure 4: Mechanical dimensions... . 136
Figure 5: Thermal solutions .... . 137

# 1. Introduction

# LEC-EL

ADLINK LEC-EL is a SMARC module based on Intel Atom® x6000 series (e.g., x6425E, x6414RE) processors (formerly Elkhart Lake) with integrated Intel® UHD graphics and high-speed interfaces. It supports up to 16GB LPDDR4 memory and is available with rugged operating temperature range and low power envelope, making it ideal for mission-critical fanless edge computing applications that require safety and reliability at all times.

# The SMARC Form Factor

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor Computer on Module definition targeting applications that require low power and high performance at low costs. Typically, under 6W, the modules often utilize ARM and other alternative low-power option CPUs, and are used in many familiar handheld devices, such as tablet computers and smart phones.

Two module sizes are defined in SMARC: 82 mm x 50 mm and 82 mm x 80 mm.

The module PCBs have 314 edge fingers that mate with a low-profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321-pin connector, with 7 pins used by the key).

SMARC modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the module. Modules are used with application-specific carrier boards that implement other features such as audio codecs, touch controllers, wireless devices, etc.

The modular approach allows scalability, faster time to market and upgradability while still maintaining low costs, low power, and small physical size.

![The image displays a logo consisting of the text 'SGeT' set against a white background. The letters 'S,' 'G,' and 'T' are uppercase and colored a bright lime green. The letter 'e' is lowercase, colored magenta, and is positioned between the 'G' and 'T,' overlapping the 'T'.](.smarc-lec-el-50m-72513-1050-15/e1849a62adc019c5c9a41dba19952a9ec0c2493217280fd771202e3a8c1afb9a.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html

# 2. Specifications

# Core System

# SoC

6th Gen Intel® Atom® series (formerly Elkhart Lake)

 x6211E
x6413E
x6425E
x6200FE
x6414RE
x6425RE

Standard embedded and industrial grade parts

# L2 Cache

1.5 MB I2 Cache, 4MB LLC Cache

# Memory

2/4/8/16 GB LPDDR4 at 4266 MT/s memory down type with IBECC

# Video

LEC-EL standard display supports 4K capable HDMI 2.0a, 4K DP++ and single/dual channel 24-bit LVDS

![The image displays a red square with rounded corners and a thin white border. Inside the red background is a large white capital letter 'E' positioned above a white equals sign.](.smarc-lec-el-50m-72513-1050-15/24644437d26629688b9d181fb8c41bb9851ed70a8b5209f730ba512af3f90ddd.jpg)

Note : The LVDS output is derived from an eDP to LVDS bridge. As build option, the bridge can be removed.

# GPU Core:

Intel Gen11LP UHD Graphics

# HDMI

HDMI 2.0a supporting up to 4K (4096 x 2160 at 60Hz)

# LVDS

LVDS single/dual channel 24-bit at max. 1920x 1200 over eDP to LVDS bridge

# MIPI DSI (option)

DSI 4 lanes at max. 1080p@60fps display output (build option multiplexed with LVDS signal)

# Audio

HDA audio interface (used by default)

![The image displays a red icon representing a document or file. It features a thick red outline shaped like a page with a folded bottom-right corner. Inside the outline are two horizontal red lines, resembling text or a list.](.smarc-lec-el-50m-72513-1050-15/c0d21a830d5b8f98d73085ebe9821ea162653c7593de0d29d916d9d5200ef259.jpg)

Note: Audio codec is located on carrier.

# Dual Ethernet

# Primary LAN (GbE0) GPY

SoC-embedded RGMII Ethernet controller with optional IEEE-1588 PTP (Precision Time Protocol) Supports 2.5Gb data transfer rates, both full-duplex and half-duplex

# Secondary LAN (GbE1) GPY

SoC-embedded RGMII Ethernet controller with optional IEEE-1588 PTP (Precision Time Protocol) Supports 2.5Gb data transfer rates, both full-duplex and half-duplex

# Extension busses

# PCIe

4x PCI Express Gen3 x1 interfaces (configurable to one x4, two x2 or one x2 + two x1 or four x1)

# USB

2x USB 3.1, 6x USB 2.0, no OTG support

# UART

4x UART interface SER0, 2(Tx/Rx/CTS/RTS) and SER1, SER3 (Tx/Rx)
7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)

![The image features a red outline icon of a document or page. It is a square shape with a folded corner on the bottom right side. Inside the outline, there are two horizontal red lines positioned near the center, resembling text on a page.](.smarc-lec-el-50m-72513-1050-15/be5f5fceee657305782941a3899d3dbf41de1928ed0cb3fb27dcac70a468d34c.jpg)

Note : SER0 and SER1 can be used as legacy ports while SER2 and SER3 will require additional drivers. Only SER2 and SER3 support 4Mbps. For SER0 and SER1, please contact your ADLINK representative.

# CAN bus

2x CAN2.0B only or mixed CAN2.0B and CAN FB mode, data bit rate up to 8 Mbps, only supported on Linux

# SPI

1x SPI, 1x eSPI

SPI0: FSPI interface for BIOS and TPM)

SPI1: eSPI interface for flash device

# HDA / I2S

1x High-Definition Audio (HDA) as default or 1x I2S on I2S2 port

# I2C

4x I2C interfaces

Supports 7-bit and 10-bit address modes

Software programmable clock frequency:

100 kbit/s in Standard-mode
400 kbit/s in Fast-mode
1 Mbit/s in Fast-mode Plus

# GPIO

14x GPIO with interrupt (GPIO4 used as HAD\_RST# by default)

# System Storage

# SDIO

1x SDIO (4-bit) compatible up to version 3.0.

# eMMC

Soldered on module 8, 16, 32, 64, 128 GB (build option) either standard or at -40 to $8 5 ^ { \circ } \mathsf { C }$ temperature range

Compatible with eMMC specification 4.51 and higher

# Board Controller

BMC lite for power sequence

SEMA BMC Error Code

<table><tr><td>Exception Code</td><td>Error Code</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_VIN</td></tr><tr><td>3</td><td>NO_SDM_RESIN_N</td></tr><tr><td>4</td><td>NO_SDM_RESIN_N</td></tr></table>

# SEMA® Board Management Controller

Voltage/current monitoring, boot configuration, logistics, forensic information, flat panel control, watchdog timer

# Debug Header

30-pin multipurpose flat cable connector for use with optional DB-30 debug module

Provides JTAG, BMC access; UART, power test points; diagnostic LEDs, Power, Reset, Boot configuration

# BIOS

Single BIOS chip, UEFI BIOS

# Power

# Supply Voltage

5V +/- 5%

# Power Sequencing

VDD\_IN is the first power domain to be turned on by the carrier circuit during power-up. Other circuit components on the carrier, which are galvanically coupled to the module, shall not be supplied to avoid feedback. From the moment VDD\_IN is stable — recognizable by VIN\_PWR\_BAD# de-asserted — the module takes over control of the power sequencing. As soon as the module reaches the next system state standby, CARRIER\_PWR\_ON signals the carrier to switch on all its standby voltages. No feedback is provided to allow the carrier to signal Power OK to the modules power state machine. When the state Runtime is reached, the module de-asserts CARRIER\_STBY#. The carrier then switches on the remaining rails.

# Mechanical and Environmental

# Form Factor

SGET SMARC Specifications v2.1.1

# Dimension

SMARC small size module, 82mm x 50mm

# Operating Temperature

Standard: 0°C to 60°C

Rugged: -40°C to 85°C (optional)

# Humidity

5-90% RH operating, non-condensing

5-95% RH storage (and operating with conformal coating)

# Shock and Vibration

IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I,

Condition A and Method 214A, Table 214-I, Condition D

# 3. Block Diagram

![**Central Processor Block**\n*   **Label:** (Elkhart Lake) Intel Atom® 6th Gen.\n\n**Left Interface Block (Grey Background)**\n*   4K HDMI / DP\n*   4K DP++ / HDMI\n*   LVDS/DSI/eDP\n*   USB 0, 1, 2, 3, 4, 5\n*   USB 2, 3\n*   SATA Gen3\n*   LAN0\n*   LAN1\n*   PCIe A, B, C, D\n*   CAN0\n*   CAN1\n*   14x GPIO\n*   SMB\n*   SDIO\n*   SER 2/3\n*   eSPI\n*   SER 0/1\n*   BOOT Select\n*   SPI\n*   4x I2C\n*   SDIO\n*   HDA/I2S\n*   Power Management\n\n**Right Peripheral/Memory Block**\n*   LPDDR4 x32 (x4 blocks)\n*   eMCC 16/32/64GB\n*   TPM 2.0\n*   Crypto ATECC608\n*   30-pin debug\n\n**Intermediary Blocks (Blue Boxes)**\n*   DSI option (Dashed box label)\n*   NXP PTN3460\n*   GPY211 (x2 blocks)\n*   SX1509\n*   BMC/EC IT5121\n*   SPI BIOS\n\n**Connections**\n*   **Video:**\n    *   4K HDMI / DP connects to DDI2.\n    *   4K DP++ / HDMI connects to DDI1.\n    *   LVDS/DSI/eDP connects to NXP PTN3460 (within DSI option), which connects to DDI0.\n*   **USB:**\n    *   USB 0, 1, 2, 3, 4, 5 connects to 6x USB 2.0 HOST.\n    *   USB 2, 3 connects to 2x USB 3.x HOST.\n*   **Storage:**\n    *   SATA Gen3 connects to SATA0.\n    *   SPI connects to SPI BIOS, which connects to FSPI.\n*   **Network:**\n    *   LAN0 connects to GPY211, which connects to SGMII0.\n    *   LAN1 connects to GPY211, which connects to SGMII1.\n*   **PCIe:**\n    *   PCIe A, B, C, D connects to 4x PCIe1Gen3.\n*   **GPIO/CAN/SMB:**\n    *   CAN0 and CAN1 connect to SX1509, which connects to CAN and CAN.\n    *   14x GPIO connects to SX1509, which connects to GPIO INT.\n    *   SMB connects to SX1509, which connects to SMB.\n*   **Serial/Debug:**\n    *   SDIO connects to SDIO.\n    *   SER 2/3 connects to HSUART.\n    *   eSPI, SER 0/1, and BOOT Select connect to BMC/EC IT5121, which connects to eSPI.\n*   **Bus/Audio:**\n    *   4x I2C connects to I2C.\n    *   SDIO connects to SDIO.\n    *   HDA/I2S connects to HDA/I2S.\n    *   Power Management connects to PM.\n*   **Right Side Connections:**\n    *   The central processor connects to four LPDDR4 x32 blocks.\n    *   The central processor connects to eMCC 16/32/64GB.\n    *   The central processor connects via SPI to TPM 2.0.\n    *   The central processor connects via I2C to Crypto ATECC608.\n    *   The central processor connects to 30-pin debug.](.smarc-lec-el-50m-72513-1050-15/eeec4560d4b6663051b834946cca92e695da73f1dd9c25edc0ea196d7ba0f4cd.jpg)

Figure 1 – Module function diagram

# 4. Pinout and Signal Descriptions

# Pin Summary

The below tables are a list of all signal pins on the MXM 3 connector in the standard specification of SMARC 2.1.

![Top Side\nP1 P74 P75 P156\nKey](.smarc-lec-el-50m-72513-1050-15/c015edce83e36b809555992615c3a20038cccb82853d036e4c1714aafb37ef56.jpg)

![Bottom Side\nS156 S76 S75 S1\nKey](.smarc-lec-el-50m-72513-1050-15/aa16fec3968bfee08e603cce537bd9ecb6653b80eddc4b540e7437df6a211c7c.jpg)

Figure 2 – Module top/botom side pin numbering

# 4.2 Signal Terminology Descriptions

Meaning of the terms used for signal description tables. Signals described in the specification but not supported on the LEC-EL are marked with strikethrough STRIKETHROUGH

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the module</td></tr><tr><td>O</td><td>Output from the module</td></tr><tr><td>O OD</td><td>Open drain output from the module</td></tr><tr><td>I OD</td><td>Open drain input to the module, with mandatory PU (pull up) on module</td></tr><tr><td>OD</td><td>Open drain</td></tr><tr><td>I/O</td><td>Bi-directional Input/Output</td></tr><tr><td>PU</td><td>PU (pull-up) resistor on module</td></tr><tr><td>PD</td><td>PD (pull-down) resistor on module</td></tr><tr><td>VDD_IN</td><td>Main power source from carrier to module</td></tr><tr><td>CMOS</td><td>Logic input or output</td></tr><tr><td>GBE MDI</td><td>Differential analog signaling for Gigabit Media Dependent Interface</td></tr><tr><td>LVDS DP</td><td>Low Voltage Differential Signal for DisplayPort interface</td></tr><tr><td>LVDS D-PHY</td><td>Low Voltage Differential Signal for MIPI CSI-2 cameras and DSI displays</td></tr><tr><td>LVDS M-PHY</td><td>Low Voltage Differential Signal for MIPI CSI-3 cameras</td></tr><tr><td>LVDS LCD</td><td>Low Voltage Differential Signal for LCD displays</td></tr><tr><td>LVDS PCIE</td><td>Low Voltage Differential Signal for PCIe</td></tr><tr><td>LVDS SATA</td><td>Low Voltage Differential Signal for SATA</td></tr><tr><td>TMDS HDMI</td><td>Transition Minimized Differential Signal for HDMI displays</td></tr><tr><td>USB</td><td>DC coupled differential signaling for traditional (non-Superspeed) USB signals</td></tr><tr><td>USB SS</td><td>Differential signal for SuperSpeed USB signals</td></tr><tr><td>USB VBUS 5V</td><td>5V tolerant input for USB VBUS detection</td></tr><tr><td>3.3V</td><td>3.3V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>1.8V</td><td>1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>3.3Vsb</td><td>3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>1.8Vsb</td><td>1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr></table>

# 4.3 Signal Description by function

# 4.3.1 The First Display Interface

The first display interface is a group of 30-pins that is split into a channel 0 and channel 1. The SMARC specification allows support for dual channel LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display type such as DSI and eDP is also permitted. Below tables show which display ports are supported on this particular module

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td>S125</td><td>LVDS0_0+</td><td>DSI0_D0+</td><td>eDP0_TX0+</td></tr><tr><td>S126</td><td>LVDS0_0-</td><td>DSI0_D0-</td><td>eDP0_TX0-</td></tr><tr><td>S128</td><td>LVDS0_1+</td><td>DSI0_D1+</td><td>eDP0_TX1+</td></tr><tr><td>S129</td><td>LVDS0_1 -</td><td>DSI0_D1-</td><td>eDP0_TX1-</td></tr><tr><td>S131</td><td>LVDS0_2+</td><td>DSI0_D2+</td><td>eDP0_TX2+</td></tr><tr><td>S132</td><td>LVDS0_2-</td><td>DSI0_D2-</td><td>eDP0_TX2-</td></tr><tr><td>S137</td><td>LVDS0_3+</td><td>DSI0_D3+</td><td>eDP0_TX3+</td></tr><tr><td>S138</td><td>LVDS0_3-</td><td>DSI0_D3-</td><td>eDP0_TX3-</td></tr><tr><td>S134</td><td>LVDS0_CK+</td><td>DSI0_CLK+</td><td>eDP0_AUX+</td></tr><tr><td>S135</td><td>LVDS0_CK-</td><td>DSI0_CLK-</td><td>eDP0_AUX-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td></tr><tr><td>S144</td><td></td><td>DSI0_TE</td><td>eDP0_HPD</td></tr></table>

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td>S111</td><td>LVDS1_0+</td><td>DSI1_D0+</td><td>eDP1_TX0+</td></tr><tr><td>S112</td><td>LVDS1_0-</td><td>DSI1_D0-</td><td>eDP1_TX0-</td></tr><tr><td>S114</td><td>LVDS1_1+</td><td>DSI1_D1+</td><td>eDP1_TX1+</td></tr><tr><td>S115</td><td>LVDS1_1 -</td><td>DSI1_D1-</td><td>eDP1_TX1-</td></tr><tr><td>S117</td><td>LVDS1_2+</td><td>DSI1_D2+</td><td>eDP1_TX2+</td></tr><tr><td>S118</td><td>LVDS1_2-</td><td>DSI1_D2-</td><td>eDP1_TX2-</td></tr><tr><td>S120</td><td>LVDS1_3+</td><td>DSI1_D3+</td><td>eDP1_TX3+</td></tr><tr><td>S121</td><td>LVDS1_3-</td><td>DSI1_D3-</td><td>eDP1_TX3-</td></tr><tr><td>S108</td><td>LVDS1_CK+</td><td>DSI1_CLK+</td><td>eDP1_AUX+</td></tr><tr><td>S109</td><td>LVDS1_CK-</td><td>DSI1_CLK-</td><td>eDP1_AUX-</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td></tr><tr><td>S113</td><td></td><td>DSI1_TE</td><td>eDP1_HPD</td></tr></table>

<table><tr><td>S139</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td></tr></table>

![The image displays a simple icon resembling a document or file. It features a white square with a thick red border. Inside the square, there are two horizontal red lines, suggesting text. The bottom right corner of the square is folded over (a 'dog-ear' fold), outlined in red. There is no text in the image.](.smarc-lec-el-50m-72513-1050-15/4c84d03f8b724906fd7aa8a991983d69bfc1a3236b9fc34014410dabfb2aeb2f.jpg)

# Note :

1. LVDS0/LVDS1 are standard supported through a eDP to LVDS bridge on the module
2. eDP or DSI can be used by build option, disabling the LVDS0/LVDS1 ports.

# 4.3.1.1 LVDS0/LVDS1 mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>LVDS0_0+</td><td>S125</td><td rowspan="8">Primary LVDS Channel Differential Pair Data Lines</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">100 ohm differential termination across the differential pairs at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS0_0-</td><td>S126</td></tr><tr><td>LVDS0_1+</td><td>S128</td></tr><tr><td>LVDS0_1 -</td><td>S129</td></tr><tr><td>LVDS0_2+</td><td>S131</td></tr><tr><td>LVDS0_2-</td><td>S132</td></tr><tr><td>LVDS0_3+</td><td>S137</td></tr><tr><td>LVDS0_3-</td><td>S138</td></tr><tr><td>LVDS0_CK+</td><td>S134</td><td rowspan="2">Primary LVDS Channel Differential Pair Clock Lines</td><td rowspan="2">O LVDS</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">100 ohm differential termination across the differential pair at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS0_CK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary LVDS Channel Power Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary LVDS Channel Backlight Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary LVDS Channel Brightness Control</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr><tr><td colspan="8"></td></tr><tr><td>LVDS1_0+</td><td>S111</td><td rowspan="8">Secondary LVDS Channel Differential Pair Data Lines</td><td rowspan="8">O LVDS</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">100 ohm differential termination across the differential pairs at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS1_0-</td><td>S112</td></tr><tr><td>LVDS1_1+</td><td>S114</td></tr><tr><td>LVDS1_1 -</td><td>S115</td></tr><tr><td>LVDS1_2+</td><td>S117</td></tr><tr><td>LVDS1_2-</td><td>S118</td></tr><tr><td>LVDS1_3+</td><td>S120</td></tr><tr><td>LVDS1_3-</td><td>S121</td></tr><tr><td>LVDS1_CK+</td><td>S108</td><td rowspan="2">Secondary LVDS Channel Differential Pair Clock Lines</td><td rowspan="2">O LVDS</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">100 ohm differential termination across the differential pair at the endpoint of the signal path, usually on the display assembly.</td></tr><tr><td>LVDS1_CK-LCD1_VDD_EN</td><td>S109S116</td></tr><tr><td></td><td></td><td>Secondary LVDS Channel Power Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>Active highOnly in use, when two separate LVDS ports are supported, please check Module user manual</td></tr><tr><td>LCD1_BKLT_EN</td><td>S107</td><td>Secondary LVDS Channel Backlight Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>Active highOnly in use, when two separate LVDS ports are supported, please check Module user manual</td></tr><tr><td>LCD1_BKLT_PWM</td><td>S122</td><td>Secondary LVDS Channel Brightness Control</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>Through pulse width modulation (PWM)only in use, when two separate LVDS ports are supported, please check Module user manual</td></tr><tr><td colspan="8"></td></tr><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if two LVDS panels are used</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>Possible conflict if two LVDS panels are used</td></tr></table>

# 4.3.1.2 eDP mode (build option)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>eDP0_TX0+</td><td>S125</td><td rowspan="8">Primary 4-Lane eDP Differential Pair Data Lines</td><td rowspan="8">O DP</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">AC coupled off Module100 nF DC blocking capacitors shall be placed on the Carrier.</td></tr><tr><td>eDP0_TX0-</td><td>S126</td></tr><tr><td>eDP0_TX1+</td><td>S128</td></tr><tr><td>eDP0_TX1-</td><td>S129</td></tr><tr><td>eDP0_TX2+</td><td>S131</td></tr><tr><td>eDP0_TX2-</td><td>S132</td></tr><tr><td>eDP0_TX3+</td><td>S137</td></tr><tr><td>eDP0_TX3-</td><td>S138</td></tr><tr><td>eDP0_AUX+</td><td>S134</td><td rowspan="2">Primary Bidirectional Channel used for Link Management and Device Control</td><td rowspan="2">I/O DP</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off Module</td></tr><tr><td>eDP0_AUX-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary Panel Power Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary Panel Backlight Enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary Panel Brightness Control</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr><tr><td>eDP0_HPD</td><td>S144</td><td>Detection of Hot Plug / Unplug of Primary eDP Display and Notification of the Link Layer</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>PD 1M</td><td>Module must tolerate high level in stand-by mode</td></tr></table>

4.3.2 Second Display Interface

<table><tr><td>Pin #</td><td>HDMI signal names</td><td>DP++ signal names</td></tr><tr><td>P92</td><td>HDMI_D2+</td><td>DP1_LANE0+</td></tr><tr><td>P93</td><td>HDMI_D2-</td><td>DP1_LANE0-</td></tr><tr><td>P95</td><td>HDMI_D1+</td><td>DP1_LANE1+</td></tr><tr><td>P96</td><td>HDMI_D1-</td><td>DP1_LANE1-</td></tr><tr><td>P98</td><td>HDMI_D0+</td><td>DP1_LANE2+</td></tr><tr><td>P99</td><td>HDMI_D0-</td><td>DP1_LANE2-</td></tr><tr><td>P101</td><td>HDMI_CK+</td><td>DP1_LANE3+</td></tr><tr><td>P102</td><td>HDMI_CK-</td><td>DP1_LANE3-</td></tr><tr><td>S105</td><td>HDMI_CTRL_CK</td><td>DP1_AUX+</td></tr><tr><td>S106</td><td>HDMI_CTRL_DAT</td><td>DP1_AUX-</td></tr><tr><td>P104</td><td>HDMI_HPD</td><td>DP1_HPD</td></tr><tr><td></td><td></td><td></td></tr></table>

# 4.3.2.1 HDMI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>HDMI_D2+</td><td>P92</td><td rowspan="6">HDMI port, differential pair data lines</td><td rowspan="6">O TMDS HDMI</td><td rowspan="6"></td><td rowspan="6">Runtime</td><td rowspan="6"></td><td rowspan="6">AC coupled off module</td></tr><tr><td>HDMI_D2-</td><td>P93</td></tr><tr><td>HDMI_D1+</td><td>P95</td></tr><tr><td>HDMI_D1-</td><td>P96</td></tr><tr><td>HDMI_D0+</td><td>P98</td></tr><tr><td>HDMI_D0-</td><td>P99</td></tr><tr><td>HDMI_CK+</td><td>P101</td><td rowspan="2">HDMI port, differential pair clock lines</td><td rowspan="2">O TMDS HDMI</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off module</td></tr><tr><td>HDMI_CK-</td><td>P102</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 100K</td><td>Level shifter FET and 5V PU resistor shall be placed between the Module and the HDMI connector.Stronger pull-up is demanded to the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete Carrier pull-ups are used, the value depends on the individual carrier board implementation.</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>I/O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 100K</td><td>Level shifter FET and 5V PU resistor shall be placed between the Module and the HDMI connector.Stronger pull-up is demanded to the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete Carrier pull-ups are used, the value depends on the individual carrier boardImplementation.</td></tr><tr><td>HDMI_HPD</td><td>P104</td><td>HDMI Hot plug active high detection signal that serves as an interrupt request</td><td>I CMOS</td><td>1.8V</td><td>runtime</td><td>PD 1M</td><td>Module must tolerate high level in stand-by mode</td></tr></table>

# 4.3.3 MIPI Camera support

# 4.3.3.1 MIPI CSI0

This design does not support CSI

4.3.4 HDA (Audio)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>HDA_SYNC / I2S2_LRCK</td><td>S50</td><td>High Definition Audio Sample synchronization clock to codec</td><td>I/O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td><td rowspan="5">SMARC HDA Audio signalling supports 1.5V or 1.8V.Please check with your module vendor if 1.5V or 1.8V is supported and use an audio codec that is capable to support the regarding I/O voltage. This specification ignores the discrepancy between the 1.5V and 1.8V signalling, as the chance of damage in mismatched systems is negligible.The SMARC HD Audio pins are shared with the I2S2 pins, which are defined to be 1.8V only.</td></tr><tr><td>HDA_SDO / I2S2_SDOUT</td><td>S51</td><td>High Definition Audio data out to codec</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_SDI / I2S2_SDIN</td><td>S52</td><td>High Definition Audio data in from codec</td><td>I/O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_CK / I2S2_CK</td><td>S53</td><td>High Definition Audio clock to codec</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr><tr><td>HDA_RST# / GPIO4</td><td>P112</td><td>High Definition Audio reset output to codec, low active.</td><td>O CMOS</td><td>1.8V / 1.5V</td><td>Runtime</td><td></td></tr></table>

![The image displays a red icon resembling a document or page. It features a thick red outline forming a square shape with a folded bottom-right corner. Inside the white interior, there are two horizontal red bars centered within the space.](.smarc-lec-el-50m-72513-1050-15/0547ce8627a34b5bcd9075a58cbea5fd4b227c7e44286fb8508f5492b67796a3.jpg)
Note: Support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification

4.3.5 USB ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>USB0+USB0-</td><td>P60P61</td><td>USB differential data pairs for port 0</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB0_EN_OC#</td><td>P62</td><td>USB over-current sense for port 0</td><td>I/O OD CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB0_VBUS_DET</td><td>P63</td><td>USB port 0 host power detection, when this port is used as a device.</td><td>↓USB-VBUS 5V</td><td>USB-VBUS 5V</td><td>Standby</td><td></td><td>Can be connected to a USB client port VBUS pin</td></tr><tr><td>USB0_OTG_ID</td><td>P64</td><td>Input pin to announce OTG device insertion on USB 2.0 port</td><td>↓CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB1+USB1-</td><td>P65P66</td><td>USB differential data pairs for port 1</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB1_EN_OC#</td><td>P67</td><td>USB over-current sense for port 1</td><td>I/O OD CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB2+USB2-</td><td>P69P70</td><td>USB differential data pairs for port 2</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB2_SSRX+USB2_SSRX-</td><td>S74S75</td><td>Receive signal differential pairs for SuperSpeed on port 2</td><td>IUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for RX pairs are on the USB Device</td></tr><tr><td>USB2_SSTX+USB2_SSTX-</td><td>S71S72</td><td>Transmit signal differential pairs for SuperSpeed on port 2</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for TX pairs are on the Module</td></tr><tr><td>USB2_EN_OC#</td><td>P71</td><td>USB over-current sense for port 2</td><td>I/O OD CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB3+USB3-</td><td>S68S69</td><td>USB differential data pairs for port 3</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_SSRX+USB3_SSRX-</td><td>S65S66</td><td>Receive signal differential pairs for SuperSpeed on port 3</td><td>IUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for RX pairs are on the USB Device</td></tr><tr><td>USB3_SSTX+USB3_SSTX-</td><td>S62S63</td><td>Transmit signal differential pairs for SuperSpeed on port 3</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>Coupling caps for TX pairs are on the Module</td></tr><tr><td>USB3_EN_OC#</td><td>P74</td><td>USB over-current sense for port 3</td><td>I/O ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB3_VBUS_DET</td><td>S37</td><td>USB port 3 host power detection, when this port is used as a device.</td><td>↓USB VBUS 5V</td><td>USB VBUS 5V</td><td>Standby</td><td></td><td></td></tr><tr><td>USB3_OTG_ID</td><td>S104</td><td>Input pin to announce OTG device insertion on USB 3.0 port</td><td>↓CMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB4+USB4-</td><td>S35S36</td><td>USB differential data pairs for port 4</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB4_EN_OC#</td><td>P76</td><td>USB over-current sense for port 4</td><td>I/O ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>USB5+USB5-</td><td>S59S60</td><td>USB differential data pairs for port 5</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td></td></tr><tr><td>USB5_EN_OC#</td><td>S55</td><td>USB over-current sense for port 5</td><td>I/O ODCMOS</td><td>3.3Vsb / 3.3V</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr></table>

![The image displays a red icon of a document or note with a folded bottom-right corner and two horizontal lines inside.](.smarc-lec-el-50m-72513-1050-15/5aa5df969071f8ad3bbc13d5908ebe0d62b99cc3083125d7516fccd7d8cd007f.jpg)

Note: All USB connected straight from SoC , no support for OTG

# 4.3.6 PCIe Ports

The module supports 4x PCIe Gen 3.0 ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>PCIE_A_TX+PCIE_A_TX-</td><td>P89P90</td><td>Differential PCIe link A transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_A_RX+PCIE_A_RX-</td><td>P86P87</td><td>Differential PCIe link A receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_A_REFCK+PCIE_A_REFCK-</td><td>P83P84</td><td>Differential PCIe Link A reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_RST#</td><td>P75</td><td>PCIe Port A reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_CKREQ#</td><td>P78</td><td>PCIe Port A clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on Module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_B_TX+PCIE_B_TX-</td><td>S90S91</td><td>Differential PCIe link B transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_B_RX+PCIE_B_RX-</td><td>S87S88</td><td>Differential PCIe link B receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_B_REFCK+PCIE_B_REFCK-</td><td>S84S85</td><td>Differential PCIe Link B reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_RST#</td><td>S76</td><td>PCIe Port B reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_CKREQ#</td><td>P77</td><td>PCIe Port B clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on Module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_C_TX+PCIE_C_TX-</td><td>S81S82</td><td>Differential PCIe link C transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_C_RX+PCIE_C_RX-</td><td>S78S79</td><td>Differential PCIe link C receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_C_REFCK+PCIE_C_REFCK-</td><td>P80P81</td><td>Differential PCIe Link C reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_C_RST#</td><td>S77</td><td>PCIe Port C reset output</td><td>O CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_D_TX+PCIE_D_TX-</td><td>S29S30</td><td>Differential PCIe link D transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_D_RX+PCIE_D_RX-</td><td>S32S33</td><td>Differential PCIe link D receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>PCIE_WAKE#</td><td>S146</td><td>PCIe wake up interrupt to host – common to PCIe links A, B, C, D</td><td>I ODCMOS</td><td>3.3V</td><td>Standby</td><td>PU 10k</td><td></td></tr></table>

# 4.3.7 SATA Gen 3 Ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SATA0_TX+ SATA0_TX-</td><td>P48 P49</td><td>Serial ATA channel 0, Transmit Output differential pair.</td><td>O SATA</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on Module 10 nF</td></tr><tr><td>SATA0_RX+ SATA0_RX-</td><td>P51 P52</td><td>Serial ATA channel 0, Receive Input differential pair.</td><td>I SATA</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on Module 10 nF</td></tr><tr><td>SATA_ACT#</td><td>S54</td><td>SATA activity indicator</td><td>O OD CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr></table>

# 4.3.8 LAN ports

# 4.3.8.1 First LAN port

The first LAN port is derived from the SoC’s RGMII interface

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td><td></td></tr><tr><td>GBE0_MDI0+</td><td>P30</td><td>Differential Pair Signals for External Transformer</td><td>I/IO GBE</td><td></td><td>Standby</td><td></td><td>Gigabit Ethernet Controller 0: Media Dependent Interface</td><td></td></tr><tr><td>GBE0_MDI0-</td><td>P29</td><td>Carrier Series Termination: Magnetics Module</td><td>MDI</td><td></td><td></td><td></td><td rowspan="3" colspan="2">Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td></tr><tr><td>GBE0_MDI1+</td><td>P27</td><td>appropriate for 10/100/1000 GBE transceivers</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE0_MDI1-</td><td>P26</td><td>Carrier Parallel Termination:</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE0_MDI2+</td><td>P24</td><td>Secondary side center tap terminations</td><td></td><td></td><td></td><td></td><td>1000 100 10 _</td><td></td></tr><tr><td>GBE0_MDI2-</td><td>P23</td><td>appropriate for Gigabit Ethernet</td><td></td><td></td><td></td><td></td><td>MDI[0]+/- B1_DA+/- TX+/- TX+/-</td><td></td></tr><tr><td>GBE0_MDI3+</td><td>P20</td><td>implementations</td><td></td><td></td><td></td><td></td><td>MDI[1]+/- B1_DB+/- RX+/- RX+/-</td><td></td></tr><tr><td>GBE0_MDI3-</td><td>P19</td><td></td><td></td><td></td><td></td><td></td><td>MDI[2]+/- B1_DC+/-</td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>MDI[3]+/- B1_DD+/-</td><td></td></tr><tr><td>GBE0_LINK100#</td><td>P21</td><td>Link Speed Indication LED for GBE0 10/100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td><td></td></tr><tr><td>GBE0_LINK1000#</td><td>P22</td><td>Link Speed Indication LED for GBE0 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td><td></td></tr><tr><td>GBE0_LINK_ACT#</td><td>P25</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td><td></td></tr><tr><td>GBE0_CTREF</td><td>P28</td><td>Center-Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td></td><td></td><td></td></tr><tr><td>GBE0_SDP</td><td>P6</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td></td><td></td><td></td></tr></table>

# 4.3.8.2 Second LAN port

The second LAN port is derived from the SOCs RGMII interface

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td><td></td></tr><tr><td>GBE1_MDI0+</td><td>S17</td><td>Differential Pair Signals for External Transformer</td><td>I/IO GBE</td><td></td><td>Standby</td><td></td><td>Gigabit Ethernet Controller 1: Media Dependent Interface</td><td></td></tr><tr><td>GBE1_MDI0-</td><td>S18</td><td>Carrier Series Termination: Magnetics Module</td><td>MDI</td><td></td><td></td><td></td><td rowspan="3" colspan="2">Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:</td></tr><tr><td>GBE1_MDI1+</td><td>S20</td><td>appropriate for 10/100/1000 GBE transceivers</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE1_MDI1-</td><td>S21</td><td>Carrier Parallel Termination:</td><td></td><td></td><td></td><td></td></tr><tr><td>GBE1_MDI2+</td><td>S23</td><td>Secondary side center tap terminations</td><td></td><td></td><td></td><td></td><td>1000 100 10 _</td><td></td></tr><tr><td>GBE1_MDI2-</td><td>S24</td><td>appropriate for Gigabit Ethernet</td><td></td><td></td><td></td><td></td><td>MDI[0]+/- B1_DA+/- TX+/- TX+/-</td><td></td></tr><tr><td>GBE1_MDI3+</td><td>S26</td><td>implementations</td><td></td><td></td><td></td><td></td><td>MDI[1]+/- B1_DB+/- RX+/- RX+/-</td><td></td></tr><tr><td>GBE1_MDI3-</td><td>S27</td><td></td><td></td><td></td><td></td><td></td><td>MDI[2]+/- B1_DC+/-</td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td>MDI[3]+/- B1_DD+/-</td><td></td></tr><tr><td>GBE1_LINK100#</td><td>S19</td><td>Link Speed Indication LED for GBE1 10/100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td><td></td></tr><tr><td>GBE1_LINK1000#</td><td>S22</td><td>Link Speed Indication LED for GBE1 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td><td></td></tr><tr><td>GBE1_LINK_ACT#</td><td>S31</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current $^{1}$ </td><td></td></tr><tr><td>GBE1_CTREF</td><td>S28</td><td>Center-Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td></td><td></td><td></td></tr><tr><td>GBE1_SDP</td><td>P5</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td></td><td></td><td></td></tr></table>

![The image displays a red icon resembling a document or piece of paper. It features a thick red outline with the bottom right corner folded over. Inside the outline, there are two horizontal red lines centered vertically, representing text.](.smarc-lec-el-50m-72513-1050-15/9989b3140feca01a2c4b2ce2dbd6b27de978102e13463ff6e5acf52664481a3c.jpg)

# Note:

1. Both LAN interfaces use a GPY 2.5Gb Ethernet PHY, there is also a 1Gb pin-compatible part.
2. LAN LEDs are inactive when the LAN transfer rate is 2.5Gb.

4.3.9 SDIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SDIO_D0</td><td>P39</td><td rowspan="4">SDIO Data lines. These signals operate in push-pull mode.</td><td rowspan="4">I/O CMOS</td><td rowspan="4">1.8V or 3.3V</td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4">SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_D1</td><td>P40</td></tr><tr><td>SDIO_D2</td><td>P41</td></tr><tr><td>SDIO_D3</td><td>P42</td></tr><tr><td>SDIO_WP</td><td>P33</td><td>SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CMD</td><td>P34</td><td>SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td>SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_CD#</td><td>P35</td><td>SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CK</td><td>P36</td><td>SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SDIO_PWR_EN</td><td>P37</td><td>SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>should be driven low in STB Mode by the module</td></tr></table>

# 4.3.10 SPI & ESPI

4.3.11 SPI0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI0_CS0#</td><td>P43</td><td>SPI0 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>This signal can be used to select carrier SPI as boot device</td></tr><tr><td>SPI0_CS1#</td><td>P31</td><td>SPI0 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_CK</td><td>P44</td><td>SPI0 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_DIN</td><td>P45</td><td>SPI0 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MISO</td></tr><tr><td>SPI0_DO</td><td>P46</td><td>SPI0 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MOSI</td></tr><tr><td colspan="8"></td></tr><tr><td>SPI1_CS0#</td><td>P54</td><td>SPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_CS1#</td><td>P55</td><td>SPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_CK</td><td>P56</td><td>SPI1 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_DIN</td><td>P57</td><td>SPI1 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr><tr><td>SPI1_DO</td><td>P58</td><td>SPI1 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>See ESPI</td></tr></table>

![The image displays a red icon resembling a document or file. It features a red square shape with a folded bottom-right corner. Inside the red shape, two horizontal lines are centered, suggesting text on a page.](.smarc-lec-el-50m-72513-1050-15/36e34ddf80a0f85c985c3ded743c7ecf6a440a3b07be92d9995ef7302e255933.jpg)

Note: SPI bus only supports FSPI mode on LEC-EL.

4.3.12 ESPI

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>ESPI_CS0#</td><td>P54</td><td>ESPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CS1#</td><td>P55</td><td>ESPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_CK</td><td>P56</td><td>ESPI Master Clock output</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>ESPI_RESET#</td><td>S58</td><td>ESPI Reset</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>Reset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves</td></tr><tr><td>ESPI_ALERT0#</td><td>S43</td><td rowspan="2">ESPI ALERT</td><td rowspan="2">I OD CMOS</td><td rowspan="2">1.8V</td><td rowspan="2">Standby</td><td rowspan="2"></td><td rowspan="2">This pin is used by eSPI slave to request service from eSPI.master.Alert# is an open-drain output from the slave.This pin is optional for Single Master-Single Slave configuration where I/O[1] can be used to signal the Alert event.</td></tr><tr><td>ESPI_ALERT1#</td><td>S44</td></tr><tr><td>ESPI_IO_0</td><td>P58</td><td rowspan="4">ESPI Master Data Input / Output.</td><td rowspan="4">I/O CMOS</td><td rowspan="4">1.8V</td><td rowspan="4">Standby</td><td rowspan="4"></td><td rowspan="4">ESPI_IO_0 can also be used as SPI1_DO (MOSI)ESPI_IO_1 can also be used as SPI1_DIN (MISO)In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO).</td></tr><tr><td>ESPI_IO_1</td><td>P57</td></tr><tr><td>ESPI_IO_2</td><td>S56</td></tr><tr><td>ESPI_IO_3</td><td>S57</td></tr></table>

# 4.4 General Purpose I2C

The SMARC specification supports a total of 6 different I2C busses on its pinout. Most of these busses are designated for specific functions such as I2C for camera management, I2C for EDID on HDMI, LVDS panels or I2C for PMIC. Only one I2C bus is marked as General purpose

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>I2C_GP_DAT</td><td>S49</td><td>General purpose I2C data signal</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_GP_CK</td><td>S48</td><td>General purpose I2C clock signal</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr></table>

Most of the other I2C busses are described in their designated function tables as opposed to a combined list.

Below is an overview of all I2C busses and where to find them.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>Where to find</td></tr><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>LVDS / DSI / eDP tables</td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>LVDS / DSI / eDP tables</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>HDMI table</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>HDMI table</td></tr><tr><td>I2C_CAM0_DAT</td><td>S7</td><td>I2C data for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM0_CK</td><td>S5</td><td>I2C clock for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM1_DAT</td><td>S2</td><td>I2C data for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_CAM1_CK</td><td>S1</td><td>I2C clock for serial camera data support link</td><td>MIPI CSI table</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA (SMBus for x86)</td><td>Power and System Management</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK (SMBus for x86)</td><td>Power and System Management</td></tr></table>

4.4.1 GPIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO0 / CAM0_PWR#</td><td>P108</td><td>General purpose I/O pin 0.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module.</td><td>Default use is GPIO0, alternative use is Camera 0 Power Enable - active low, through DTS</td></tr><tr><td>GPIO1 / CAM1_PWR#</td><td>P109</td><td>General purpose I/O pin 1.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>Default use is is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS</td></tr><tr><td>GPIO2 / CAM0_RST#</td><td>P110</td><td>General purpose I/O pin 2.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>Default use is GPIO2, alternative use is Camera 0 Reset - active low, through DTS</td></tr><tr><td>GPIO3 / CAM1_RST#</td><td>P111</td><td>General purpose I/O pin 3.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>Default use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS</td></tr><tr><td>GPIO4/ HDA_RST#</td><td>P112</td><td>General purpose I/O pin 4.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td>GPIO 4 support requires BOM change</td></tr><tr><td>GPIO5 / PWM_OUT</td><td>P113</td><td>General purpose I/O pin 5.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO6</td><td>P114</td><td>General purpose I/O pin 6.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO7</td><td>P115</td><td>General purpose I/O pin 7.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO8</td><td>P116</td><td>General purpose I/O pin 8.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO9</td><td>P117</td><td>General purpose I/O pin 9.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO10</td><td>P118</td><td>General purpose I/O pin 10.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO11</td><td>P119</td><td>General purpose I/O pin 11.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO12</td><td>S142</td><td>General purpose I/O pin 12</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr><tr><td>GPIO13</td><td>S123</td><td>General purpose I/O pin 13</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470K on the Module</td><td></td></tr></table>

# 4.4.2 UART

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SER0_TX</td><td>P129</td><td>Asynchronous serial data output port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RX</td><td>P130</td><td>Asynchronous serial data input port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RTS#</td><td>P131</td><td>&quot;Request to Send&quot; handshake line for port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_CTS#</td><td>P132</td><td>&quot;Clear to Send&quot; handshake line for port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>SER1_TX</td><td>P134</td><td>Asynchronous serial data output port 1</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER1_RX</td><td>P135</td><td>Asynchronous serial data input port 1</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>SER2_TX</td><td>P136</td><td>Asynchronous serial data output port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>-</td></tr><tr><td>SER2_RX</td><td>P137</td><td>Asynchronous serial data input port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>-</td></tr><tr><td>SER2_RTS#</td><td>P138</td><td>&quot;Request to Send&quot; handshake line for port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>-</td></tr><tr><td>SER2_CTS#</td><td>P139</td><td>&quot;Clear to Send&quot; handshake line for port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>-</td></tr><tr><td colspan="8"></td></tr><tr><td>SER3_TX</td><td>P140</td><td>Asynchronous serial data output port 3</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER3_RX</td><td>P141</td><td>Asynchronous serial data input port 3</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

# 4.4.3 CAN bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CAN0_TX</td><td>P143</td><td>CAN port 0 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Only supported on Linux</td></tr><tr><td>CAN0_RX</td><td>P144</td><td>CAN port 0 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Only supported on Linux</td></tr></table>

<table><tr><td>CAN1_TX</td><td>P145</td><td>CAN port 1 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Only supported on Linux</td></tr><tr><td>CAN1_RX</td><td>P146</td><td>CAN port1 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Only supported on Linux</td></tr></table>

# 4.4.4 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>TEST#</td><td>S157</td><td>Held low by Carrier to invoke Module vendor specific test function(s).</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>PU on Module. Driven by OD on Carrier</td><td>Module must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation</td></tr><tr><td>WDT_TIME_OUT#</td><td>S145</td><td>Watch-Dog-Timer Output, low active.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Driven only during runtime</td></tr></table>

4.4.5 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>BATLOW#</td><td>S156</td><td>Battery low indication to Module. Carrier to float the line in inactive state.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 10K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CARRIER_PWR_ON</td><td>S154</td><td>Carrier board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.</td><td>O CMOS</td><td>1.8Vsb / 1.8V</td><td>-</td><td></td><td>1.8Vsb is only used for signaling, not a power source to the module</td></tr><tr><td>CARRIER_STBY#</td><td>S153</td><td>The Module shall drive this signal low when the system is in a standby power state.</td><td>O CMOS</td><td>1.8Vsb / 1.8V</td><td>-</td><td></td><td></td></tr><tr><td>CHARGER_PRSNT#</td><td>S152</td><td>Held low by Carrier if DC input for battery charger is present.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CHARGING#</td><td>S151</td><td>Held low by Carrier during battery charging. Carrier to float the line when charge is complete.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>VIN_PWR_BAD#</td><td>S150</td><td>Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>Driven by OD on Carrier Module must implement PU but actual value is depended on particular module design.</td></tr><tr><td>SLEEP#</td><td>S149</td><td>Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>LID#</td><td>S148</td><td>Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>POWER_BTN#</td><td>P128</td><td>Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>RESET_OUT#</td><td>P126</td><td>General purpose reset output to Carrier board.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>RESET_IN#</td><td>P127</td><td>Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 4.7K</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>On x86 systems these serve as SMB DATA. Pulled up on module.</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>On x86 systems these serve as SMB CLK. Pulled up on module.</td></tr><tr><td>SMB_ALERT_1V8#</td><td>P1</td><td>SMBus Alert# (interrupt) signal</td><td>I OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td>only used on x86 design</td></tr></table>

# 4.4.6 Boot Select

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>BOOT_SEL0#</td><td>P123</td><td rowspan="3">Input straps determine the Module boot</td><td rowspan="3">IOD CMOS</td><td rowspan="3">1.8Vsb</td><td rowspan="3">Standby</td><td rowspan="3">PU 4.7K</td><td rowspan="3">Driven by OD on Carrier.Pulled up on module.Supports MODE 7 (default) and MODE 3.</td></tr><tr><td>BOOT_SEL1#</td><td>P124</td></tr><tr><td>BOOT_SEL2#</td><td>P125</td></tr><tr><td>FORCE_RECOV#</td><td>S155</td><td></td><td>IOD CMOS</td><td>1.8Vsb</td><td>Standby</td><td>PU 10K-</td><td>Driven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode - such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.</td></tr></table>

# 4.4.7 Power

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>Power Rail / Tolerance</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="7"></td></tr><tr><td>VDD_IN</td><td>P147, P148, P149, P150, P151, P152, P153, P154, P155, P156</td><td>Module power input voltage 4.75 min to 5.25V max</td><td>P</td><td>4.75 to 5.25V</td><td></td><td></td></tr><tr><td>GND</td><td>P2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158</td><td>Module signal and power return, and GND reference</td><td>P</td><td>Ground</td><td></td><td></td></tr><tr><td>VDD_RTC</td><td>S147</td><td>Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P</td><td>[2 to 3.25] / 3.25V</td><td></td><td></td></tr></table>

SMARC pin to controller mapping

<table><tr><td>Pin</td><td>SMARC Signal Name</td><td>Module Direction</td><td>Module Termination</td><td>Type/Tolerance</td><td>Controller</td><td>Controller Pin Name</td><td>I/O Mux default</td><td>Power Rail</td></tr><tr><td>P1</td><td>SMB_ALERT_1V8#</td><td>-</td><td>-</td><td>-</td><td></td><td></td><td>-</td><td>-</td></tr><tr><td>P2</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P3</td><td>CSI1_CK+</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_CLK_P</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P4</td><td>CSI1_CK-</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_CLK_N</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P5</td><td>GBE1_SDP</td><td>Out</td><td>-</td><td>GPIO/3.3V</td><td></td><td>SPD0</td><td></td><td></td></tr><tr><td>P6</td><td>GBE0_SDP</td><td>Out</td><td>-</td><td>GPIO/3.3V</td><td></td><td>CLK_OUT</td><td></td><td></td></tr><tr><td>P7</td><td>CSI1_RX0+</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D0_P</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P8</td><td>CSI1_RX0-</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D0_N</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P9</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P10</td><td>CSI1_RX1+</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D1_P</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P11</td><td>CSI1_RX1-</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D1_N</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P12</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P13</td><td>CSI1_RX2+</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D2_P</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P14</td><td>CSI1_RX2-</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D2_N</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P15</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P16</td><td>CSI1_RX3+</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D3_P</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P17</td><td>CSI1_RX3-</td><td>In</td><td>-</td><td>LVDS_D-PHY</td><td></td><td>MIPI_CSI2_D3_N</td><td>-</td><td>CSI_P2_VDDHA</td></tr><tr><td>P18</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P19</td><td>GBE0_MDI3-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_M_D</td><td>-</td><td>VDDIO</td></tr><tr><td>P20</td><td>GBE0_MDI3+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_P_D</td><td>-</td><td>VDDIO</td></tr><tr><td>P21</td><td>GBE0_LINK100#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>GPY</td><td>LED_1</td><td>-</td><td>VDDIO</td></tr><tr><td>P22</td><td>GBE0_LINK1000#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>GPY</td><td>LED_2</td><td>-</td><td>VDDIO</td></tr><tr><td>P23</td><td>GBE0_MDI2-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_M_C</td><td>-</td><td>VDDIO</td></tr><tr><td>P24</td><td>GBE0_MDI2+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_P_C</td><td>-</td><td>VDDIO</td></tr><tr><td>P25</td><td>GBE0_LINK_ACT#</td><td>Out/OD</td><td>-</td><td>GPIO / 3.3V</td><td>GPY</td><td>LED_0</td><td>-</td><td>VDDIO</td></tr><tr><td>P26</td><td>GBE0_MDI1-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_M_B</td><td>-</td><td>VDDIO</td></tr><tr><td>P27</td><td>GBE0_MDI1+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_P_B</td><td>-</td><td>VDDIO</td></tr><tr><td>P28</td><td>GBE0_CTREF</td><td>PWR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P29</td><td>GBE0_MD10-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_M_A</td><td>-</td><td>VDDIO</td></tr><tr><td>P30</td><td>GBE0_MD10+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>TD_P_A</td><td>-</td><td>VDDIO</td></tr><tr><td>P31</td><td>SPI0_CS1#</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P32</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P33</td><td>SDIO_WP</td><td>In</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_WP</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P34</td><td>SDIO_CMD</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_CMD</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P35</td><td>SDIO_CD#</td><td>In</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_CD</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P36</td><td>SDIO_CK</td><td>Out</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_CLK</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P37</td><td>SDIO_PWR_EN</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>GPIO1_IO12</td><td>ALT0</td><td>NVCC_GPIO1</td></tr><tr><td>P38</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P39</td><td>SDIO_D0</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_DATA0</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P40</td><td>SDIO_D1</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_DATA1</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P41</td><td>SDIO_D2</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_DATA2</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P42</td><td>SDIO_D3</td><td>Bi-Dir</td><td>-</td><td>SD2 / 3.3V</td><td>EL x6000</td><td>SD2_DATA3</td><td>ALT0</td><td>NVCC_SD2</td></tr><tr><td>P43</td><td>SPI0_CS0#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI2_SS0</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P44</td><td>SPI0_CK</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI2_SCLK</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P45</td><td>SPI0_DIN</td><td>In</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI2_MISO</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P46</td><td>SPI0_DO</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI2_MOSI</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P47</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P48</td><td>SATA_TX+</td><td>out</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P49</td><td>SATA_TX-</td><td>out</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P50</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P51</td><td>SATA_RX+</td><td>In</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P52</td><td>SATA_RX-</td><td>In</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P53</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P54</td><td>ESPI_CS0# / SPI1_CS0#</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI1_SS0</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P55</td><td>ESPI_CS1# / SPI1_CS1#</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P56</td><td>ESPI_CK / SPI1_CK</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI1_SCLK</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P57</td><td>ESPI_IO_1 / SPI1_DIN</td><td>In</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI1_MISO</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P58</td><td>ESPI_IO_0 / SPI1_DO</td><td>Out</td><td>-</td><td>SPI / 1.8V</td><td>EL x6000</td><td>ECSPI1_MOSI</td><td>ALT0</td><td>NVCC_ECSPI</td></tr><tr><td>P59</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P60</td><td>USB0+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>USB1_DP</td><td></td><td>USB1_VDD33</td></tr><tr><td>P61</td><td>USB0-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>USB1_DN</td><td></td><td>USB1_VDD33</td></tr><tr><td>P62</td><td>USB0_EN_OC#</td><td>In</td><td>PU-10K</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>GPIO1_IO13</td><td>ALT0</td><td>NVCC_GPIO1</td></tr><tr><td>P63</td><td>USB0_VBUS_DET</td><td>PWR</td><td>-</td><td>USB</td><td>EL x6000</td><td>USB1_VBUS</td><td>-</td><td>USB1_VDD33</td></tr><tr><td>P64</td><td>USB0_OTG_ID</td><td>In</td><td>-</td><td>USB</td><td>EL x6000</td><td>USB1_ID</td><td>-</td><td>USB1_VDD33</td></tr><tr><td>P65</td><td>USB1+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS3_DP</td><td>-</td><td>AVDD33</td></tr><tr><td>P66</td><td>USB1-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS3_DM</td><td>-</td><td>AVDD33</td></tr><tr><td>P67</td><td>USB1_EN_OC#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>DS3_OVRCURR</td><td>-</td><td>AVDD33</td></tr><tr><td>P68</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P69</td><td>USB2+</td><td>Bi-Dir</td><td>-</td><td>PHY</td><td>EL x6000</td><td>DS2_DP</td><td>-</td><td>AVDD33</td></tr><tr><td>P70</td><td>USB2-</td><td>Bi-Dir</td><td>-</td><td>PHY</td><td>EL x6000</td><td>DS2_DM</td><td>-</td><td>AVDD33</td></tr><tr><td>P71</td><td>USB2_EN_OC#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>DS2_OVRCURR</td><td>-</td><td>AVDD33</td></tr><tr><td>P72</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>P73</td><td>RSVD</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>P74</td><td>USB3_EN_OC#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>DS1_OVRCURR</td><td>-</td><td>AVDD33</td></tr><tr><td>P75</td><td>PCIE_A_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>SAI1_TXC</td><td>ALT5</td><td>NVCC_SAI1</td></tr><tr><td>P76</td><td>USB4_EN_OC#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>DS4_OVRCURR</td><td>-</td><td>AVDD33</td></tr><tr><td>P77</td><td>PCIE_B_CKREQ#</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>PCIE_B_CKREQ#</td><td>-</td><td>-</td></tr><tr><td>P78</td><td>PCIE_A_CKREQ#</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>PCIE_A_CKREQ#</td><td>-</td><td>-</td></tr><tr><td>P79</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+</td><td>Out</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P81</td><td>PCIE_C_REFCK-</td><td>Out</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P82</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>DIF3</td><td>-</td><td>VDDDIG1p8</td></tr><tr><td>P84</td><td>PCIE_A_REFCK-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>DIF3\</td><td>-</td><td>VDDDIG1p8</td></tr><tr><td>P85</td><td>GND</td><td>-</td><td>-</td><td></td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P86</td><td>PCIE_A_RX+</td><td>In</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE2_RXN_P</td><td>-</td><td>PCIE2_VPH</td></tr><tr><td>P87</td><td>PCIE_A_RX-</td><td>In</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE2_RXN_N</td><td>-</td><td>PCIE2_VPH</td></tr><tr><td>P88</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P89</td><td>PCIE_A_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE2_TXN_P</td><td>-</td><td>PCIE2_VPH</td></tr><tr><td>P90</td><td>PCIE_A_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE2_TXN_N</td><td>-</td><td>PCIE2_VPH</td></tr><tr><td>P91</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P92</td><td>HDMI_D2+ / DP1_LANE0+</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_P_LN_2</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P93</td><td>HDMI_D2- / DP1_LANE0-</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_N_LN_2</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P94</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P95</td><td>HDMI_D1+ / DP1_LANE1+</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_P_LN_1</td><td></td><td>HDMI_AVDDIO</td></tr><tr><td>P96</td><td>HDMI_D1- / DP1_LANE1-</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_N_LN_1</td><td></td><td>HDMI_AVDDIO</td></tr><tr><td>P97</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P98</td><td>HDMI_D0+ / DP1_LANE2+</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_P_LN_0</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P99</td><td>HDMI_D0- / DP1_LANE2-</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_N_LN_0</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P100</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P101</td><td>HDMI_CK+ / DP1_LANE3+</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_P_LN_3</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P102</td><td>HDMI_CK- / DP1_LANE3-</td><td>Out</td><td>-</td><td>HDMI</td><td>EL x6000</td><td>HDMI_TX_N_LN_3</td><td>`</td><td>HDMI_AVDDIO</td></tr><tr><td>P103</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P104</td><td>HDMI_HPD / DP1_HPD</td><td>In</td><td></td><td>HDMI</td><td>EL x6000</td><td>HDMI_HPD</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK / DP1_AUX+</td><td>Out</td><td>PU-2.2K / PD-100K</td><td>HDMI</td><td>EL x6000</td><td>HDMI_DDC_SCL(H) HDMI_AUX(P(L))</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT / DP1_AUX-</td><td>Bi-Dir</td><td>PU-2.2K / PD-100K</td><td>HDMI</td><td>EL x6000</td><td>HDMI_DDC_SDA(H) HDMI_AUX(N(L))</td><td>-</td><td>HDMI_AVDDIO</td></tr><tr><td>P107</td><td>DP1_AUX_SEL</td><td>Out</td><td>PD-1M</td><td>HDMI</td><td>EL x6000</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P108</td><td>GPIO0 / CAMO_PWR#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>GPIO1_IO03</td><td>ALT0</td><td>NVCC_GPIO1</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>GPIO1_IO05</td><td>ALT0</td><td>NVCC_GPIO1</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>GPIO1_IO06</td><td>ALT0</td><td>NVCC_GPIO1</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>GPIO1_IO06</td><td>ALT0</td><td>NVCC_GPIO1</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST#</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P0_4</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P113</td><td>GPIO5 / PWM_OUT</td><td>Out</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P0_5</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P114</td><td>GPIO6 / TACHIN</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P0_6</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P115</td><td>GPIO7</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P0_7</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P116</td><td>GPIO8</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P1_0</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P117</td><td>GPIO9</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P1_1</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P118</td><td>GPIO10</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P1_2</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P119</td><td>GPIO11</td><td>In</td><td>PU-470K</td><td>GPIO / 1.8V</td><td>SX1509</td><td>P1_3</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P120</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>P121</td><td>I2C_PM_CK</td><td>Out</td><td>PU-2k2</td><td>I2C2</td><td>EL x6000</td><td>I2C2_SCL</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>P122</td><td>I2C_PM_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>I2C2</td><td>EL x6000</td><td>I2C2_SDA</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>P123</td><td>BOOT_SEL0#</td><td>In</td><td>PU-4k7</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB0</td><td>-</td><td>+1V8SMC</td></tr><tr><td>P124</td><td>BOOT_SEL1#</td><td>In</td><td>PU-4k7</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB1</td><td>-</td><td>+1V8SMC</td></tr><tr><td>P125</td><td>BOOT_SEL2#</td><td>In</td><td>PU-4k7</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB2</td><td>-</td><td>+1V8SMC</td></tr><tr><td>P126</td><td>RESET_OUT#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB15</td><td>-</td><td>+1V8SMC</td></tr><tr><td>P127</td><td>RESET_IN#</td><td>In</td><td>PU-4K7</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB14</td><td>-</td><td>+1V8SMC</td></tr><tr><td>P128</td><td>POWER_BTN#</td><td>In</td><td>PU-4K7</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB4</td><td>-</td><td>+1V8SMC</td></tr><tr><td>P129</td><td>SER0_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART2_TXD</td><td>ALT0</td><td>NVCC_UART</td></tr><tr><td>P130</td><td>SER0_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART2_RXD</td><td>ALT0</td><td>NVCC_UART</td></tr><tr><td>P131</td><td>SER0_RTS#</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART4_TXD</td><td>ALT1</td><td>NVCC_UART</td></tr><tr><td>P132</td><td>SER0_CTS#</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART4_RXD</td><td>ALT1</td><td>NVCC_UART</td></tr><tr><td>P133</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P134</td><td>SER1_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART1_TXD</td><td>ALT0</td><td>NVCC_UART</td></tr><tr><td>P135</td><td>SER1_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART1_RXD</td><td>ALT0</td><td>NVCC_UART</td></tr><tr><td>P136</td><td>SER2_TX</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P137</td><td>SER2_RX</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P138</td><td>SER2_RTS#</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P139</td><td>SER2_CTS#</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>P140</td><td>SER3_TX</td><td>Out</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART3_TXD</td><td>ALT0</td><td>NVCC_UART</td></tr><tr><td>P141</td><td>SER3_RX</td><td>In</td><td>-</td><td>UART / 1.8V</td><td>EL x6000</td><td>UART3_RXD</td><td>ALT0</td><td>NVCC_UART</td></tr><tr><td>P142</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>P143</td><td>CAN0_TX</td><td>Out</td><td>-</td><td>CAN</td><td>EL x6000</td><td>TXCAN</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P144</td><td>CAN0_RX</td><td>In</td><td>-</td><td>CAN</td><td>EL x6000</td><td>RSCAN</td><td>-</td><td>VDD_1V8</td></tr><tr><td>P145</td><td>CAN1_TX</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>TXCAN</td><td></td><td></td></tr><tr><td>P146</td><td>CAN1_RX</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>RXCAN</td><td></td><td></td></tr><tr><td>P147</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P148</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P149</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P150</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P151</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P152</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P153</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P154</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P155</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr><tr><td>P156</td><td>VDD_IN</td><td>PWR</td><td>-</td><td>-</td><td>From Carrier board</td><td>-</td><td>-</td><td>3 ~ 5.25 V</td></tr></table>

<table><tr><td>Pin</td><td>SMARC Signal Name</td><td>Module Direction</td><td>Module Termination</td><td>Type/Tolerance</td><td>Controller</td><td>Controller Pin Name</td><td>I/O Mux default</td><td>Power Rail</td></tr><tr><td>S1</td><td>CSI1_TX+ / I2C_CAM1_CK</td><td>In</td><td>PU-2k2</td><td>I2C3</td><td>EL x6000</td><td>I2C3_SCL</td><td>ALTO</td><td>NVCC_I2C</td></tr><tr><td>S2</td><td>CSI1_TX- / I2C_CAM1_DAT</td><td>In</td><td>PU-2k2</td><td>I2C3</td><td>EL x6000</td><td>I2C3_SDA</td><td>ALTO</td><td>NVCC_I2C</td></tr><tr><td>S3</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S4</td><td>RSVD</td><td>In</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S5</td><td>CSI0_TX- / I2C_CAM0_CK</td><td>Out</td><td>PU-2k2</td><td>I2C4</td><td>EL x6000</td><td>I2C4_SCL</td><td>ALTO</td><td>NVCC_I2C</td></tr><tr><td>S6</td><td>CAM_MCK</td><td>Out</td><td>-</td><td>GPIO/1.8V</td><td>EL x6000</td><td>GPIO1_IO15</td><td>ALT5</td><td>NVCC_GPIO1</td></tr><tr><td>S7</td><td>CSI0_TX+ / I2C_CAM0_DAT</td><td>Bi-Dir</td><td>PU-2k2</td><td>I2C4</td><td>EL x6000</td><td>I2C4_SDA</td><td>ALTO</td><td>NVCC_I2C</td></tr><tr><td>S8</td><td>CSI0_CK+</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>EL x6000</td><td>MIPI_CSI1_CLK_P</td><td>-</td><td>MIPI_CSI1_VDDHA</td></tr><tr><td>S9</td><td>CSI0_CK-</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>EL x6000</td><td>MIPI_CSI1_CLK_N</td><td>-</td><td>MIPI_CSI1_VDDHA</td></tr><tr><td>S10</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S11</td><td>CSI0_RX0+</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>EL x6000</td><td>MIPI_CSI1_D0_P</td><td>-</td><td>MIPI_CSI1_VDDHA</td></tr><tr><td>S12</td><td>CSI0_RX0-</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>EL x6000</td><td>MIPI_CSI1_D0_N</td><td>-</td><td>MIPI_CSI1_VDDHA</td></tr><tr><td>S13</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S14</td><td>CSI0_RX1+</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>EL x6000</td><td>MIPI_CSI1_D1_P</td><td>-</td><td>MIPI_CSI1_VDDHA</td></tr><tr><td>S15</td><td>CSI0_RX1-</td><td>In</td><td>-</td><td>MIPI-CSI</td><td>EL x6000</td><td>MIPI_CSI1_D1_N</td><td>-</td><td>MIPI_CSI1_VDDHA</td></tr><tr><td>S16</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S17</td><td>GBE1_MDI0+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_PLUS[0]</td><td>-</td><td>-</td></tr><tr><td>S18</td><td>GBE1_MDI0-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_MINUS[0]</td><td>-</td><td>-</td></tr><tr><td>S19</td><td>GBE1_LINK100#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>GPY</td><td>LED0</td><td>-</td><td>-</td></tr><tr><td>S20</td><td>GBE1_MDI1+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_PLUS[1]</td><td>-</td><td>-</td></tr><tr><td>S21</td><td>GBE1_MDI1-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_MINUS[1]</td><td>-</td><td>-</td></tr><tr><td>S22</td><td>GBE1_LINK1000#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>GPY</td><td>LED2</td><td>-</td><td>-</td></tr><tr><td>S23</td><td>GBE1_MDI2+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_PLUS[2]</td><td>-</td><td>-</td></tr><tr><td>S24</td><td>GBE1_MDI2-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_MINUS[2]</td><td>-</td><td>-</td></tr><tr><td>S25</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S26</td><td>GBE1_MDI3+</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_PLUS[3]</td><td>-</td><td>-</td></tr><tr><td>S27</td><td>GBE1_MDI3-</td><td>Bi-Dir</td><td>-</td><td>GBE MDI</td><td>GPY</td><td>MDI_MINUS[3]</td><td>-</td><td>-</td></tr><tr><td>S28</td><td>GBE1_CTREF</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S29</td><td>PCIE_D_TX+ / SERDES_1_TX+</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PCIE_D</td><td>-</td><td>-</td></tr><tr><td>S30</td><td>PCIE_D_TX- / SERDES_1_TX-</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PCIE_D</td><td>-</td><td>-</td></tr><tr><td>S31</td><td>GBE1_LINK_ACT#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>GPY</td><td>LED1</td><td>-</td><td>-</td></tr><tr><td>S32</td><td>PCIE_D_RX+ / SERDES_1_RX+</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PCIE_D</td><td>-</td><td>-</td></tr><tr><td>S33</td><td>PCIE_D_RX- / SERDES_1_RX-</td><td>-</td><td>-</td><td>-</td><td>PCIE_D</td><td>PCIE_D</td><td>-</td><td>-</td></tr><tr><td>S34</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>S35</td><td>USB4+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS4_DP</td><td>-</td><td>-</td></tr><tr><td>S36</td><td>USB4-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS4_DM</td><td>-</td><td>-</td></tr><tr><td>S37</td><td>USB3_VBUS_DET</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S38</td><td>AUDIO_MCK</td><td>Out</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI2_MCLK</td><td>ALT0</td><td>NVCC_SAI2</td></tr><tr><td>S39</td><td>I2S0_LRCK</td><td>Bi-Dir</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI2_TXFS</td><td>ALT0</td><td>NVCC_SAI2</td></tr><tr><td>S40</td><td>I2S0_SDOUT</td><td>Out</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI2_TXD0</td><td>ALT0</td><td>NVCC_SAI2</td></tr><tr><td>S41</td><td>I2S0_SDIN</td><td>In</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI2_RXD0</td><td>ALT0</td><td>NVCC_SAI2</td></tr><tr><td>S42</td><td>I2S0_CK</td><td>Bi-Dir</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI2_TXC</td><td>ALT0</td><td>NVCC_SAI2</td></tr><tr><td>S43</td><td>ESPI_ALERT0#</td><td>In</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI1_RXFS</td><td>ALT5</td><td>NVCC_SAI1</td></tr><tr><td>S44</td><td>ESPI_ALERT1#</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>S45</td><td>MDIO_CLK</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>S46</td><td>MDIO_DAT</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td></td><td></td></tr><tr><td>S47</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td></td></tr><tr><td>S48</td><td>I2C_GP_CK</td><td>Out</td><td>PU-2.2K</td><td>I2C3</td><td>EL x6000</td><td>I2C3_SCL</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>S49</td><td>I2C_GP_DAT</td><td>Bi-Dir</td><td>PU-2.2K</td><td>I2C3</td><td>EL x6000</td><td>I2C3_SDA</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>S50</td><td>HDA_SYNC / I2S2_LRCK</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI3_TXFS</td><td>ALT0</td><td>NVCC_SAI3</td></tr><tr><td>S51</td><td>HDA_SDO / I2S2_SDOUT</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI3_TXD</td><td>ALT0</td><td>NVCC_SAI3</td></tr><tr><td>S52</td><td>HDA_SDI / I2S2_SDIN</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI3_RXD</td><td>ALT0</td><td>NVCC_SAI3</td></tr><tr><td>S53</td><td>HDA_CK / I2S2_CK</td><td>-</td><td>-</td><td>SAI / 1.8V</td><td>EL x6000</td><td>SAI3_TXC</td><td>ALT0</td><td>NVCC_SAI3</td></tr><tr><td>S54</td><td>SATA_ACT#</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S55</td><td>USB5_EN_OC#</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S56</td><td>ESPI_IO_2</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S57</td><td>ESPI_IO_3</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S58</td><td>ESPI_RESET#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB15</td><td>-</td><td>+1V8SMC</td></tr><tr><td>S59</td><td>USB5+</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S60</td><td>USB5-</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S61</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S62</td><td>USB3_SSTX+</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>EL x6000</td><td>DS1_TXP</td><td>-</td><td>-</td></tr><tr><td>S63</td><td>USB3_SSTX-</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>EL x6000</td><td>DS1_TXM</td><td>-</td><td>-</td></tr><tr><td>S64</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S65</td><td>USB3_SSRX+</td><td>In</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS1_RXP</td><td>-</td><td>-</td></tr><tr><td>S66</td><td>USB3_SSRX-</td><td>In</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS1_RXM</td><td>-</td><td>-</td></tr><tr><td>S67</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S68</td><td>USB3+</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS1_DP</td><td>-</td><td>-</td></tr><tr><td>S69</td><td>USB3-</td><td>Bi-Dir</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS1_DM</td><td>-</td><td>-</td></tr><tr><td>S70</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S71</td><td>USB2_SSTX+</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>EL x6000</td><td>DS2_TXP</td><td>-</td><td>-</td></tr><tr><td>S72</td><td>USB2_SSTX-</td><td>Out</td><td>Serial-0.1uF</td><td>USB</td><td>EL x6000</td><td>DS2_TXM</td><td>-</td><td>-</td></tr><tr><td>S73</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S74</td><td>USB2_SSRX+</td><td>In</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS2_RXP</td><td>-</td><td>-</td></tr><tr><td>S75</td><td>USB2_SSRX-</td><td>In</td><td>-</td><td>USB</td><td>EL x6000</td><td>DS2_RXM</td><td>-</td><td>-</td></tr><tr><td>S76</td><td>PCIE_B_RST#</td><td>Out</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>NAND_ALE</td><td>ALT5</td><td>NVCC_NAND</td></tr><tr><td>S77</td><td>PCIE_C_RST#</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S78</td><td>PCIE_C_RX+ / SERDES_2_RX+</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S79</td><td>PCIE_C_RX- / SERDES_2_RX-</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S80</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S81</td><td>PCIE_C_TX+ / SERDES_2_TX+</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S82</td><td>PCIE_C_TX- / SERDES_2_TX-</td><td>-</td><td>-</td><td>-</td><td>EL x6000</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S83</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S84</td><td>PCIE_B_REFCK+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>DIF1</td><td>-</td><td>VDDDIG1p8</td></tr><tr><td>S85</td><td>PCIE_B_REFCK-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>DIF1\</td><td>-</td><td>VDDDIG1p8</td></tr><tr><td>S86</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S87</td><td>PCIE_B_RX+</td><td>In</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE1_RXN_P</td><td>-</td><td>PCIE1_VPH</td></tr><tr><td>S88</td><td>PCIE_B_RX-</td><td>In</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE1_RXN_N</td><td>-</td><td>PCIE1_VPH</td></tr><tr><td>S89</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S90</td><td>PCIE_B_TX+</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE1_TXN_P</td><td>-</td><td>PCIE1_VPH</td></tr><tr><td>S91</td><td>PCIE_B_TX-</td><td>Out</td><td>Serial-0.1uF</td><td>PCIe</td><td>EL x6000</td><td>PCIE1_TXN_N</td><td>-</td><td>PCIE1_VPH</td></tr><tr><td>S92</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S93</td><td>DP0_LANE0+</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S94</td><td>DP0_LANE0-</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S95</td><td>DP0_AUX_SEL</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S96</td><td>DP0_LANE1+</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S97</td><td>DP0_LANE1-</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S98</td><td>DP0_HPD</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S99</td><td>DP0_LANE2+</td><td>-</td><td>-</td><td>-</td><td>DDI1</td><td>DDI1</td><td>-</td><td>-</td></tr><tr><td>S100</td><td>DP0_LANE2-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S101</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S102</td><td>DP0_LANE3+</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S103</td><td>DP0_LANE3-</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S104</td><td>USB3_OTG_ID</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S105</td><td>DP0_AUX+</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S106</td><td>DP0_AUX-</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S108</td><td>LVDS1_CK+/ eDP1_AUX+/ DSI1_CLK+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_CLKP</td><td>-</td><td>-</td></tr><tr><td>S109</td><td>LVDS1_CK-/ eDP1_AUX-/ DSI1_CLK-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_CLKN</td><td>-</td><td>-</td></tr><tr><td>S110</td><td>GND</td><td>-</td><td>-</td><td>-</td><td></td><td></td><td>-</td><td>-</td></tr><tr><td>S111</td><td>LVDS1_0+/ eDP1_TX0+/ DSI1_D0+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_YOP</td><td>-</td><td>-</td></tr><tr><td>S112</td><td>LVDS1_0-/ eDP1_TX0-/ DSI1_D0-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_YON</td><td>-</td><td>-</td></tr><tr><td>S113</td><td>eDP1_HPD/ DSI1_TE</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S114</td><td>LVDS1_1+/ eDP1_TX1+/ DSI1_D1+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_Y1P</td><td>-</td><td>-</td></tr><tr><td>S115</td><td>LVDS1_1-/ eDP1_TX1-/ DSI1_D1-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_Y1N</td><td>-</td><td>-</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S117</td><td>LVDS1_2+/ eDP1_TX2+/ DSI1_D2+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_Y2P</td><td>-</td><td>-</td></tr><tr><td>S118</td><td>LVDS1_2-/ eDP1_TX2-/ DSI1_D2-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_Y2N</td><td>-</td><td>-</td></tr><tr><td>S119</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S120</td><td>LVDS1_3+/ eDP1_TX3+/ DSI1_D3+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_Y3P</td><td>-</td><td>-</td></tr><tr><td>S121</td><td>LVDS1_3-/ eDP1_TX3-/ DSI1_D3-</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>B_Y3N</td><td>-</td><td>-</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S123</td><td>GPIO13</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S124</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S125</td><td>LVDS0_0+/ eDP0_TX0+/ DSI0_D0+</td><td>Out</td><td>Serial-OR</td><td>LVDS</td><td>PTN3460</td><td>A_YOP</td><td>-</td><td>-</td></tr><tr><td>S126</td><td>LVDS0_0- / eDP0_TX0- / DSIO_D0-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y0N</td><td>-</td><td>-</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>GPIO1_IO00</td><td>-</td><td>-</td></tr><tr><td>S128</td><td>LVDS0_1+ / eDP0_TX1+ / DSIO_D1+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y1P</td><td>-</td><td>-</td></tr><tr><td>S129</td><td>LVDS0_1- / eDP0_TX1- / DSIO_D1-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y1N</td><td>-</td><td>-</td></tr><tr><td>S130</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S131</td><td>LVDS0_2+ / eDP0_TX2+ / DSIO_D2+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y2P</td><td>-</td><td>-</td></tr><tr><td>S132</td><td>LVDS0_2- / eDP0_TX2- / DSIO_D2-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y2N</td><td>-</td><td>-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>Out</td><td>-</td><td>GPIO/1.8V</td><td>EL x6000</td><td>GPIO1_IO04</td><td>-</td><td>-</td></tr><tr><td>S134</td><td>LVDS0_CK+ / eDP0_AUX+ / DSIO_CLK+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_CLKP</td><td>-</td><td>-</td></tr><tr><td>S135</td><td>LVDS0_CK- / eDP0_AUX- / DSIO_CLK-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_CLKN</td><td>-</td><td>-</td></tr><tr><td>S136</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S137</td><td>LVDS0_3+ / eDP0_TX3+ / DSIO_D3+</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y3P</td><td>-</td><td>-</td></tr><tr><td>S138</td><td>LVDS0_3- / eDP0_TX3- / DSIO_D3-</td><td>Out</td><td>Serial-0R</td><td>LVDS</td><td>PTN3460</td><td>A_Y3N</td><td>-</td><td>-</td></tr><tr><td>S139</td><td>I2C_LCD_CK</td><td>Out</td><td>PU-2.2K</td><td>I2C4</td><td>EL x6000</td><td>I2C4_SCL</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td><td>Bi-Dir</td><td>PU-2.2K</td><td>I2C4</td><td>EL x6000</td><td>I2C4_SCL</td><td>ALT0</td><td>NVCC_I2C</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>GPIO1_IO01</td><td>ALT1</td><td>NVCC_GPIO1</td></tr><tr><td>S142</td><td>GPIO12</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>BMC</td><td>PC14</td><td>-</td><td>-</td></tr><tr><td>S143</td><td>GND</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S144</td><td>eDP0_HPD / DSIO_TE</td><td>-</td><td>-</td><td>-</td><td>N.C.</td><td>N.C.</td><td>-</td><td>-</td></tr><tr><td>S145</td><td>WDT_TIME_OUT#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>BMC</td><td>PD2</td><td>-</td><td>+1V8SMC</td></tr><tr><td>S146</td><td>PCIE_WAKE#</td><td>In</td><td>-</td><td>GPIO / 3.3V</td><td>EL x6000</td><td>SAI1_TXFS</td><td>ALT5</td><td>NVCC_SAI1</td></tr><tr><td>S147</td><td>VDD_RTC</td><td>PWR</td><td>-</td><td>PWR</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>S148</td><td>LID#</td><td>In</td><td>PU-4.7K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>SAI5_MCLK</td><td>ALT5</td><td>NVCC_SAI5</td></tr><tr><td>S149</td><td>SLEEP#</td><td>In</td><td>PU-4.7K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>SAI5_RXFS</td><td>ALT5</td><td>NVCC_SAI5</td></tr><tr><td>S150</td><td>VIN_PWR_BAD#</td><td>In</td><td>PU-10K</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB7</td><td>-</td><td>+1V8SMC</td></tr><tr><td>S151</td><td>CHARGING#</td><td>Out</td><td>PU-68K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>SAI5_RXC</td><td>ALT5</td><td>NVCC_SAI5</td></tr><tr><td>S152</td><td>CHARGER_PRSNT#</td><td>Out</td><td>PU-100K</td><td>GPIO / 1.8V</td><td>EL x6000</td><td>SAI5_RXD0</td><td>ALT5</td><td>NVCC_SAI5</td></tr><tr><td>S153</td><td>CARRIER_STBY#</td><td>Out</td><td>-</td><td>GPIO / 1.8V</td><td>BMC</td><td>PB5</td><td>-</td><td>+1V8SMC</td></tr></table>

# 5. Additional Features

This chapter describes connectors, LEDs, switches and additional items located on the module and not necessarily included in the PICMG standard specification. The locations of these items are as below:

# 5.1 Module Feature Loca

![Status\nLEDs\n40-pin Debug\nConnector](.smarc-lec-el-50m-72513-1050-15/16b02fe292e399a047bf85b8f6a313e867c0c2e918849ee091a9a8a860f47197.jpg)

Figure 3 – Module feature locations (top side)

# Status LEDs

Status LED’s are mounted on the module to facilitate easier maintenance.

LED3 LED2 LED1

![Close-up of a green printed circuit board with integrated circuits and a resistor (no readable text or symbols)](.smarc-lec-el-50m-72513-1050-15/726e75033c43758ea86166091ec9880efcf90c681c163719b14316ed97d353fe.jpg)

<table><tr><td>Name</td><td>Color</td><td>Connection</td><td>Function</td></tr><tr><td>LED1</td><td>Blue</td><td>BMC/EC output</td><td>Power Sequence Status Code (BMC) Power Changes, RESET (see Exception Codes below)</td></tr><tr><td>LED2</td><td>Green</td><td>Power Source</td><td>S0 LED ONS3/S4/S5 LED OFFECO mode LED OFF</td></tr><tr><td>LED3</td><td>Red</td><td>Watchdog (WD)</td><td>Module power up WD LED = LED OFFWatchdog counting WD LED = Keep Last StateWatchdog timed out WD LED = LED ONWatchdog RESET WD LED = LED ONRebooted after WD RESET WD LED = LED ONRebooted after PWRBTN WD LED = LED OFFRebooted after RESET BTN WD LED = LED OFFNote: only a RESET not initiated by the BMC can clear the WD LED (user action)</td></tr></table>

5.2.1 Exception Codes

<table><tr><td>Exception Code</td><td>Error Message</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>3</td><td>NO_SLP_S5</td></tr><tr><td>4</td><td>NO_SLP_S4</td></tr><tr><td>5</td><td>NO_SLP_S3</td></tr><tr><td>6</td><td>BIOS_FAIL</td></tr><tr><td>8</td><td>RESETIN_FAIL</td></tr><tr><td>9</td><td>NO_CB_PWROK</td></tr><tr><td>10</td><td>CRITICAL_TEMP</td></tr><tr><td>11</td><td>POWER_FAIL</td></tr><tr><td>12</td><td>VOLTAGE_FAIL</td></tr><tr><td>13</td><td>RSMRST_FAIL</td></tr><tr><td>14</td><td>NO_VDDQ_PG</td></tr><tr><td>16</td><td>NO_VCORE_PG</td></tr><tr><td>17</td><td>NO_SYS_GD</td></tr><tr><td>19</td><td>NO_V3P3A</td></tr><tr><td>21</td><td>NO_PWRSRC_GD</td></tr></table>

# 6. System Resources

System Memory Map

<table><tr><td>Memory Range</td><td>Target</td><td>Dependency / Comments</td></tr><tr><td>000E 0000h-000E FFFFh</td><td>SPI</td><td>Bit6 in BIOS Decode Enable register is set</td></tr><tr><td>0000F 0000h-0000F FFFFh</td><td>SPI</td><td>Bit7 in BIOS Decode Enable register is set</td></tr><tr><td>FECX X000h-FECX X040h</td><td>IO(x) APIC inside PCH</td><td>XX controlled via APIC Range Select(ASEL) field and APIC Enable IOAC.AE bit.</td></tr><tr><td>FEC1 0000h-FEC1 7FFFh</td><td>PCI Express* Port 1</td><td>PCI Express Root Port 1 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC1 8000h-FEC1 FFFFh</td><td>PCI Express* Port 2</td><td>PCI Express Root Port 2 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC2 0000h-FEC2 7FFFh</td><td>PCI Express* Port 3</td><td>PCI Express Root Port 3 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC2 8000h-FEC2 FFFFh</td><td>PCI Express* Port 4</td><td>PCI Express Root Port 4 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC3 8000h-FEC3 FFFFh</td><td>PCI Express* Port 5</td><td>PCI Express Root Port 5 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC3 8000h-FEC3 FFFFh</td><td>PCI Express* Port 6</td><td>PCI Express Root Port 6 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEC4 0000h-FEC4 7FFFh</td><td>PCI Express* Port 7</td><td>PCI Express* Root Port 7 I/OxAPIC Enable(PAE) set</td></tr><tr><td>FEF0 0000h-FEFF FFFFh</td><td>SPI</td><td>uCode Patch Region Enable UCPR.UPRE is set</td></tr><tr><td>FEC0 0000h-FFC7 FFFFhFF80 0000h-FF87 FFFFh</td><td>SPI</td><td>Bit 8 in BIOS Decode Enable register is set</td></tr><tr><td>FFC8 0000h-FFCF FFFFhFF88 0000h-FF8F</td><td>SPI</td><td>Bit 9 in BIOS Decode Enable register is set</td></tr><tr><td>FED0 0000h-FFD7 FFFFhFF90 0000h-FF97 FFFFh</td><td>SPI</td><td>Bit 10 in BIOS Decode Enable register is set</td></tr><tr><td>FFD8 0000h-FFDF FFFFhFF98 0000h-FF9F FFFFh</td><td>SPI</td><td>Bit11 in BIOS Decode Enable register is set</td></tr><tr><td>FFE0 0000h-FFE7 FFFFhFFA0 0000h-FFA7 FFFFh</td><td>SPI</td><td>Bit 12 in BIOS Decode Enable register is set</td></tr><tr><td>FFE8 0000h-FFEF FFFFhFFA8 0000h-FFAF FFFFh</td><td>SPI</td><td>Bit 13 in BIOS Decode Enable register is set</td></tr><tr><td>FFF0 0000h-FFF7 FFFFhFFB0 0000h-FFB7 FFFFh</td><td>SPI</td><td>Bit 14 in BIOS Decode Enable register is set</td></tr><tr><td>FFFC 0000h-FFFFh</td><td>SPI</td><td>Always Enabled.</td></tr><tr><td>FFF8 0000h-FFFB FFFFh</td><td>SPI</td><td>Always enabled.</td></tr><tr><td>FFB8 0000h-FFBF FFFFh</td><td></td><td></td></tr><tr><td>FF70 0000h-FF7F FFFFhFF30 0000h-FF3F FFFFh</td><td>SPI</td><td>Bit 3 in BIOS Decode Enable register is set</td></tr><tr><td>FF60 0000h-FF6F FFFFhFF20 0000h-FF2F FFFFh</td><td>SPI</td><td>Bit 2 in BIOS Decode Enable register is set</td></tr><tr><td>FF50 0000h-FF5F FFFFhFF10 0000h-FF1F FFFFh</td><td>SPI(</td><td>Bit 1 in BIOS Decode Enable register is set</td></tr><tr><td>FF40 0000h-FF4F FFFFhFF00 0000h-FF0F FFFFh</td><td>SPI</td><td>Bit 0 in BIOS Decode Enable register is set</td></tr><tr><td>FED0 X000h-FED0 X3FFh</td><td>HPET</td><td>BIOS determines "fixed" location which is one of four 1KB ranges where X(in the first column) is 0h,1h,2h,or 3h.</td></tr><tr><td>FED4 0000h-FED4 7FFFh</td><td>SPI or CSE(set by strap)</td><td>TPM nad Trusted Mobile KBC</td></tr><tr><td>FED4 C000h-FED4 FFFFh</td><td>PCH Internal(PSE Error Handler)</td><td>Always Enable</td></tr><tr><td>FED5 0000h-FED5 FFFFh</td><td>CSE</td><td>Always Enable</td></tr><tr><td>FED6 0000h-FED6 1FFFh</td><td>XHCI</td><td>NOT positively decoded in PCH(OPI/PSF)</td></tr><tr><td>FED7 0000h-FED7 4FFFh</td><td>Internal Device</td><td>Security feature related</td></tr><tr><td>64Kb(MBAR) anywhere in 64-bit address range</td><td>XHCI</td><td>Enable via standard PCI mechanism(D20:F0)</td></tr><tr><td>2MB(BAR)&amp;4Kb(BAR1) anywhere in 64-bit address range</td><td>USB eXtensible Device Controller Interface(xDCI)</td><td>Enable via standard PCI mechanism(D20:F1)</td></tr><tr><td>16kB(HDAxBA),4kB(SPCxBA)&amp;1MB(ADSPxBA) anywhere in 64-bit address range</td><td>Converged Audio, Video Speech(cAVS) Controller</td><td>Enable via standard PCI mechanism(D20:F3)</td></tr><tr><td>64 KB anywhere in 4 GB range</td><td>eSPI</td><td>LPC Generic Memory Range.Enable via setting bit[0] of the LPC Generic Memory Range Register(D31:F0:offset98h).</td></tr><tr><td>32B(SMBBAR) anywhere in 64-bit address range</td><td>SM Bus</td><td>Enable via standard PCI mechanism(D31:F4)</td></tr><tr><td>2 KB anywhere above 64 KB to 4 GB range</td><td>SATA Controller(AHCI)</td><td>Enable via standard PCI mechanism(D23:F0)</td></tr><tr><td>Memory Base/Limit anywhere in 4 GB range</td><td>PCI Express Root Ports1-7</td><td>Enable via standard PCI mechanism(D28:F[0:6])</td></tr><tr><td>Pre-fetchable Memory Base/Limit anywhere in 64-bit address range</td><td>PCI Express Root Ports1-7</td><td>Enable via standard PCI mechanism(D28:F[0:6])</td></tr><tr><td>16B(HECIx_MMIO_BAR) anywhere in 64-bit address range</td><td>HECI #0,#1,#2,#4</td><td>Enable via standard PCI mechanism(D22:F[0:1,4:5])</td></tr><tr><td>16 MB(SBREG_BAR) anywhere in 64-bit address range</td><td>P2SB</td><td>Enable via standard PCI mechanism(D31:F1)</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Intel(R) Serial I/O Controllers</td><td>Enable via standard PCI mechanism(D30:F[0:3,D25:F[0:2],D21:F[0:3],D18:F0,D16:F[1:0])</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Embedded Multi Media Card(eMMC) Controller</td><td>Enable via standard PCI mechanism(D26:F0)</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Secure Digital (SD) &amp; Secure Digital I/O Controller</td><td>Enable via standard PCI mechanism(D26:F1)</td></tr><tr><td>4kB(BAR &amp; BAR1) anywhere in 64-bit address range</td><td>Universal Flash Storage(UFS) Controller</td><td>Enable via standard PCI mechanism(D18:F[5,7])</td></tr></table>

6.2 Fixed I/O Address Range Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>020-021</td><td>Interrupt Controller</td></tr><tr><td>024-025</td><td>Interrupt Controller</td></tr><tr><td>028-029</td><td>Interrupt Controller</td></tr><tr><td>02C-02D</td><td>Interrupt Controller</td></tr><tr><td>02E-02F</td><td>Super I/O</td></tr><tr><td>030-031</td><td></td></tr><tr><td>034-035</td><td></td></tr><tr><td>038-039</td><td>Interrupt Controller</td></tr><tr><td>03C-03D</td><td>Interrupt Controller</td></tr><tr><td>040</td><td>Timer/Counter</td></tr><tr><td>042-043</td><td>Timer/Counter</td></tr><tr><td>04E-04F</td><td>Microcontroller</td></tr><tr><td>050</td><td>Timer/Counter</td></tr><tr><td>052-053</td><td>Timer/Counter</td></tr><tr><td>060</td><td>Keyboard Controller</td></tr><tr><td>061</td><td>NMI Controller</td></tr><tr><td>062</td><td>Microcontroller</td></tr><tr><td>063</td><td>NMI Controller</td></tr><tr><td>064</td><td>Keyboard Controller</td></tr><tr><td>065</td><td>NMI Controller</td></tr><tr><td>066</td><td>Microcontroller</td></tr><tr><td>067</td><td>NMI Controller</td></tr><tr><td>070</td><td>RTC Controller</td></tr><tr><td>071</td><td>RTC Controller</td></tr><tr><td>072</td><td>RTC Controller</td></tr><tr><td>073</td><td>RTC Controller</td></tr><tr><td>074</td><td>RTC Controller</td></tr><tr><td>075</td><td>RTC Controller</td></tr><tr><td>076-077</td><td>RTC Controller</td></tr><tr><td>080</td><td>eSPI or PCIe</td></tr><tr><td>084-086</td><td>eSPI or PCIe</td></tr><tr><td>088</td><td>eSPI or PCIe</td></tr><tr><td>08C-08E</td><td>eSPI or PCIe</td></tr><tr><td>090</td><td>eSPI</td></tr><tr><td>092</td><td>Reset Generator</td></tr><tr><td>094-096</td><td>eSPI</td></tr><tr><td>098</td><td>eSPI</td></tr><tr><td>09C-09E</td><td>eSPI</td></tr><tr><td>0A0-0A1</td><td>Interrupt Controller</td></tr><tr><td>0A4-0A5</td><td></td></tr><tr><td>0A8-0A9</td><td></td></tr><tr><td>0AC-0AD</td><td></td></tr><tr><td>0B0-0B1</td><td>Interrupt Controller</td></tr><tr><td>0B2-0B3</td><td>Power Management</td></tr><tr><td>0B4-0B5</td><td>Interrupt Controller</td></tr><tr><td>0B8-0B9</td><td></td></tr><tr><td>0BC-0BD</td><td></td></tr><tr><td>200-207</td><td>Gameport Low</td></tr><tr><td>208-20F</td><td>Gameport High</td></tr><tr><td>4D0-4D1</td><td>Interrupt Controller</td></tr><tr><td>CF9</td><td>Reset Generator</td></tr></table>

6.3 Variable I/O Address Range Map

<table><tr><td>Hex Range</td><td>Device</td></tr><tr><td>Anywhere in 64 K I/O Space</td><td>ACPI</td></tr><tr><td>Anywhere in 64 K I/O Space</td><td>SMBus</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>TCO</td></tr><tr><td>3 ranges in 64 KB I/O Space</td><td>Parallel Port</td></tr><tr><td>8 ranges in 64 KB I/O Space</td><td>Serial Port1</td></tr><tr><td>8 ranges in 64 KB I/O Space</td><td>Serial Port2</td></tr><tr><td>2 ranges in 64 KB I/O Space</td><td>Serial Port3</td></tr><tr><td>Anywhere in 64 K I/O Space</td><td>Floppy Disk Controller</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 1</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 2</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 3</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>LPC Generic 4</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>Serial ATA Index/Data Pair</td></tr><tr><td>Anywhere in 64 KB I/O Space</td><td>PCI Express Root Ports</td></tr></table>

PCI Configuration Space Map

<table><tr><td>Bus Number</td><td>Device Number</td><td>Function Number</td><td>Description</td></tr><tr><td>00h</td><td>31h</td><td>00h</td><td>Enhanced Serial Peripheral Interface(eSPI) Controller</td></tr><tr><td>00h</td><td>31h</td><td>01h</td><td>Primary to Sideband Bridge(P2SB)</td></tr><tr><td>00h</td><td>31h</td><td>02h</td><td>Power Management Controller(PMC)</td></tr><tr><td>00h</td><td>31h</td><td>03h</td><td>Converged Audio,Video,Speech(cAVS) Controller</td></tr><tr><td>00h</td><td>31h</td><td>04h</td><td>System Management Bus(SMBus) Controller</td></tr><tr><td>00h</td><td>31h</td><td>05h</td><td>Serial Peripheral Interface(SPI) Controller for Flash &amp; TPM</td></tr><tr><td>00h</td><td>31h</td><td>07h</td><td>Intel(R) Trace Hub</td></tr><tr><td>00h</td><td>30h</td><td>00h</td><td>Intel(R) Serial I/O:Universal Asynchronous Receiver/Transmitter(UART) Controller #0</td></tr><tr><td>00h</td><td>30h</td><td>01h</td><td>Intel(R) Serial I/O:UART Controller #1</td></tr><tr><td>00h</td><td>30h</td><td>02h</td><td>Intel(R) Serial I/O:Serial Peripheral Interface(SPI) Controller #0</td></tr><tr><td>00h</td><td>30h</td><td>03h</td><td>Intel(R) Serial I/O:SPI Controller #1</td></tr><tr><td>00h</td><td>30h</td><td>04h</td><td>Gigabit Ethernet TSN Controller</td></tr><tr><td>00h</td><td>30h</td><td>06h</td><td>High Precision Event Timer(HPET)</td></tr><tr><td>00h</td><td>30h</td><td>07h</td><td>I/O Advanced Programmable Interrupt Controller(IOAPIC)</td></tr><tr><td>00h</td><td>29h</td><td>00h</td><td>Intel(R) Programmable Services Engine(Intel(R) PSE):Local Host to PSE(LH2OSE) IPC</td></tr><tr><td>00h</td><td>29h</td><td>01h</td><td>Intel(R) Programmable Services Engine(Intel(R) PSE):Gigabit Ethernet TSN Controller #0(RGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>01h</td><td>Intel(R) PSE:Gigabit Ethernet TSN Controller #0(SGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>01h</td><td>Intel(R) PSE:Gigabit Ethernet TSN Controller #0(SGMII:2.5 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>02h</td><td>Intel(R) PSE:Gigabit Ethernet Time Sensitive Networking(TSN) Controller #1(RGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>02h</td><td>Intel(R) PSE:Gigabit Ethernet TSN Controller #1(SGMII:1 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>02h</td><td>Intel(R) PSE:Gigabit Ethernet TSN Controller #1(SGMII:2.5 Gb Mode)</td></tr><tr><td>00h</td><td>29h</td><td>03h</td><td>Intel(R) PSE:Direct Memory Access (DMA) Controller #0</td></tr><tr><td>00h</td><td>29h</td><td>04h</td><td>Intel(R) PSE:DMA Controller #1</td></tr><tr><td>00h</td><td>29h</td><td>05h</td><td>Intel(R) PSE:DMA Controller #2</td></tr><tr><td>00h</td><td>29h</td><td>06h</td><td>Intel(R) PSE:Pulse Width Modulation(PWM) Controller</td></tr><tr><td>00h</td><td>29h</td><td>07h</td><td>Intel(R) PSE:Analog to Digital Converter(ADC)</td></tr><tr><td>00h</td><td>28h</td><td>00h</td><td>PCI Express*(PCIe*) Root Port #0(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>01h</td><td>PCIe* Root Port #1(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>02h</td><td>PCIe* Root Port #2(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>03h</td><td>PCIe* Root Port #3(PCIe 0,Single VC)</td></tr><tr><td>00h</td><td>28h</td><td>04h</td><td>PCIe* Root Port #4(PCIe 0,Multi VC)</td></tr><tr><td>00h</td><td>28h</td><td>05h</td><td>PCIe* Root Port #5(PCIe 0, Multi VC)</td></tr><tr><td>00h</td><td>28h</td><td>06h</td><td>PCIe* Root Port #6(PCIe 0, Multi VC)</td></tr><tr><td>00h</td><td>27h</td><td>00h</td><td>Intel(R) PSE:Inter-Integrated Circuit(I2C) Controller #0</td></tr><tr><td>00h</td><td>27h</td><td>01h</td><td>Intel(R) PSE:I2C Controller #1</td></tr><tr><td>00h</td><td>27h</td><td>02h</td><td>Intel(R) PSE:I2C Controller #2</td></tr><tr><td>00h</td><td>27h</td><td>03h</td><td>Intel(R) PSE:I2C Controller #3</td></tr><tr><td>00h</td><td>27h</td><td>04h</td><td>Intel(R) PSE:I2C Controller #4</td></tr><tr><td>00h</td><td>27h</td><td>05h</td><td>Intel(R) PSE:I2C Controller #5</td></tr><tr><td>00h</td><td>27h</td><td>06h</td><td>Intel(R) PSE:I2C Controller #6</td></tr><tr><td>00h</td><td>26h</td><td>00h</td><td>Embedded Multi Media Card(eMMC) Controller</td></tr><tr><td>00h</td><td>26h</td><td>01h</td><td>Secure Digital (SD) &amp; Secure Digital I/O Controller</td></tr><tr><td>00h</td><td>26h</td><td>03h</td><td>Intel(R) Safely Island(Intel(R) SI) Controller</td></tr><tr><td>00h</td><td>25h</td><td>00h</td><td>Intel(R) Serial I/O:Inter-Integrated Circuit(I2C) Controller #4</td></tr><tr><td>00h</td><td>25h</td><td>01h</td><td>Intel(R) Serial I/O I2C Controller #5</td></tr><tr><td>00h</td><td>25h</td><td>02h</td><td>Intel(R) Serial I/O:Universal Asynchronous Receiver/Transmitter(UART) Controller #2</td></tr><tr><td>00h</td><td>24h</td><td>00h</td><td>Intel(R) Programmable Services Engine(Intel(R) PSE:I2C Controller #7</td></tr><tr><td>00h</td><td>24h</td><td>01h</td><td>Intel(R) PSE:Controller Area Network (CAN) Controller #0</td></tr><tr><td>00h</td><td>24h</td><td>02h</td><td>Intel(R) PSE:CAN Controller #1</td></tr><tr><td>00h</td><td>24h</td><td>03h</td><td>Intel(R) PSE:Quadrature Encoder Peripheral,(QEP) Controller #0</td></tr><tr><td>00h</td><td>24h</td><td>04h</td><td>Intel(R) PSE:QEP Controller #1</td></tr><tr><td>00h</td><td>24h</td><td>05h</td><td>Intel(R) PSE: QEP Controller #2</td></tr><tr><td>00h</td><td>24h</td><td>06h</td><td>Intel(R) PSE: QEP Controller #3</td></tr><tr><td>00h</td><td>22h</td><td>00h</td><td>Intel(R)</td></tr><tr><td>00h</td><td>22h</td><td>01h</td><td>Intel(R) CSE:HECI #1</td></tr><tr><td>00h</td><td>22h</td><td>04h</td><td>Intel(R) CSE:HECI #2</td></tr><tr><td>00h</td><td>22h</td><td>05h</td><td>Intel(R) CSE:HECI #3</td></tr><tr><td>00h</td><td>21h</td><td>00h</td><td>Intel(R) Serial I/O:Inter-Integrated Circuit(I2C) Controller #0</td></tr><tr><td>00h</td><td>21h</td><td>01h</td><td></td></tr><tr><td>00h</td><td>21h</td><td>02h</td><td>Intel(R) Serial I/O:I2C Controller #1</td></tr><tr><td>00h</td><td>21h</td><td>03h</td><td>Intel(R) Serial I/O:I2C Controller #2</td></tr><tr><td>00h</td><td>21h</td><td>07h</td><td>Intel(R) Serial I/O:I2C Controller #3</td></tr><tr><td>00h</td><td>19h</td><td>00h</td><td>Intel(R) PSE:Serial Peripheral Interface(SPI) Controller #0</td></tr><tr><td>00h</td><td>19h</td><td>01h</td><td>Intel(R) PSE:SPI Controller #1</td></tr><tr><td>00h</td><td>19h</td><td>02h</td><td>Intel(R) PSE:SPI Controller #2</td></tr><tr><td>00h</td><td>19h</td><td>03h</td><td>Intel(R) PSE:SPI Controller #3</td></tr><tr><td>00h</td><td>19h</td><td>04h</td><td>Intel(R) PSE:General Pupose Input Output(GPIO) Controller #0</td></tr><tr><td>00h</td><td>19h</td><td>05h</td><td>Intel(R) PSE:General Pupose Input Output(GPIO) Controller #1</td></tr><tr><td>00h</td><td>18h</td><td>00h</td><td>Intel(R) Serial I/O:SPI Controller #2</td></tr><tr><td>00h</td><td>18h</td><td>03h</td><td>Intel(R) Converged Security Engine(Intel(R) CSE):UMA Access</td></tr><tr><td>00h</td><td>18h</td><td>04h</td><td>Intel(R) CSE:Intel(R) PTT DMA Controller</td></tr><tr><td>00h</td><td>18h</td><td>05h</td><td>Universal Flash Storage(UFS) Controller #0</td></tr><tr><td>00h</td><td>18h</td><td>07h</td><td>UFS Controller #1</td></tr><tr><td>00h</td><td>17h</td><td>00h</td><td>Intel(R) PSE:Universal Asynchronous Receiver/Transmitter(UART) Controller#0</td></tr><tr><td>00h</td><td>17h</td><td>01h</td><td>Intel(R) PSE:UART Controller #1</td></tr><tr><td>00h</td><td>17h</td><td>02h</td><td>Intel(R) PSE:UART Controller #2</td></tr><tr><td>00h</td><td>17h</td><td>03h</td><td>Intel(R) PSE:UART Controller #3</td></tr><tr><td>00h</td><td>17h</td><td>04h</td><td>Intel(R) PSE:UART Controller #4</td></tr><tr><td>00h</td><td>17h</td><td>05h</td><td>Intel(R) PSE:UART Controller #5</td></tr><tr><td>00h</td><td>17h</td><td>06h</td><td>Intel(R) PSE:Inter-Integrated Circuit Sound(I2S) Controller #0</td></tr><tr><td>00h</td><td>17h</td><td>07h</td><td>Intel(R) PSE:I2S Controller #1</td></tr><tr><td>00h</td><td>16h</td><td>00h</td><td>Intel(R) Serial I/O:Inter-Integrated Circuit(I2C) Controller #6</td></tr><tr><td>00h</td><td>16h</td><td>01h</td><td>Intel(R) Serial I/O:I2C Controller #7</td></tr><tr><td>00h</td><td>16h</td><td>05h</td><td>Integrated Error Handler(IEH)</td></tr></table>

PCI Interrupt Routing Map

<table><tr><td>INT Line</td><td>xHCI Controller</td><td>SATA Controller</td><td>SMBus Controller</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTA:16</td><td>INTA:16</td></tr><tr><td>Int1</td><td>INTB:17</td><td></td><td></td></tr><tr><td>Int2</td><td>INTC:18</td><td></td><td></td></tr><tr><td>Int3</td><td>INTD:19</td><td></td><td></td></tr></table>

<table><tr><td>INT Line</td><td>PCIe Port 1</td><td>PCIe Port 2</td><td>PCIe Port 3</td><td>PCIe Port 4</td><td>PCIe Port 5</td><td>PCIe Port 6</td><td>PCIe Port 7</td></tr><tr><td>Int0</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td></tr><tr><td>Int1</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td></tr><tr><td>Int2</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td></tr><tr><td>Int3</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td><td>INTC:18</td><td>INTD:19</td><td>INTA:16</td><td>INTB:17</td></tr></table>

# SMBus Address Table

<table><tr><td>Device</td><td>Address</td></tr><tr><td>PTN3460</td><td>C0h</td></tr></table>

# 7. BIOS Configurations

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS Information</td><td>CPU Configuration</td><td rowspan="2">System Agent (SA)</td><td>Setup</td><td>Boot</td><td>Save Change and Exit</td></tr><tr><td>System Information</td><td>Power &amp; Performance</td><td>Administrator Password</td><td>Configuration</td><td>Exit</td></tr><tr><td>Board Information</td><td>Graphics Configuration</td><td>Configuration</td><td>Password</td><td>FIXED BOOT</td><td>Discard Changes and Exit</td></tr><tr><td>System Date and Time</td><td>Power Management</td><td>PCH-IO</td><td>User Password</td><td>ORDER Priorities</td><td>Save Changes and Reset</td></tr><tr><td>Access Level</td><td>System Management</td><td>Configuration</td><td>Secure Boot</td><td>UEFI USB Key Drive BBS Priorities</td><td>Discard Changes and Reset</td></tr><tr><td></td><td>Thermal Management</td><td></td><td></td><td></td><td>Save Options</td></tr><tr><td></td><td>Watchdog Timer</td><td></td><td></td><td></td><td>Boot Override</td></tr><tr><td></td><td>Super IO Configuration</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Miscellaneous</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>USB Configuration</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Serial Port Console Redirection</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Network Stack Configuration</td><td></td><td></td><td></td><td></td></tr><tr><td></td><td>Trusted Computing</td><td></td><td></td><td></td><td></td></tr></table>

# 7.1 Main

7.1.1 Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>ADLINK BIOS version</td></tr><tr><td>Build Date</td><td>Info only</td><td>ADLINK BIOS Build Date</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Display GOP Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display ME FW Version</td></tr><tr><td>BIOS Boot Source</td><td>Info only</td><td>Display BIOS Boot Source</td></tr></table>

7.1.2 Main > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name.</td></tr><tr><td>CPU Board version</td><td>Info only</td><td>Display CPU Board Version.</td></tr><tr><td>CPU Board String</td><td>Info only</td><td>Display CPU Board String.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU Frequency.</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display Installed Memory Size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display Memory Frequency.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH SKU Version</td></tr></table>

7.1.3 Main > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Board Information</td><td>Info only</td><td></td></tr><tr><td>Serial Number</td><td>Info only</td><td>Display SEMA serial Number.</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Display SEMA manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Display SEMA last repair date.</td></tr><tr><td>MAC ID</td><td>Info only</td><td>Display SEMA MAC ID.</td></tr><tr><td>Runtime Statistics</td><td>Info only</td><td></td></tr><tr><td>Total Runtime</td><td>Info only</td><td>The returned value specifies the total time in minutes the system is running in S0 state.</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>The returned value specifies the time in seconds the system is running in S0 state. This counter is cleared when the system is removed from the external power supply.</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>The returned value specifies the number of times the external power supply has been shut down</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>The Boot counter is increased after a HW- or SW-Reset or after a successful power-up.</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>The boot reason is the event which causes the reboot of the system.</td></tr></table>

7.1.4 Main > System Date/Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Info only</td><td></td></tr><tr><td>System Time</td><td>Info only</td><td></td></tr></table>

# 7.1.5 Main > Access Level

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# Advanced

# 7.2.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Configuration</td><td>Info only</td><td></td></tr><tr><td>Type</td><td>Info only</td><td>Socket Specific CPU Information.</td></tr><tr><td>ID</td><td>Info only</td><td>Display Microcode Patch.</td></tr><tr><td>Speed</td><td>Info only</td><td>Display Max CPU speed.</td></tr><tr><td>Stepping</td><td>Info only</td><td>Display Min CPU stepping.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>VMX</td><td>Info only</td><td>Display VMX support info.</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>Display SMX/TXT support info.</td></tr><tr><td>Intel Virtualization Technology</td><td>Disabled Enabled</td><td>When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.</td></tr><tr><td>Active Processor Cores</td><td>ALL123</td><td>Number of cores to enable in each processor package.</td></tr></table>

# 7.2.2 Advanced > Power & Performance

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU – Power Management Control</td><td>Submenu</td><td>CPU- Power Management Control Options</td></tr><tr><td>GT – Power Management Control</td><td>Submenu</td><td>GT- Power Management Control</td></tr></table>

# 7.2.2.1 Advanced > Power & Performance > CPU – Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU – Power Management Control</td><td>Info only</td><td></td></tr><tr><td>P0 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td>P1 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td>P2 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td>P3 Fused Max Core Ratio</td><td>Info only</td><td></td></tr><tr><td></td><td></td><td></td></tr><tr><td>Boot performance mode</td><td>Max Battery
Max Non-Turbo Performance
Turbo Performance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Intel(R) SpeedStep(tm)</td><td>Disabled
Enabled</td><td>Allows more than two frequency ranges to be supported</td></tr><tr><td>Race To Halt (RTH)</td><td>DisabledEnabled</td><td>Enable/Disable Race To Halt features. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>DisabledEnabled</td><td>Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.</td></tr><tr><td>HwP Autonomous EPP Grouping</td><td>DisabledEnabled</td><td>Enable EPP grouping (default bit 29 = 0, command 0x11) Autonomous will request the same values for all cores with same EPP. Disable EPP grouping (BIT 29 = 1, command 0x11) Autonomous will not necessarily request same values for all cores with same EPP.</td></tr><tr><td>EPB override over PECI</td><td>DisabledEnabled</td><td>Enable/Disable EPB override over PECI. Enable by sending pcode command 0x2b, subcommand 0x3 to1. This will allow OOB EPB PECI override control</td></tr><tr><td>HwP Fast MSR Support</td><td>DisabledEnabled</td><td>Enable/Disable HwP Fast MSR Support for IA32_HwP_REQUEST MSR.</td></tr><tr><td>HDC Control</td><td>DisabledEnabled</td><td>This option allows HDC configuration. Disabled: Disable HDC Enabled: Can be enabled by OS if OS native support is available.</td></tr><tr><td>View/Configure Turbo Options</td><td>Submenu</td><td>View/Configure Turbo Options</td></tr><tr><td>CPU VR Settings</td><td>Submenu</td><td>CPU VR Settings</td></tr><tr><td>Platform PL1 Enable</td><td>DisabledEnabled</td><td>Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window.</td></tr><tr><td>Platform PL2 Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Power Limit 4 override</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 4 override. If this option is disabled, BIOS will leave the default values for Power Limit 4.</td></tr><tr><td>C states</td><td>DisabledEnabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Enhanced C-states</td><td>DisabledEnabled</td><td>Enable/DISABLE C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.</td></tr><tr><td>C-State Auto Demotion</td><td>DisabledC1</td><td>Configure C-State Auto Demotion</td></tr><tr><td>C-State Un-demotion</td><td>DisabledC1</td><td>Configure C-State Un-demotion</td></tr><tr><td>Package C-State Demotion</td><td>DisabledEnabled</td><td>Package C-State Demotion</td></tr><tr><td></td><td></td><td></td></tr><tr><td>Package C-State Un-demotion</td><td>DisabledEnabled</td><td>Package C-State Un-demotion</td></tr><tr><td>CState Pre-Wake</td><td>DisabledEnabled</td><td>Disable – Sets bit 30 of POWER_CTL MSR(0x1FC) to 1 to disable the Cstate Pre-Wake</td></tr><tr><td>IO MWAIT Redirection</td><td>DisabledEnabled</td><td>When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset to MWAIT(offset)</td></tr><tr><td>Package C State Limit</td><td>C0/C1C2C3C6C7C7SC8C9C10Cpu DefaultAuto</td><td>Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit.</td></tr><tr><td>C6/C7 Short Latency Control(MSR 0x60B)</td><td>Info only</td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value – bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C6/C7 Long Latency Control(MSR 0x60C)</td><td>Info only</td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value - bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C8 Latency Control(MSR 0x633)</td><td></td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value - bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C9 Latency Control(MSR 0x634)</td><td></td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value - bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>C10 Latency Control(MSR 0x635)</td><td></td><td></td></tr><tr><td>Time Unit</td><td>1 ns32ns1024ns32768 ns1048576 ns33554432 ns</td><td>Unit of measurement for IRTL value - bits [12:10]</td></tr><tr><td>Latency</td><td>0-1023</td><td>Interrupt Response Time Limit value- bits [9:0], Enter 0-1023</td></tr><tr><td>Thermal Monitor</td><td>DisabledEnabled</td><td>Enable/Disable Thermal Monitor</td></tr><tr><td>Interrupt Redirection mode Selection</td><td>Fixed PriorityRound robinHash VectorNo Change</td><td>Interrupt Redirection Mode Select for Logical Interrupts</td></tr><tr><td>Timed MWAIT</td><td>DisabledEnabled</td><td>Enable/Disable Timed MWAIT Support</td></tr><tr><td>Custom P-state Table</td><td>Submenu</td><td></td></tr><tr><td>EC Turbo Control Mode</td><td>DisabledEnabled</td><td>Enable/Disable EC Turbo Control mode</td></tr><tr><td>Energy Performance Gain</td><td>DisabledEnabled</td><td>Enable/Disable Energy Performance Gain.</td></tr><tr><td>EPG DIMM ldd3N</td><td>26</td><td>Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis.</td></tr><tr><td>EPG DIMM ldd3P</td><td>11</td><td>Active power-down current(Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis.</td></tr><tr><td>Power Limit 3 Settings</td><td>Submenu</td><td></td></tr><tr><td>CPU Lock Configuration</td><td>Submenu</td><td>CPU Lock Configuration</td></tr></table>

7.3.2.1.1 Advanced > Thermal Management > CPU – Power Management > View/Configure Turbo Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Current Turbo Settings</td><td>Info only</td><td></td></tr><tr><td>Max Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Min Turbo Power Limit</td><td>Info only</td><td></td></tr><tr><td>Package TDP Limit</td><td>Info only</td><td></td></tr><tr><td>Power Limit 1</td><td>Info only</td><td></td></tr><tr><td>Power Limit 2</td><td>Info only</td><td></td></tr><tr><td>1-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>2-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>3-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>4-core Turbo Ratio</td><td>Info only</td><td></td></tr><tr><td>Energy Efficient P-state</td><td>DisabledEnabled</td><td>Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function 6 ECX[3] will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS MSR</td></tr><tr><td>Package Power Limit MSR Lock</td><td>DisabledEnabled</td><td>Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register.</td></tr><tr><td>Power Limit 1 Override</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 1 override. If this option is disabled, BIOS will program the default values for Power Limit 1 and Power Limit 1 Time Window.</td></tr><tr><td>Power Limit 2 Override</td><td>DisabledEnabled</td><td>Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2.</td></tr><tr><td>Power Limit 2</td><td>0</td><td>Power Limit 2 value in milli-watts. BIOS will round to the nearest 1/8W when programming. If the value is 0, BIOS will program this value as 1.25*TDP. For 12.50W, enter 12500. Processor applies control policies such that the package power does not exceed this limit.</td></tr><tr><td>1-Core Ratio Limit Override</td><td>19</td><td>1-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.</td></tr><tr><td>2-Core Ratio Limit Override</td><td>19</td><td>2-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.</td></tr><tr><td>3-Core Ratio Limit Override</td><td>19</td><td>3-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.</td></tr><tr><td>4-Core Ratio Limit Override</td><td>19</td><td>4-Core Ratio Limit with range 0 to 83. The Minimum range may vary between Processors. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.</td></tr><tr><td>Energy Efficient Turbo</td><td>DisabledEnabled</td><td>Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, leave enabled.</td></tr></table>

7.3.2.1.2 Advanced > Thermal Management > CPU – Power Management > CPU VR Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU VR Settings</td><td>Info only</td><td></td></tr><tr><td>PSYS Slope</td><td>0</td><td></td></tr><tr><td>PSYS Offset</td><td>0</td><td></td></tr><tr><td>PSYS PMax Power</td><td>+ -</td><td></td></tr><tr><td>Acoustic Noise Settings</td><td>Submenu</td><td>Configure Acoustic Noise Settings for IA, GT and SA domains</td></tr><tr><td>VccIn VR Settings</td><td>Submenu</td><td>VccIn VR Settings</td></tr><tr><td>RFI Settings</td><td>Submenu</td><td>RFI Settings</td></tr></table>

7.3.2.1.3 Advanced > Thermal Management > CPU – Power Management > Custom P-state Table

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Custom P-state Table</td><td>Info only</td><td></td></tr><tr><td>Number of P states</td><td>0</td><td>Sets the number of custom P-states. At least 2 states must be present.</td></tr></table>

7.3.2.1.4 Advanced > Thermal Management > CPU – Power Management > CPU Lock Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CFG Lock</td><td>DisabledEnabled</td><td>Configure MSR 0xE2[15], CFG Lock bit</td></tr><tr><td>Overclocking Lock</td><td>DisabledEnabled</td><td>Enable/Disable Overclocking Lock (BIT 20) in FLEX_RATIO(194) MSR</td></tr></table>

7.2.2.2 Advanced > Power & Performance > GT – Power Management Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GT – Power Management Control</td><td>Info only</td><td></td></tr><tr><td>RC6(Render Standby)</td><td>DisabledEnabled</td><td></td></tr><tr><td>Maximum GT frequency</td><td>Default Max Frequency100Mhz150Mhz200Mhz250Mhz300Mhz350Mhz400Mhz450Mhz500Mhz550Mhz600Mhz650Mhz700Mhz750Mhz800Mhz850Mhz900Mhz950Mhz1000Mhz1050Mhz1100Mhz1150Mhz1200Mhz</td><td>Maximum GT frequency limited by the user. Choose between 400MHz (RPN) and 400MHz (RP0). Value beyond the range will be clipped to min/max supported by SKU</td></tr><tr><td>Disable Turbo GT frequency</td><td>EnabledDisabled</td><td>Enabled: Disables Turbo GT frequency. Disabled: GT frequency is not limited</td></tr></table>

7.2.3 Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nxp configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>VESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>Dual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>LVDS Backlight Mode</td><td>EC ModeGTT Mode</td><td>Select LVDS Backlight control function.</td></tr><tr><td>LVDS Backlight</td><td>Submenu</td><td></td></tr><tr><td>DDI port 1</td><td>No DeviceDisplay PortHDMIDisplayPort WithHDMI/DVI Compatible</td><td>DDI port 1 function choose to Display Port or HDMI</td></tr><tr><td>DDI port 2</td><td>No DeviceDisplay PortHDMIDisplayPort WithHDMI/DVI Compatible</td><td>DDI port 2 function choose to Display Port or HDMI</td></tr></table>

7.2.3.1 Advanced > Graphics Configuration > LVDS Backlight

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS Backlight</td><td>Info Only</td><td></td></tr><tr><td>LVDS Backlight Brightness</td><td>0-255</td><td>A change takes effect immediately.The value range starts by 0 and ends by 255.</td></tr></table>

7.2.4 Advanced > AMI Graphic Output Protocol Policy

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Intel (R) Graphics Controller</td><td>Info Only</td><td></td></tr><tr><td>Intel (R) GOP Driver</td><td>Info Only</td><td></td></tr><tr><td>Output Select</td><td>DP1[ACTIVE Current]</td><td>Output Interface</td></tr></table>

7.2.5 Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Management</td><td>Info Only</td><td></td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enables or Disables BIOS ACPI Auto Configuration</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State), This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend DisabledS3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>LID Function</td><td>DisabledEnabled</td><td>Enable/Disable LID Function.</td></tr><tr><td>ECO Mode</td><td>DisabledEnabled</td><td>Reduces the power consumption of the system, but after a shut down, you have to wait at least 5 seconds beforeyou can restart the system.</td></tr><tr><td>Power-Up Mode</td><td>Turn OnRemain OffLast State</td><td>Turn on: The machine starts automatically when the power supply is turned on.Remain Off: To start the machine the power button has to be pressed.Last State: The machine will power up to last power state.</td></tr><tr><td>Power Consumption</td><td>Submenu</td><td>Power Consumption.</td></tr></table>

7.2.6 Advanced > System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Management</td><td>Info Only</td><td></td></tr><tr><td>Version</td><td>Info Only</td><td>Display SEMA Module Version.</td></tr><tr><td>SEMA Firmware</td><td>Info Only</td><td>Display SEMA Firmware Version.</td></tr><tr><td>SEMA Flags</td><td>Submenu</td><td>Display SEMA Flags</td></tr><tr><td>SEMA Features</td><td>Info</td><td>Display SEMA Supported Features</td></tr></table>

7.2.6.1 Advanced > System Management > SEMA Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Flags</td><td>Info Only</td><td></td></tr><tr><td>BIOS Select</td><td>Info Only</td><td></td></tr><tr><td>ATX/AT-Mode</td><td>Info Only</td><td></td></tr></table>

7.2.7 Advanced > Thermal Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Thermal Management</td><td>Info Only</td><td></td></tr><tr><td>Critical Trip Point</td><td>Disabled80 C90 C95 C</td><td>The value is the temperature threshold of the Critical Trip Point.</td></tr><tr><td>Passive Cooling Trip Point</td><td>Disabled70 C80 C90 C100 C</td><td>The value is the temperature threshold of the Passive Cooling Trip Point.</td></tr><tr><td>Active Cooling Trip Point</td><td>40 C50 C60 C70 CRefer to BMC</td><td>This value is the temperature threshold of the active cooling trip point.</td></tr><tr><td>Watchdog ACPI Event Shutdown</td><td>DisabledEnabled</td><td>Watchdog ACPI Event Shutdown Enabled/Disabled</td></tr><tr><td>Temperature and Fan Speed</td><td>Submenu</td><td></td></tr></table>

7.2.7.1 Advanced > Thermal Management > Temperatures

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Temperatures</td><td>Info Only</td><td></td></tr><tr><td>CPU Temperature</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Display Current CPU Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Display Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Display Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Display Max Board Temperature</td></tr><tr><td>Board Temperatures</td><td>Info Only</td><td></td></tr><tr><td>Current</td><td>Info Only</td><td>Display Current Board Temperature</td></tr><tr><td>Startup</td><td>Info Only</td><td>Display Startup Board Temperature</td></tr><tr><td>Min</td><td>Info Only</td><td>Display Min Board Temperature</td></tr><tr><td>Max</td><td>Info Only</td><td>Display Max Board Temperature</td></tr></table>

7.2.8 Advanced > Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>Power-Up Watchdog</td><td>Disabled Enabled</td><td>The Power Up Watchdog resets the system after a certain amount of time after power up. Pressing F12 during start up disables the Power Up Watchdog</td></tr><tr><td>Timeout</td><td>65535</td><td>Here you can enter the time the Power Up Watchdog should wait until it resets the system. The value range starts by 24 and ends by 65535</td></tr></table>

7.2.9 Advanced > Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>IT5121E Super IO Configuration</td><td>Submenu</td><td>System Super IO Chip Parameters.</td></tr></table>

7.2.9.1 Advanced > Super IO Configuration > IT5121E Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IT5121E Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1/2 Configuration</td><td>Submenu</td><td>Set Parameters of Serial Port 1/2</td></tr><tr><td>Serial Port 1/2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info Only</td><td>Display IO / IRQ information of COM Port.</td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h/2F8h; IRQ=4;IO=3F8h;IRQ=3,4,5,6,7,10,11,12IO=2F8h;IRQ=3,4,5,6,7,10,11,12IO=3E8h;IRQ=3,4,5,6,7,10,11,12IO=2E8h;IRQ=3,4,5,6,7,10,11,12</td><td>Select an optimal setting for Super IO Device.</td></tr><tr><td>Change Settings</td><td>NormalHigh Speed</td><td>Select an optimal settings for Super IO Device</td></tr></table>

7.2.10 Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchangedata.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM2</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM3</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>COM4</td><td>Info only</td><td></td></tr><tr><td>Console Redirection</td><td>EnabledDisabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data.Both computers should have the same or compatible settings.The item will be lunched before enable Console Redirection.</td></tr><tr><td>Legacy Console Redirection</td><td>Info only</td><td></td></tr><tr><td>Legacy Console Redirection Settings</td><td>Submenu</td><td>Legacy Console Redirection Settings</td></tr></table>

7.2.10.1 Advanced > Serial Console Redirection > Console Redirection Settings (if COM1 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.2.10.2 Advanced > Serial Console Redirection > Console Redirection Settings (if COM2 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM2</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad onPutty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.2.10.3 Advanced > Serial Console Redirection > Console Redirection Settings (if COM3 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM3</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.2.10.4 Advanced > Serial Console Redirection > Console Redirection Settings (if COM4 enabled)

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM4</td><td>Info only</td><td></td></tr><tr><td>Console Redirection Settings</td><td>Info only</td><td></td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII char set.VT100: ASCII char set.VT100+: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if thenumof 1's in the data bits is even.Odd: parity bit is 0 ifnumof 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/stop signals.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>EnabledDisabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent.This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>EnabledDisabled</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Legacy OS Redirection Resolution</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Putty KeyPad</td><td>VT100Intel LinuxXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad onPutty.</td></tr><tr><td>Redirection After BIOS POST</td><td>Always EnableBootLoader</td><td>When Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS. When Always Enable is selected, then Legacy Console Redirection is enabled for legacy OS. Default setting for this option is set to Always Enable.</td></tr></table>

7.2.10.5 Advanced > Serial Console Redirection >Legacy Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Legacy Serial Redirection Port</td><td>COM1COM2COM3COM4</td><td>Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages</td></tr></table>

7.2.11 Advanced > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td>Info Only</td><td></td></tr><tr><td>Power Supply Unit</td><td>Emulate AT ModeATX Mode</td><td>Select Emulation AT or ATX function. If this option set to [Emulation AT], BIOS will report no suspend functions (S3 &amp; S4) to ACPI OS. In windows XP, it will make OS show shutdown message during system shutdown. ATX: OS will turn off system power when shutdown.</td></tr><tr><td>I2C Speed Control</td><td>100 kbps400 kbps</td><td>I2C Speed Control</td></tr><tr><td>Smart Battery Function</td><td>DisabledEnabledAuto</td><td>Enable/Disable Smart Battery function. Auto: disable Smart Battery function if charger IC not be detected.</td></tr><tr><td>WOL From S5</td><td>ONOFF</td><td>This Config to control power on/off LAN in S5 State by SEMA (EC).</td></tr></table>

7.2.12 Advanced > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>USB Module Version</td><td>Info Only</td><td>Display USB Module Version</td></tr><tr><td>USB Controllers:</td><td>Info Only</td><td>Display USB Controllers is XHCI or EHCI.</td></tr><tr><td>USB Devices:</td><td>Info Only</td><td>Display attachment USB devices.</td></tr><tr><td>Legacy USB Support</td><td>EnabledDisabledAuto</td><td>Enables Legacy USB support.Auto option disables legacy support if no USB devices are connected.Disable option will keep USB devices available only for EFI applications.</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support.The XHCI ownership change should be claimed by XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>DisabledEnabled</td><td>Enable / Disable USB Mass Storage Driver Support.</td></tr><tr><td>USB hardware delays and time-outs:</td><td>Info Only</td><td></td></tr><tr><td>USB transfer rime-out</td><td>1 sec5sec10sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>AutoManual</td><td>Maximum time the device will take before it properly reports itself to the Hot Controller.&#x27;Auto&#x27; uses default value: for a Root po\rt it is 100 ms, for a Hub port the delay is taken form Hub descriptor.</td></tr></table>

7.2.13 Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>DisableEnable</td><td>Enable / Disable UEFI Network Stack.</td></tr></table>

7.2.14 Advanced > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>TPM20 Device Found</td><td>Info Only</td><td></td></tr><tr><td>Security Device Support</td><td>DisableEnable</td><td>Enables or Disable BIOS support for security device.OS will not show Security Device.TCG EFI protocol and available.</td></tr></table>

# 7.3 Chipset

7.3.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>Submenu</td><td>Memory Configuration Parameters</td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td>Graphics Configuration</td></tr><tr><td>VT-D</td><td>DisabledEnabled</td><td>VT-d capability</td></tr><tr><td>GNA Device</td><td>DisabledEnabled</td><td>Enable/Disable SA GNA Device.</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>DisabledEnabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignment. This is enabled automatically when Aperture Size is set to 2048MB.</td></tr></table>

7.3.1.1 Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory Configuration</td><td>Info Only</td><td></td></tr><tr><td>Memory RC Version</td><td>Info Only</td><td></td></tr><tr><td>Memory Data Rate</td><td>Info Only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info Only</td><td></td></tr><tr><td>Channel 0 Slot 0</td><td>Info Only</td><td></td></tr><tr><td>Channel 1 Slot 0</td><td>Info Only</td><td></td></tr><tr><td>Size</td><td>Info Only</td><td></td></tr><tr><td>Number of Ranks</td><td>Info Only</td><td></td></tr><tr><td>Manufacturer</td><td>Info Only</td><td></td></tr><tr><td>Maximum Memory Frequency</td><td>Auto1067120013331400......4267</td><td>Maximum Memory Frequency in Mhz. Must divide by 133 or 100 according to the refclk. In Gear2 must divide by 266 or 200. Lowest Gear2 speed is 2133</td></tr><tr><td>HOB Buffer Size</td><td>Auto1B1KBMax (assuming 63KB total HOB size)</td><td>Size to set HOB Buffer</td></tr><tr><td>Max TOLUD</td><td>Dynamioc1 GB1.25 GB......3.5GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller</td></tr><tr><td>SA GV</td><td>DisabledFixed LowFixed MidFixed HighEnabled</td><td>System Agent Geyserville. Can disable, fix to a specific point, or enable frequency switching.</td></tr><tr><td>In-Band ECC</td><td>EnabledDisabled</td><td>Enable/Disable In-Band ECC.</td></tr><tr><td>In-Band ECC Operation Mode</td><td>012</td><td>0: Functional Mode protects requests based on the address range, 1: Makes all requests non protected and ignore range checks, 2:Makes all requests protected and ignore range checks</td></tr><tr><td>In-Band ECC Error Injection</td><td>EnabledDisabled</td><td>By enabling this Error Injection Enabling feature, the user acknowledges the security risks. Enabling ErrorInjection allows attackers who have access to the Host Operating System to inject IBECC errors that can cause unintended memory corruption and enable the leak of security data in the BIOS stolen memory regions</td></tr><tr><td>Memory Remap</td><td>EnabledDisabled</td><td>Enable/Disable Memory Remap above 4GB</td></tr><tr><td>Memory Test on Warm Boot</td><td>DisabledEnabled</td><td>Enable Or Disable Base Memory Test Run on Warm Boot</td></tr></table>

7.3.1.2 Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>Info Only</td><td></td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCIe</td><td>Select which of IGFX/PEG/PCIe Graphics device should be Primary Display Or select HG for Hybrid Gfx.</td></tr><tr><td>External Gfx Card Primary Display Configuration</td><td>Submenu</td><td>External Gfx Card Primary Display Configuration</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB</td><td>Select the Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M32M46M96M128M......60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128256MAX</td><td>Select DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>Intel Graphics Pei Display Peim</td><td>EnabledDisabled</td><td>Enable/Disable Pei (Early) Display</td></tr></table>

7.4.1.2.1 Chipset > System Agent (SA) Configuration > Graphics Configuration > External Gfx Card Primary Display Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>External Gfx Card Primary Display Configuration</td><td>Info Only</td><td></td></tr><tr><td>Primary PCIE</td><td>Auto</td><td>Select Auto/PCIE1/PCIE2/PCIE3/PCIE4/PCIE5/PCIE6/PCIE7 of D28:F0/F1/F2/F3/F4/F5/F6/F7,PCIE8/PCIE9/PCIE10/PCIE11/PCIE12/PCIE13/PCIE14/PCIE15 of D29:F0/F1/F2/F3/F4/F5/F6/F7,PCIE16/PCIE17/PCIE18/PCIE19 of D27:F0/F1/F2/F3, Graphics device should be Primary PCIE.</td></tr></table>

7.3.2 Chipset > PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCH-IO Configuration</td><td>Info Only</td><td>Memory Configuration Parameters</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td>PCI Express Configuration setting</td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td>SATA Device Options Settings</td></tr><tr><td>USB Configuration</td><td>Submenu</td><td>USB Configuration settings</td></tr><tr><td>Security Configuration</td><td>Submenu</td><td>Security Configuration setting</td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td>HD Audio Subsystem Configuration Settings</td></tr><tr><td>SCS Configuration</td><td>Submenu</td><td>Storage and Communication Subsystem (SCS) Configuration</td></tr><tr><td>PSE Configuration</td><td>Submenu</td><td>Programmable Service Engine (PSE) Configuration</td></tr><tr><td>TSN GBE Configuration</td><td>Submenu</td><td>Time Sensitive Network GBE Configuration</td></tr><tr><td>Enhance Port 80h LPC Decoding</td><td>DisabledEnabled</td><td>Support the word/dword decoding of port 80h behind LPC</td></tr><tr><td>Enable TCO Timer</td><td>DisabledEnabled</td><td>Enable/Disable TCO timer. When disabled, it disables PCH ACPI timer, stops TCO timer, and ACPI WDAT table will not be published.</td></tr><tr><td>PCIe PII SSC</td><td>Auto</td><td>Pcie PII SSC percentage.AUTO - Keep hw default, no BIOS override. Range is 0.0%-2.0%.</td></tr><tr><td>SPD Write Disable</td><td>TRUEFALSE</td><td>Enable/Disable setting SPD Write Disable. For security recommendations, SPD write disable bit must be set.</td></tr></table>

7.3.2.1 Chipset > PCH-IO Configuration > PCIE Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Info Only</td><td></td></tr><tr><td>DMI Link ASPM Control</td><td>DisabledL0sL1L0sL1Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>PCIE Ports 1-4 Configuration</td><td>4x1 Port1x2 2x1 Port2x2 Port1x4 Port</td><td>To configure PCI-E Port 1-4 of PCH.[4X1]:Port 1-4 (x1) and Port 8 (x1) / [1x2 2x1]:Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1) / [2x2]:Port 1-2 (x2) and Port 3-4 (x2) / [1x4]:Port 1 (x4), Ports 2-4 (disabled)</td></tr><tr><td>Port8xh Decode</td><td>DisabledEnabled</td><td></td></tr><tr><td>Peer Memory Write Enable</td><td>DisabledEnabled</td><td></td></tr><tr><td>Compliance Test Mode</td><td>DisabledEnabled</td><td></td></tr><tr><td>PCH PCI Express Clock Gating</td><td>Platform-POREnabledDisabled</td><td></td></tr><tr><td>PCIe function swap</td><td>DisabledEnabled</td><td></td></tr><tr><td>PCIe EQ settings</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port 1/2/3/4/5/6/7</td><td>Submenu</td><td></td></tr><tr><td>PCIE clocks</td><td>Submenu</td><td></td></tr></table>

7.4.2.1.1 Chipset > PCH-IO Configuration > PCI Express Configuration > PCIe EQ Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe EQ override</td><td>DisabledEnabled</td><td>Choose your own PCIe EQ settings, only for users who have a thorough understanding of equalization process</td></tr></table>

7.4.2.1.2 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port 1/2/3/4/5/6/7/

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 1/2/3/4/5/6/7/</td><td>DisabledEnabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Build-inSlot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot. SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level:Force L0s – Force all links to L0s StateAuto – BIOS auto configureDISABLE – Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisabledL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>ACS</td><td>DisabledEnabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>DisabledEnabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>DisabledEnabled</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>DisabledEnabled</td><td>Enable/Disable Rootport extensions for Downstream Port Containment</td></tr><tr><td>URR</td><td>DisabledEnabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable.</td></tr><tr><td>FER</td><td>DisabledEnabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable.</td></tr><tr><td>NFER</td><td>DisabledEnabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>DisabledEnabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>SEFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable.</td></tr><tr><td>SECE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>DisabledEnabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>Advanced Error Reporting</td><td>DisabledEnabled</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Halt Swing</td><td>DisabledEnabled</td><td>Transmitter Half Swing Enable/Disable.</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory for this Root Bridge (1-20) MB</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info Only</td><td></td></tr><tr><td>LTR</td><td>DisabledEnabled</td><td>PCH PCIE Latency Reporting Enable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE level. Disabled: Disable override.Manual: Manual enter override values.Auto (default): Maintain default bios flow.</td></tr><tr><td>Force LTR Override</td><td>DisabledEnabled</td><td>Force LTR Override for PCH PCIE.</td></tr><tr><td>LTR Lock</td><td>DisabledEnabled</td><td>PCIE LTR Configuration Lock</td></tr><tr><td>Extra options</td><td>Submenu</td><td></td></tr></table>

7.4.2.1.2.1 Chipset > PCH-IO Configuration > PCI Express Configuration > PCI Express Root Port 1/2/3/4/5/6/7/ > Extra Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Detect Non-Compliance Device/</td><td>DisabledEnabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr><tr><td>Prefetchable Memory</td><td>10</td><td>Prefetchable Memory Range for this Root Bridge.</td></tr><tr><td>Reserved Memory Alignment</td><td>1</td><td>Reserved Memory Alignment (0 - 31 bits)</td></tr><tr><td>Prefetchable Memory Alignment</td><td>1</td><td>Prefetchable Memory Alignment (0 - 31 bits)</td></tr></table>

7.4.2.1.3 Chipset > PCH-IO Configuration > PCI Express Configuration > PCIe Clocks

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Clock0 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock0</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock1 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock1</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock2 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock2</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock3 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock3</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock4 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock4</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr><tr><td>Clock5 assignment</td><td>Platform-POREnabledDisabled</td><td>Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabled even if unused. Disabled = Disable clock.</td></tr><tr><td>ClkReq for Clock5</td><td>Platform-PORDisabled</td><td>Platform-POR = CLKREQ signal is assigned to CLKSRC according to board layout. Disabled = CLKREQ will not be used.</td></tr></table>

7.3.2.2 Chipset > PCH-IO Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Configuration</td><td>Info Only</td><td></td></tr><tr><td>SATA Controller</td><td>Submenu</td><td>PCI Express Configuration setting</td></tr><tr><td>SATA Mode Selection</td><td>AHCI</td><td>Determines how SATA controller(s) operate.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>SATA Ports Multiplier</td><td>EnabledDisabled</td><td>Ports Multiplier Enable/Disable</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabled</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td>RST Legacy OROM/RST UEFI driver will refer to the SWFM configuration to enable/disable the storage features.</td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>Serial ATA Port x</td><td>Info Only</td><td></td></tr><tr><td>Software Preserve</td><td>Info Only</td><td></td></tr><tr><td>Port0</td><td>DisabledEnabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>Configured as eSATA</td><td>Info Only</td><td></td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>Topology</td><td>UnknownISATADirect ConnectFlexM2</td><td>Identify the SATA Topology if it is Default or ISATA or Flex or DirectConnect or M2</td></tr><tr><td>SATA Portx DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior might happen. Please check board design before enabling it.</td></tr><tr><td>SATA Portx RxPolarity</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port 0 RxPolarity. Default should disable, please check board design before enable it.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>DITO value</td><td>Info Only</td><td></td></tr><tr><td>DM Value</td><td>Info Only</td><td></td></tr></table>

7.4.2.2.1 Chipset > PCH-IO Configuration > SATA Configuration > Software Feature Mask Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Software Feature Mask Configuration</td><td>Info Only</td><td></td></tr><tr><td>HDD Unlock</td><td>DisabledEnabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr><tr><td>LED Locate</td><td>DisabledEnabled</td><td>If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.</td></tr></table>

7.3.2.3 Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Configuration</td><td>Info Only</td><td></td></tr><tr><td>XHCI Compliance Mode</td><td>DisabledEnabled</td><td>Option to enable Compliance Mode. Default is to disable Compliance Mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>xDCI Support</td><td>DisabledEnabled</td><td>Enable/Disable xDCI (USB OTG Device).</td></tr><tr><td>USB2 PHY Sus Well Power Gating</td><td>GEN1GEN2</td><td>Select &#x27;Enabled&#x27; to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H</td></tr><tr><td>USB3 Link Speed Selection</td><td>DisabledEnabled</td><td>This option is to select USB3 Link Speed GEN1 or GEN2</td></tr><tr><td>USB PD0 Programming</td><td>DisabledEnabled</td><td>Select &#x27;Enabled&#x27; if Port Disable Override functionality is used.</td></tr><tr><td>USB Overcurrent</td><td>DisabledEnabled</td><td>Select &#x27;Disabled&#x27; for pin-based debug. If pin-based debug is enabled but USB overcurrent is not disabled, USB DbC does not work.</td></tr><tr><td>USB Overcurrent Lock</td><td>DisabledEnabled</td><td>Select &#x27;Enabled&#x27; if Overcurrent functionality is used. Enabling this will make xHCI controller consume the Overcurrent mapping data</td></tr><tr><td>USB Port Disable Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB Device/HOST Mode Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enable/Disable the corresponding USB 2.0 and USB 3.0 port device mode</td></tr><tr><td>USB UCSI ACPI device</td><td>DisabledEnabled</td><td>Enable/Disable USB UCSI ACPI device</td></tr></table>

7.3.2.4 Chipset > PCH-IO Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Configuration</td><td>Info Only</td><td></td></tr><tr><td>RTC Memory Lock</td><td>DisabledEnabled</td><td>Enable will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM</td></tr><tr><td>BIOS Lock</td><td>DisabledEnabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr><tr><td>Force unlock on all GPIO pads</td><td>DisabledEnabled</td><td>If Enabled BIOS will force all GPIO pads to be in unlocked state</td></tr></table>

7.3.2.5 Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio Subsystem Configuration Settings</td><td>Info Only</td><td></td></tr><tr><td>HD Audio</td><td>DisabledEnabled</td><td>Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled.</td></tr></table>

7.3.2.6 Chipset > PCH-IO Configuration > SCS Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>eMMC 5.1 Controller</td><td>DisabledEnabled</td><td>Enable or Disable SCS eMMC 5.1 Controller</td></tr><tr><td>eMMC 5.1 HS400 Mode</td><td>DisabledEnabled</td><td>Enable or Disable SCS eMMC 5.1 HS400 Mode</td></tr><tr><td>Enable HS400 software tuning</td><td>DisabledEnabled</td><td>Software tuning should improve eMMC HS400 stability at the expense of boot time</td></tr><tr><td>Driver Strength</td><td>33 0hm40 0hm50 0hm</td><td>Sets I/O driver strength</td></tr><tr><td>SDCard 3.0 Controller</td><td>DisabledEnabled</td><td>Enable or Disable SCS SDHC 3.0 Controller</td></tr></table>

7.3.2.7 Chipset > PCH-IO Configuration > PSE Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PSE Controller</td><td>DisabledEnabled</td><td>Enables/Disables Programmable Service Engine (PSE) Device</td></tr><tr><td>PSE DashBoard Configuration</td><td>Info Only</td><td></td></tr><tr><td>LOG OUTPUT CHANNEL</td><td>3</td><td>Determine the PSE log output channel</td></tr><tr><td>LOG OUTPUT OFFSET</td><td>0</td><td>Determine the PSE log output region offset in memory</td></tr><tr><td>LOT OUTPUT SIZE</td><td>0</td><td>Determine the PSE log output region size limitation in memory</td></tr><tr><td>Shell</td><td>DisabledEnabled</td><td>Enable/Disable PSE Shell</td></tr><tr><td>Eclite</td><td>DisabledEnabled</td><td>Enable/Disable PSE Eclite Service</td></tr><tr><td>OOB</td><td>DisabledEnabled</td><td>Enable/Disable PSE OOB Service</td></tr><tr><td>WOL</td><td>DisabledEnabled</td><td>Enable/Disable PSE GBE WoL</td></tr><tr><td>PSE Debug (JTAGSWD) Enable</td><td>DisabledEnabled</td><td>PSE JTAG/SWD Debug enable. Set to enable. Unset to disable</td></tr><tr><td>PSE JTAG/SWD PIN MUX</td><td>DisabledEnabled</td><td>Enable/Disable PSE Jtag Pin Mux. Grayed out if Sci Pin Mux is enabled</td></tr><tr><td>PSE Add-In-Card</td><td>DisabledEnabled</td><td>Enable/Disable PSE Add-In-Card</td></tr><tr><td>PSE IP Ownership and GPIO Mux Assignment Configuration</td><td>Info Only</td><td></td></tr><tr><td>UART1/SER3</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE UART0 to host owned because UART0 is the function 0 of this device.\nUART0 has no pin conflict. UART1 has pin conflict with TGPIO.\nUART2 is default enabled for PSE logging purpose.\nUART3 has pin conflict with GBE0-1, PWM and TGPIO. UART4 has no pin conflict.\nUART5 has pin conflict with GBE1.\nIf it is grayed out, check the above options.The same pin cannot be assigned to multiple IP.</td></tr><tr><td>UART1/SER3 ACPI UART SubDevice</td><td>DisabledEnabled</td><td>Enable/Disable ACPI Uart Subdevice for Windows. Disable for Linux</td></tr><tr><td>UART1/SER3 ACPI UART Baudrate</td><td>9600192003840057600115200</td><td>Select default Baudrate</td></tr><tr><td>Uart4/SER2</td><td>NonePSE owned with pin muxedHost owned with pinmuxed</td><td>To assign this device to host owned, you must enable PSE UART0 to host owned because UART0 is the function 0 of this device.\nUART0 has no pin conflict. UART1 has pin conflict with TGPIO.\nUART2 is default enabled for PSE logging purpose.\nUART3 has pin conflict with GBE0-1, PWM and TGPIO. UART4 has no pin conflict.\nUART5 has pin conflict with GBE1.\nlf it is grayed out, check the above options. The same pin cannot be assigned to multipleIP.</td></tr><tr><td>UART4/SER2 ACPI UART SubDevice</td><td>DisabledEnabled</td><td>Enable/Disable ACPI Uart Subdevice for Windows. Disable for Linux</td></tr><tr><td>UART4/SER2 ACPI UART Baudrate</td><td>9600192003840057600115200</td><td>Select default Baudrate</td></tr><tr><td>I2C5</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C0 to host owned because I2C0 is the function 0 of this device.\nI2C1 has pin conflict with TGPIO8-9\nI2C2 has no pin conflict.I2C3 has pin conflict with TGPIO18-19.I2C4 has no pin conflict.I2C5 has pin conflict with PWM.\nI2C6 has no pin conflict.I2C7 has no pin conflict If it is greyed out, check the above options. The same pin cannot be assigned to multiple IP.</td></tr><tr><td>I2C7</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>If I2C7 is not set to host owned, all PSE CAN and QEP devices could not be set to host owned too due to sharing same function.I2C7 can't assign Host own if UCSI ACPI device enabled</td></tr><tr><td>CAN0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.CAN0 has pin conflict with I2S0 and TGPIO 16-17.\nCAN1 has pin conflict with I2S0 and TGPIO14-15.If it is greyed out, check the above options. The same pin cannot be assigned to multiple IP.</td></tr><tr><td>CAN1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>To assign this device to host owned, you must enable PSE I2C7 to host owned because I2C7 is the function 0 of this device.CAN0 has pin conflict with I2S0 and TGPIO 16-17.\nCAN1 has pin conflict with I2S0 and TGPIO14-15.If it is greyed out, check the above option. The same pin cannot be assigned to multiple IP.</td></tr><tr><td>GBE0</td><td>NonePSE owned with pin muxed</td><td>Select ownership for GBE</td></tr><tr><td></td><td>Host owned with pin muxed</td><td></td></tr><tr><td>PSE GBE0 DLL Overrid</td><td>DisabledEnabled</td><td>Enable/Disable PSE GBE0 DLL.To Enable this GBE1 must be Enabled</td></tr><tr><td>GBE1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Select ownership for GBE</td></tr><tr><td>PSE GBE1 DLL Overrid</td><td>DisabledEnabled</td><td>Enable/Disable PSE GBE1 DLL.To Enable this GBE1 must be Enabled</td></tr><tr><td>GPIO/TGPIO 0</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Owner of GPIO/TGPIO 0 Controller (PSE or HOST owned).</td></tr><tr><td>GPIO/TGPIO 0 MUX SELECTION</td><td>LOWERMIDTOPAll pins are GPIO</td><td>Choose Top, Mid, Lower or All mux for GPIO/TGPIO 1 Controller Instance.</td></tr><tr><td>GPIO/TGPIO 0 Pin Selection</td><td>Submenu</td><td>Enable individual GPIO/TGPIO pin</td></tr><tr><td>GPIO/TGPIO 1</td><td>NonePSE owned with pin muxedHost owned with pin muxed</td><td>Owner of GPIO/TGPIO 1 Controller(PSE or HOST owned).</td></tr><tr><td>GPIO/TGPIO 1 MUX SELECTION</td><td>LOWERMIDTOPAll pins are GPIO</td><td>Choose Top, Mid, Lower or All mux for GPIO/TGPIO 1 Controller Instance.</td></tr><tr><td>GPIO/TGPIO 1 Pin SELECTION</td><td>Submenu</td><td>Enable individual GPIO/TGPIO pin</td></tr><tr><td>PSE Interrupt Assignment Configuration</td><td>Info Only</td><td></td></tr><tr><td>I2S0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2S1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART1/SER3</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>UART4/SER2</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>I2C5</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>LH2PSE</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>CAN0</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr><tr><td>CAN1</td><td>DisabledEnabled</td><td>Checked = Interrupt set to SB mode. Default unchecked is MSI mode.</td></tr></table>

7.3.2.8 Chipset > PCH-IO Configuration > TSN GBE Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PSE TSN GBE 0 Multi-Vc</td><td>EnabledDisabled</td><td>Enable/Disable TSN Multi Virtual Channels. TSN GBE must be host owned.</td></tr><tr><td>PSE TSN GBE 0 SGMII Support</td><td>EnabledDisabled</td><td>Enable/Disable Modphy support for SGMII mode for PSE TSN GBE 0. Ports in SGMII mode with the same PLL common lane must use the same link speed. UFS will need to be disabled as this TSN port uses the same PLLcommon lane. Please make sure IFWI has proper straps set for SGMII. Make sure Flex IO Lane Assignment is not NONE.</td></tr><tr><td>PSE TSN GBE 0 Link Speed</td><td>RefClk 24Mhz 2.5GbpsRefClk 24Mhz 1GbpsRefClk 38.4Mhz 2.5GbpsRefClk 38.4Mhz 1Gbps</td><td>PSE TSN GBE 0 Link Speed configuration.</td></tr><tr><td>Flex IO Lane Assignment:</td><td>Info Only</td><td></td></tr><tr><td>PSE TSN GBE1 Multi-Vc</td><td>EnabledDisabled</td><td>Enable/Disable TSN Multi Virtual Channels. TSN GBE must be host owned.</td></tr><tr><td>PSE TSN GBE1 SGMII Support</td><td>EnabledDisabled</td><td>Enable/Disable Modphy support for SGMII mode for PSE TSN GBE 1. Ports in SGMII mode with the same PLL common lane must use the same link Speed. SATA or UFS may need to be disabled if TSN port is using the same PLL common lane. Please make sure IFWI has proper straps set for SGMII. Make sure Flex IO Lane Assignment is not NONE.</td></tr><tr><td>PSE TSN GBE 1 Link Speed</td><td>RefClk 24Mhz 2.5GbpsRefClk 24Mhz 1GbpsRefClk 38.4Mhz 2.5GbpsRefClk 38.4Mhz 1Gbps</td><td>PSE TSN GBE 1 Link Speed configuration.</td></tr><tr><td>Flex IO Lane Assignment:</td><td>Info Only</td><td></td></tr><tr><td>PLL Common Lane 1</td><td>Info Only</td><td></td></tr></table>

# Security

7.4.1 Security > Password Description

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Password Description</td><td>Info only</td><td></td></tr><tr><td>Setup Administrator Password</td><td>Enter Password</td><td>Set Setup Administrator Password</td></tr><tr><td>User Password</td><td>Enter Password</td><td>Set User Password</td></tr><tr><td>Secure Boot</td><td>Submenu</td><td>Customizable Secure Boot settings.</td></tr><tr><td>System Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Info only</td><td></td></tr><tr><td>Secure Boot Control</td><td>DisabledEnabled</td><td>Secure Boot activated when Platform Key(PK) is enrolled, System mode is User / Deployed, and CSM function is disabled</td></tr></table>

# Boot

7.5.1 Boot > Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key.65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>OnOff</td><td>Select the keyboard Number state.</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Select the keyboard NumLock state.</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enable or Disable FastBoot features.Most probes are skipped to reduce time cost during boot.</td></tr><tr><td>New Boot Option Policy</td><td>DefaultPlace FirstPlace Last</td><td>Controls the placement of newly detected UEFI boot option.</td></tr><tr><td>Boot Mode select</td><td>LEGACYUEFI</td><td>Select boot mode LEGACY/UEFI</td></tr></table>

7.5.2 Boot > Fixed Boot Order Priorities

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Option #1</td><td>Hardware</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #2</td><td>CD/DVD</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #3</td><td>USB Hard Disk</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #4</td><td>USB CD/DVD</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #5</td><td>USB Key</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #6</td><td>USB Floppy</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #7</td><td>USB Lan</td><td>Set the system boot order.</td></tr><tr><td>Boot Option #8</td><td>Network</td><td>Set the system boot order.</td></tr></table>

Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Change and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td>Info only</td><td></td></tr></table>

# 8. BIOS Checkpoints, Beep Codes

A status code is a data value used to provide diagnostic information about the boot process. Progress codes are status codes that signify successful progression to a following initialization step. Error codes signify error conditions encountered in the process of system initialization. Aptio 5.x core can be configured to send status codes to a variety of sources. The two most commonly used types of status codes are checkpoint codes and beep codes. Checkpoint codes are byte length data values. Checkpoints are typically output to I/O port 80h, but Aptio 5.x core can be configured to send checkpoints to a variety of sources. Aptio 5.x core outputs checkpoints throughout the boot process to indicate the task the system is currently executing. Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process on production hardware. Beep code is a series of short sound signals. Beep codes are typically error codes that do not occur during normal boot process.

![The image displays a red outline icon of a document or note on a white background. The icon depicts a rectangular shape with a folded top-right corner. Inside the outline, there are two horizontal lines.](.smarc-lec-el-50m-72513-1050-15/6d91909db88ff69657c917140b404f63432aa1134463c2f1883a66b24126511d.jpg)

Note: Beep codes are not the only sounds generated during the boot process. Some firmware components may use sounds to notify user about other events such as detection of a hot-pluggable device. These sounds are typically generated using a frequency that is different from the frequency of the beep codes

Aptio 5.x core follows the firmware model described by the UEFI Platform Initialization Specification (PI). The PI Specification refers the following “boot phases”, which may apply to various checkpoint and beep code descriptions:

Security (SEC) – initial low-level initialization
Pre-EFI Initialization (PEI) – memory initialization
• Driver Execution Environment (DXE) – main hardware initialization
• Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network, Shell, ...)

# Viewing Checkpoints

Checkpoints generated by Aptio firmware can be viewed using a PCI checkpoint card, also referred to as a “POST Card” or “POST Diagnostic Card”. These PCI add-in cards show the value of I/O port 80h on a LED display. Checkpoint cards are available through a variety of computer mail-order outlets.

Newer systems feature support for AMI Debug Rx, a USB connected alternative to the PCI POST Card. AMI Debug Rx is a low-cost debug tool built around the debug port feature common to today’s USB 2.0 EHCI controllers. AMI Debug Rx is designed as replacement for the PCI POST Checkpoint Card as newer systems omit PCI expansion slots. Along with checkpoints, AMI Debug Rx has several features specifically designed for BIOS developers.

Status Code Ranges

<table><tr><td>Code Range</td><td>Description</td></tr><tr><td>0x01 – 0x0B</td><td>SEC execution</td></tr><tr><td>0x0C – 0x0F</td><td>SEC errors</td></tr><tr><td>0x10 – 0x2F</td><td>PEI execution up to and including memory detection</td></tr><tr><td>0x30 – 0x4F</td><td>PEI execution after memory detection</td></tr><tr><td>0x50 – 0x5F</td><td>PEI errors</td></tr><tr><td>0x60 – 0x8F</td><td>DXE execution up to BDS</td></tr><tr><td>0x90 – 0xFC</td><td>BDS execution</td></tr><tr><td>0xD0 – 0xDF</td><td>DXE errors</td></tr><tr><td>0xE0 – 0xE8</td><td>S3 Resume (PEI)</td></tr><tr><td>0xE9 – 0xEF</td><td>S3 Resume errors (PEI)</td></tr><tr><td>0xF0 – 0xF8</td><td>Recovery (PEI)</td></tr><tr><td>0xF9 – 0xFF</td><td>Recovery errors (PEI)</td></tr></table>

# Standard Status Codes

# 8.2.1 SEC Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x00</td><td>Not used</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x01</td><td>Power on. Reset type detection (soft/hard).</td></tr><tr><td>0x02</td><td>AP initialization before microcode loading</td></tr><tr><td>0x03</td><td>North Bridge initialization before microcode loading</td></tr><tr><td>0x04</td><td>South Bridge initialization before microcode loading</td></tr><tr><td>0x05</td><td>OEM initialization before microcode loading</td></tr><tr><td>0x06</td><td>Microcode loading</td></tr><tr><td>0x07</td><td>AP initialization after microcode loading</td></tr><tr><td>0x08</td><td>North Bridge initialization after microcode loading</td></tr><tr><td>0x09</td><td>South Bridge initialization after microcode loading</td></tr><tr><td>0x0A</td><td>OEM initialization after microcode loading</td></tr><tr><td>0x0B</td><td>Cache initialization</td></tr></table>

<table><tr><td colspan="2">SEC Error Codes</td></tr><tr><td>0x0C – 0x0D</td><td>Reserved for future AMI SEC error codes</td></tr><tr><td>0x0E</td><td>Microcode not found</td></tr><tr><td>0x0F</td><td>Microcode not loaded</td></tr></table>

# 8.2.2 SEC Phase > SEC Beep Codes

None.

8.2.3 SEC Phase > PEI Phase

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td colspan="2">Progress Codes</td></tr><tr><td>0x10</td><td>PEI Core is started</td></tr><tr><td>0x11</td><td>Pre-memory CPU initialization is started</td></tr><tr><td>0x12</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x13</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x14</td><td>Pre-memory CPU initialization (CPU module specific)</td></tr><tr><td>0x15</td><td>Pre-memory North Bridge initialization is started</td></tr><tr><td>0x16</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x17</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x18</td><td>Pre-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x19</td><td>Pre-memory South Bridge initialization is started</td></tr><tr><td>0x1A</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1B</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1C</td><td>Pre-memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x2B</td><td>Memory initialization. Serial Presence Detect (SPD) data reading</td></tr><tr><td>0x2C</td><td>Memory initialization. Memory presence detection</td></tr><tr><td>0x2D</td><td>Memory initialization. Programming memory timing information</td></tr><tr><td>0x2E</td><td>Memory initialization. Configuring memory</td></tr><tr><td>0x2F</td><td>Memory initialization (other).</td></tr><tr><td>0x30</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0x31</td><td>Memory Installed</td></tr><tr><td>0x32</td><td>CPU post-memory initialization is started</td></tr><tr><td>0x33</td><td>CPU post-memory initialization. Cache initialization</td></tr><tr><td>0x34</td><td>CPU post-memory initialization. Application Processor(s) (AP) initialization</td></tr><tr><td>0x35</td><td>CPU post-memory initialization. Boot Strap Processor (BSP) selection</td></tr><tr><td>0x36</td><td>CPU post-memory initialization. System Management Mode (SMM) initialization</td></tr><tr><td>0x37</td><td>Post-Memory North Bridge initialization is started</td></tr><tr><td>0x38</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x39</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3A</td><td>Post-Memory North Bridge initialization (North Bridge module specific)</td></tr><tr><td>0x3B</td><td>Post-Memory South Bridge initialization is started</td></tr><tr><td>0x3C</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3D</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3E</td><td>Post-Memory South Bridge initialization (South Bridge module specific)</td></tr><tr><td>0x3F-0x4E</td><td>OEM post memory initialization codes</td></tr><tr><td>0x4F</td><td>DXE IPL is started</td></tr><tr><td colspan="2">PEI Error Codes</td></tr><tr><td>0x50</td><td>Memory initialization error. Invalid memory type or incompatible memory speed</td></tr><tr><td>0x51</td><td>Memory initialization error. SPD reading has failed</td></tr><tr><td>0x52</td><td>Memory initialization error. Invalid memory size or memory modules do not match.</td></tr><tr><td>0x53</td><td>Memory initialization error. No usable memory detected</td></tr><tr><td>0x54</td><td>Unspecified memory initialization error.</td></tr><tr><td>0x55</td><td>Memory not installed</td></tr><tr><td>0x56</td><td>Invalid CPU type or Speed</td></tr><tr><td>0x57</td><td>CPU mismatch</td></tr><tr><td>0x58</td><td>CPU self test failed or possible CPU cache error</td></tr><tr><td>0x59</td><td>CPU micro-code is not found or micro-code update is failed</td></tr><tr><td>0x5A</td><td>Internal CPU error</td></tr><tr><td>0x5B</td><td>reset PPI is not available</td></tr><tr><td>0x5C-0x5F</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">S3 Resume Progress Codes</td></tr><tr><td>0xE0</td><td>S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)</td></tr><tr><td>0xE1</td><td>S3 Boot Script execution</td></tr><tr><td>0xE2</td><td>Video repost</td></tr><tr><td>0xE3</td><td>OS S3 wake vector call</td></tr><tr><td>0xE4-0xE7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">S3 Resume Error Codes</td></tr><tr><td>0xE8</td><td>S3 Resume Failed</td></tr><tr><td>0xE9</td><td>S3 Resume PPI not Found</td></tr><tr><td>0xEA</td><td>S3 Resume Boot Script Error</td></tr><tr><td>0xEB</td><td>S3 OS Wake Error</td></tr><tr><td>0xEC-0xEF</td><td>Reserved for future AMI error codes</td></tr><tr><td colspan="2">Recovery Progress Codes</td></tr><tr><td>0xF0</td><td>Recovery condition triggered by firmware (Auto recovery)</td></tr><tr><td>0xF1</td><td>Recovery condition triggered by user (Forced recovery)</td></tr><tr><td>0xF2</td><td>Recovery process started</td></tr><tr><td>0xF3</td><td>Recovery firmware image is found</td></tr><tr><td>0xF4</td><td>Recovery firmware image is loaded</td></tr><tr><td>0xF5-0xF7</td><td>Reserved for future AMI progress codes</td></tr><tr><td colspan="2">Recovery Error Codes</td></tr><tr><td>0xF8</td><td>Recovery PPI is not available</td></tr><tr><td>0xF9</td><td>Recovery capsule is not found</td></tr><tr><td>0xFA</td><td>Invalid recovery capsule</td></tr><tr><td>0xFB - 0xFF</td><td>Reserved for future AMI error codes</td></tr></table>

8.2.4 SEC Phase > PEI Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Memory not Installed</td></tr><tr><td>1</td><td>Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)</td></tr><tr><td>2</td><td>Recovery started</td></tr><tr><td>3</td><td>DXEIPL was not found</td></tr><tr><td>3</td><td>DXE Core Firmware Volume was not found</td></tr><tr><td>4</td><td>Recovery failed</td></tr><tr><td>4</td><td>S3 Resume failed</td></tr><tr><td>7</td><td>Reset PPI is not available</td></tr></table>

8.2.5 SEC Phase > DXE Status Codes

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x60</td><td>DXE Core is started</td></tr><tr><td>0x61</td><td>NVRAM initialization</td></tr><tr><td>0x62</td><td>Installation of the South Bridge Runtime Services</td></tr><tr><td>0x63</td><td>CPU DXE initialization is started</td></tr><tr><td>0x64</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x65</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x66</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x67</td><td>CPU DXE initialization (CPU module specific)</td></tr><tr><td>0x68</td><td>PCI host bridge initialization</td></tr><tr><td>0x69</td><td>North Bridge DXE initialization is started</td></tr><tr><td>0x6A</td><td>North Bridge DXE SMM initialization is started</td></tr><tr><td>0x6B</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6C</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6D</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6E</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x6F</td><td>North Bridge DXE initialization (North Bridge module specific)</td></tr><tr><td>0x70</td><td>South Bridge DXE initialization is started</td></tr><tr><td>0x71</td><td>South Bridge DXE SMM initialization is started</td></tr><tr><td>0x72</td><td>South Bridge devices initialization</td></tr><tr><td>0x73</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x74</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x75</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x76</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x77</td><td>South Bridge DXE Initialization (South Bridge module specific)</td></tr><tr><td>0x78</td><td>ACPI module initialization</td></tr><tr><td>0x79</td><td>CSM initialization</td></tr><tr><td>0x7A – 0x7F</td><td>Reserved for future AMI DXE codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0x90</td><td>Boot Device Selection (BDS) phase is started</td></tr><tr><td>0x91</td><td>Driver connecting is started</td></tr><tr><td>0x92</td><td>PCI Bus initialization is started</td></tr><tr><td>0x93</td><td>PCI Bus Hot Plug Controller Initialization</td></tr><tr><td>0x94</td><td>PCI Bus Enumeration</td></tr><tr><td>0x95</td><td>PCI Bus Request Resources</td></tr><tr><td>0x96</td><td>PCI Bus Assign Resources</td></tr><tr><td>0x97</td><td>Console Output devices connect</td></tr><tr><td>0x98</td><td>Console input devices connect</td></tr><tr><td>0x99</td><td>Super IO Initialization</td></tr><tr><td>0x9A</td><td>USB initialization is started</td></tr><tr><td>0x9B</td><td>USB Reset</td></tr><tr><td>0x9C</td><td>USB Detect</td></tr><tr><td>0x9D</td><td>USB Enable</td></tr><tr><td>0x9E – 0x9F</td><td>Reserved for future AMI codes</td></tr><tr><td>0xA0</td><td>IDE initialization is started</td></tr><tr><td>0xA1</td><td>IDE Reset</td></tr><tr><td>0xA2</td><td>IDE Detect</td></tr><tr><td>0xA3</td><td>IDE Enable</td></tr><tr><td>0xA4</td><td>SCSI initialization is started</td></tr><tr><td>0xA5</td><td>SCSI Reset</td></tr><tr><td>0xA6</td><td>SCSI Detect</td></tr><tr><td>0xA7</td><td>SCSI Enable</td></tr><tr><td>0xA8</td><td>Setup Verifying Password</td></tr><tr><td>0xA9</td><td>Start of Setup</td></tr><tr><td>0xAA</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAB</td><td>Setup Input Wait</td></tr><tr><td>0xAC</td><td>Reserved for ASL (see ASL Status Codes section below)</td></tr><tr><td>0xAD</td><td>Ready To Boot event</td></tr><tr><td>0xAE</td><td>Legacy Boot event</td></tr><tr><td>0xAF</td><td>Exit Boot Services event</td></tr><tr><td>0xB0</td><td>Runtime Set Virtual Address MAP Begin</td></tr><tr><td>0xB1</td><td>Runtime Set Virtual Address MAP End</td></tr><tr><td>0xB2</td><td>Legacy Option ROM Initialization</td></tr><tr><td>0xB3</td><td>System Reset</td></tr><tr><td>0xB4</td><td>USB hot plug</td></tr><tr><td>0xB5</td><td>PCI bus hot plug</td></tr><tr><td>0xB6</td><td>Clean-up of NVRAM</td></tr><tr><td>0xB7</td><td>Configuration Reset (reset of NVRAM settings)</td></tr><tr><td>0xB8 – 0xBF</td><td>Reserved for future AMI codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr><tr><td colspan="2">DXE Error Codes</td></tr><tr><td>0xD0</td><td>CPU initialization error</td></tr><tr><td>0xD1</td><td>North Bridge initialization error</td></tr><tr><td>0xD2</td><td>South Bridge initialization error</td></tr><tr><td>0xD3</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>0xD4</td><td>PCI resource allocation error. Out of Resources</td></tr><tr><td>0xD5</td><td>No Space for Legacy Option ROM</td></tr><tr><td>0xD6</td><td>No Console Output Devices are found</td></tr><tr><td>0xD7</td><td>No Console Input Devices are found</td></tr><tr><td>0xD8</td><td>Invalid password</td></tr><tr><td>0xD9</td><td>Error loading Boot Option (LoadImage returned error)</td></tr><tr><td>0xDA</td><td>Boot Option is failed (StartImage returned error)</td></tr><tr><td>0xDB</td><td>Flash update is failed</td></tr><tr><td>0xDC</td><td>Reset protocol is not available</td></tr></table>

# 8.2.6 SEC Phase > DXE Beep Codes

<table><tr><td># of Beeps</td><td>Description</td></tr><tr><td>1</td><td>Invalid password</td></tr><tr><td>4</td><td>Some of the Architectural Protocols are not available</td></tr><tr><td>5</td><td>No Console Output Devices are found</td></tr><tr><td>5</td><td>No Console Input Devices are found</td></tr><tr><td>6</td><td>Flash update is failed</td></tr><tr><td>7</td><td>Reset protocol is not available</td></tr><tr><td>8</td><td>Platform PCI resource requirements cannot be met</td></tr></table>

8.2.7 SEC Phase > ACPI/ASL Checkpoint

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x01</td><td>System is entering S1 sleep state</td></tr><tr><td>0x02</td><td>System is entering S2 sleep state</td></tr><tr><td>0x03</td><td>System is entering S3 sleep state</td></tr><tr><td>0x04</td><td>System is entering S4 sleep state</td></tr><tr><td>0x05</td><td>System is entering S5 sleep state</td></tr><tr><td>0x10</td><td>System is waking up from the S1 sleep state</td></tr><tr><td>0x20</td><td>System is waking up from the S2 sleep state</td></tr><tr><td>0x30</td><td>System is waking up from the S3 sleep state</td></tr><tr><td>0x40</td><td>System is waking up from the S4 sleep state</td></tr><tr><td>0xAC</td><td>System has transitioned into ACPI mode. Interrupt controller is in PIC mode.</td></tr><tr><td>0xAA</td><td>System has transitioned into ACPI mode. Interrupt controller is in APIC mode.</td></tr></table>

# OEM-reserved Checkpoint Ranges

<table><tr><td>Status Code</td><td>Description</td></tr><tr><td>0x05</td><td>OEM SEC initialization before microcode loading</td></tr><tr><td>0x0A</td><td>OEM SEC initialization after microcode loading</td></tr><tr><td>0x1D – 0x2A</td><td>OEM pre-memory initialization codes</td></tr><tr><td>0x3F – 0x4E</td><td>OEM PEI post memory initialization codes</td></tr><tr><td>0x80 – 0x8F</td><td>OEM DXE initialization codes</td></tr><tr><td>0xC0 – 0xCF</td><td>OEM BDS initialization codes</td></tr></table>

# 9. Software Support

# 9.1.1 Yocto

Yocto is available on ADlink Github > https://github.com/ADLINK/meta-adlink-x86-64bit

# 9.1.2 Ubuntu

Ubuntu is supported from kernel 5.15 and up

# 9.1.3 Windows

Windows 10 is supported

# 10. Mechanical

PCB dimension: 82 x 50 x 1.2 mm, 12 layer PCB
![This image is a technical schematic displaying the layout and dimensions for a rectangular module.\n\n**Top Section (Main Views):**\n*   **Left View:** Labeled 'Module Primary (Top) Side'. It shows a rectangular outline with mounting holes at the corners annotated as '4X Ø6' and '4X Ø2.70 THROUGH'. Pin connectors run along the bottom edge, divided into '74 PINS P1 - P74' and '82 PINS P75 - P156'. Dimensions along the left edge include '0', '4', '50', '46', and a series near the connector '12', '7.70', '6.20', '3.30', '3.10', '0', and '1.25 PINP1'. The bottom width is marked '39'. Corner dimensions '78' and '82' appear at the top right.\n*   **Right View:** Labeled 'Module Primary (Bottom) Side'. It shows the reverse side with a connector along the top edge. Annotations include '1.00 PIN S1', '75 PINS S1 - S75', and '83 PINS S76 - S158'.\n\n**Middle Section (Detail Views):**\n*   **Left Detail:** Labeled 'DETAILA TOP SIDE'. It shows a close-up of pins 'P74' and 'P75'. Dimensions include '73X0.50', '81X0.50', '156X0.35', 'FULLRAD', '(3.30)', '3.10 TYP', '1.00', and '1.25'.\n*   **Center Detail:** Labeled 'DETAILD NOTCH, 2 PLACES'. It depicts a corner notch with pin '1S'. Dimensions are '1.70', '2X R0.50', '(6.20)', and '(1.50)'.\n*   **Center Right Detail:** Labeled 'PIN ALIGNMENT DETAIL'. It is a circular view showing 'TOP SIDE' with pins 'P74' and 'P75' and 'BOTTOM SIDE' with pins 'S75' and 'S76'. A gap dimension is marked '0.25'.\n*   **Far Right Detail:** Labeled 'DETAILB BOTTOM SIDE'. It shows pins 'S75' and 'S76'. Dimensions include '1', '1', '74X0.50', '82X0.50', '158X0.35', and '3.10 TYP'.\n\n**Bottom Section:**\n*   **Bottom Left:** Labeled 'CHAMFEREDGE DETAIL'. It shows a chamfer angle with dimensions '0.18', '1.20±0.1', and '45°'.\n*   **Bottom Right:** A side profile view indicating '3.00 MAX COMPONENT HEIGHT (TOP SIDE)' and '1.30 MAX COMPONENT HEIGHT (BOTTOM SIDE)'.](.smarc-lec-el-50m-72513-1050-15/2a370bdbc78ac06a56c765eaea4412f35ec39f95c66f29ff83af4ac7c66fdead.jpg)
Figure 4: Mechanical dimensions

# 11. Thermal Solutions

For optimal performance, LEC-EL has to be cooled by a passive heatsink / heat-spreader optionally available for ordering

![This is a technical engineering drawing of a rectangular component featuring vertical fins.\n\n**Top Section:**\n*   **Left:** A side profile view.\n*   **Center:** A front view displaying vertical fins, corner mounting holes with crosshairs, and a rectangular notch cut out of the bottom edge.\n*   **Right:** A side profile view with a circled number **②** pointing to a small feature.\n\n**Bottom Section:**\n*   **Bottom View:** Shows the reverse side of the plate with mounting holes and recessed areas.\n*   **Dimensions (in red):**\n    *   Top dimension: **① 82±0.3**\n    *   Left dimension: **② 42±0.2**\n*   **Internal Text/Labels:**\n    *   Vertical text reading **NC1198**.\n    *   A central square recess labeled with a circled **③**.](.smarc-lec-el-50m-72513-1050-15/94e83b213ce53ed06e33665e895d8df1216f6452c03dbb128843c11b0e72d2a8.jpg)

<table><tr><td>HTS-sEL</td><td>Heatspreader for LEC-EL</td></tr><tr><td>THS-sEL</td><td>Low profile heatsink for LEC-EL</td></tr></table>

Figure 5: Thermal solutions