# LEC-IMX6R2 User's Guide NXP 02/12/2021 ![Close-up of a blue printed circuit board with various electronic components and gold contacts (no readable text or symbols)](.smarc-lec-imx6r2-user-s-guide-final/bcfb23b38e4be37c4bef58ea3faa4f9c2cd95b5d69c51b38906beca1d45ebf57.jpg) # Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # © Copyright 2017 ADLINK Technology, Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: Keep equipment away from water or liquid sources; Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![The image displays a red icon resembling a document or memo with a folded bottom-right corner. Inside the white space of the document, there are three horizontal red lines representing text.](.smarc-lec-imx6r2-user-s-guide-final/c387a2e16db04eea32070a876e5c00016e5ccab00e00fba23e658aa8a391e297.jpg) Note: This information adds clarity or specifics to text and illustrations. ![The image displays a standard yellow triangular warning sign containing a white exclamation point in the center, set against a light grey background.](.smarc-lec-imx6r2-user-s-guide-final/163d8786d828fa0a95eed5e37fb16f2625de21c074f117fe44590a3d47596dda.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image displays a red triangular warning sign with rounded corners. Centered inside the red triangle is a white exclamation mark.](.smarc-lec-imx6r2-user-s-guide-final/aa837f2ac3c5d2ce7d40f6e616db387b10b9f2ab746a0730a3e5ba356be893c9.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Revision History
RevisionDescriptionDate dd/mm/yyyyAuthor
1.0Initial public release10/03/2021Henri Parmentier
# Table of Contents # Introduction .. . 8 1.1 The SMARC Formfactor . ..8 # 2. Specifications... C 2.1 Core System... ..9 2.2 Video.... ... 10 2.3 Audio ... . 12 2.4 Dual Ethernet... ... 12 2.5 Extension busses.. ... 13 2.6 System Storage . .. 14 2.7 SEMA® Board Management Controller .. ... 15 2.8 Debug Header ... ... 15 2.9 Boot Modes .. ... 15 2.10 Power.... ... 16 2.11 Mechanical and Environmental . ... 16 # 3. Block Diagram .. .17 # 4. Pinout and Signal Descriptions ... .18 4.1 Pin Summary .. ... 18 4.2 Signal Terminology Descriptions.. ... 22 4.3 Signal Description by function.. .. 23 4.3.1 The First Display Interface .. . 23 4.3.2 Second & Third Display Interface . . 26 4.3.3 MIPI Camera support .. . 28 4.3.4 I2S (audio) ... ... 30 4.3.5 USB ports... . 31 4.3.6 PCIe Ports .. . 34 4.3.7 SATA Ports .. ... 36 4.3.8 LAN ports .. . 37 4.3.9 SDIO.... ... 39 4.3.10 SPI & ESPI.. ... 40 4.3.11 SPI0 .... .... 40 4.3.12 ESPI ... . 41 4.4 General Purpose I2C.. ... 42 4.4.1 GPIO.... .... 43 4.4.2 UART.. . 44 4.4.3 CAN bus... . 45 4.4.4 Miscellaneous ..... .. 45 4.4.5 Power and System Management . . 46 4.4.6 DB30 Multipurpose Connector . . 47 4.4.7 Boot Select... ... 48 4.4.8 Power . . 49 4.5 SMARC pin to controller mapping.... ... 50 5. Software Support .......... ... 61 5.1.1 Uboot / Yocto... . 61 5.1.2 Ubuntu... ... 61 5.1.3 Android ... . 61 6. Mechanical... ..62 7. Thermal Solutions... .63 # List of Figures Figure 1 – Module function diagram... Figure 2 – Module top/botom side pin numbering .. .18 # Introduction # 1.1 The SMARC Formfactor The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer on Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented X86 devices and other RISC CPUs may be used as well. The Module power envelope is typically under 6W. Two Module sizes are defined: 82 mm x 50 mm and 82 mm x 80 mm. The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321 pin connector, but 7 pins are lost to the key). The Modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the Module. The Modules are used with application specific Carrier Boards that implement other features such as audio CODECs, touch controllers, wireless devices, etc. The modular approach allows scalability, fast time to market and upgradability while still maintaining low costs, low power and small physical size. ![The image displays the letters 'SG' in yellow. To the right, there is a yellow 'T' (top part visible). Below/overlapping the 'T' is a pink lowercase 'e'.](.smarc-lec-imx6r2-user-s-guide-final/9a456634fb280ae02054107a74cdf611b1f16639c0d1e4a512a8edb46d5b1354.jpg) STANDARDIZATION GROUP FOR EMBEDDED TECHNOLOGIES SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html # 2. Specifications # 2.1 Core System # SoC NXP i.MX 6 Series • i.MX6 Solo / Duallite: Single/Dual core ARM® Cortex™-A9 SOC • i.MX6 Dual / Quad: Dual/Quad core ARM® Cortex™-A9 SOC • i.MX6 DualPlus / QuadPlus: Dual/Quad core ARM® Cortex™-A9 SOC available either as industrial (-40°C to +85°C) or commercial (0°C to +70°C) type" # L2 Cache • 32 KB I-cache 32 KB D-cache # Memory • 512MB/ 1/2/4GB DDR3L memory down # IoT security CryptoAuthentication™ Device, Microchip ATECC608A • Cryptographic co-processor with secure hardware-based key storage • Protected storage for up to 16 Keys, certificates or data ECDH: FIPS SP800-56A Elliptic Curve Diffie-Hellman • NIST standard P256 elliptic curve support • SHA-256 & HMAC hash including off-chip context save/restore • AES-128: encrypt/decrypt, galois field multiply for GCM # 2.2 Video LEC-iMX6R2 standard display support is consisting of full HD capable HDMI 1.4, MIPI DSI and single/dual channel 24-bit LVDS. # GPU Core: Vivante GC880 / GX2000 / GC2000+ GPU cores are varying between SKU’s check datasheet for more info # GPU/VPU Feature Support Video, 2D and 3D Graphics Units integrated in i.MX6 Processor OpenGL® ES 1.1/2.0/Halti, OpenVG™ 1.1, OpenCL™ 1.1 EP • Multi-Format Hardware Video Encoder/Decoder # HDMI • HDMI V1.4 up to WUXGA (1920x1080) • FHD 1080p @ 30fps # LVDS • Dual-channel 18/24-bit max 1920 x 1080 x 30fps Single-channel 18/24-bit max 1366 x 768 x 30fps # MIPI DSI • 1080p @ 60fps display output Compatible with MIPI specification v1.0 • 2 data lanes, 1.0 Gbps max data rate per lane support HS and LP mode # Camera support Single MIPI CSI camera supported on CSI1 ▪ Four lanes : QuadPlus, Quad, DualPlus, Dual ▪ Two lanes : DualLite and Solo # 2.3 Audio • Supports i2S audio codec interface, audio ADC and DAC (located on carrier) # 2.4 Dual Ethernet # Primary LAN MAC 10/100/1000 Ethernet Controller in SOC • PHY on module through RGMII • Operates on TCP/IP, UDP/IP, and ICMP/IP protocol data or on IP header only NOTE: The Ethernet throughput is limited to 400 Mbit/s by the Freescale SoC. # Optional Secondary LAN MAC/PHY 10/100 Ethernet Controller in LAN9514 on USB 2.0 Supports 10/100-Mbps data transfer rates, both full-duplex and half-duplex Supports IEEE 802.1Q VLAN tag detection for reception frames Support detection of LAN wake-up frames and AMD Magic Packet frames # 2.5 Extension busses # PCIe One PCI Express GEN2 x1 interfaces Only available on QuadPlus, Quad, DualPlus, Dual # SATA Single port SATA 2 support Only available on QuadPlus, Quad, DualPlus, Dual # USB 4x USB 2.0 and 1x USB2.0 OTG # UART Four UART interface SER0 and SER2 (TX/X/CTS/RTS) • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) • Programmable baud rates up to 5 MHz • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) • Option to operate as 8- pins full UART, DCE, or DTE # CAN bus 2x CAN2.0B only or mixed CAN2.0B and CAN FB mode, data bit rate up to 8 Mbps via SPI to CAN controller # SPI 2 x SPI # I2S 2x I2S interfaces with audio resolution from 16-bits to 32-bits and sample rate up to 192KHz (see Audio Codec support) # I2C # Three I2C interfaces • Support 7bits and 10bits address mode • Data transfer rates of 100 kbit/s, 400 kbit/s and 1 Mbit/s General Purpose I2C\_GP for usage on carrier ▪ Power Management I2C\_PM , connected to PMIC ▪ LCD I2C to detect and manage connected displays Camera I2C # GPIO 12x GPIO with interrupt # 2.6 System Storage # SDIO 1x SDIO (4-bit) compatible up to version 3.0. # eMMC soldered on module 16, 32 or 64 GB (build option) either standard or -40+85C temp range Compatible with eMMC specification 4.41, 4.51 and 5.0 # 2.7 SEMA® Board Management Controller Voltage/current monitoring, boot configuration, logistics and forensic information, flat panel control, watchdog timer # 2.8 Debug Header 30-pin multipurpose flat cable connector for use with optional DB-30 debug module Provides JTAG, BMC access; UART, power test points; diagnostic LEDs, Power, Reset, Boot configuration # 2.9 Boot Modes eMMC and SD-Card boot modes are supported # 2.10 Power # Supply Voltage 4.75 V – 5.25 V # 2.11 Mechanical and Environmental # Form Factor SGET SMARC Specifications v2.1 # Dimension SMARC small size module, 82mm x 50mm # Operating Temperature Standard: 0°C to +60°C Rugged: -40°C to +85°C (optional) # Humidity 5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # 3. Block Diagram ![**Central Block:**\n* **NXP iMX6 SMARC REV 2.1** (Large red block)\n\n**Left Column (Grey Block Interfaces):**\n* LVDS0 / DSI0\n* LVDS1\n* HDMI\n* CSI0\n* USB0\n* USB1\n* USB2\n* USB3\n* USB4\n* LAN1\n* LAN0\n* PCIe0\n* CAN0\n* CAN1\n* SPI0\n* SPI1\n* UART0\n* UART1\n* UART2\n* UART3\n* I2S0\n* SDIO\n* GPIO\n* I2C_GP\n* I2C_PM\n* Watchdog / Boot Select, Power Control\n\n**Right Side Blocks:**\n* **DDR3L x16** (Four distinct blocks)\n* **eMCC 16/32/64GB**\n* **30-pin debug**\n\n**Bottom Blocks:**\n* **Lite BMC**\n* **RTC**\n\n**Intermediary Blocks:**\n* **USB HUB 4x USB 2.0 1x GbE**\n* **LAN PHY**\n* **Crypto Auth. ATECC608A**\n* **PMIC**\n\n**Connections:**\n* **LVDS0 / DSI0** and **LVDS1** connect to **Dual Channel LVDS** and **DSI 2 lanes**.\n* **HDMI** connects to **HDMI V1.4**.\n* **CSI0** connects to **MIPI CSI 2-lanes**.\n* **USB0** connects to **USB 2.0 OTG**.\n* **USB1** connects to **USB 2.0 Host**.\n* **USB2**, **USB3**, **USB4**, and **LAN1** connect to the **USB HUB 4x USB 2.0 1x GbE**.\n* **LAN0** connects to **LAN PHY**, which connects to **RGMII**.\n* **PCIe0** connects to **1x PCIe x1**.\n* **CAN0** and **CAN1** connect to **CAN**.\n* **SPI0** connects to **SPI0**.\n* **SPI1** connects to **SPI1**.\n* **UART0** connects to **UART0**.\n* **UART1** connects to **UART1**.\n* **UART2** connects to **UART2**.\n* **UART3** connects to **UART3**.\n* **I2S0** connects to **I2S**.\n* **SDIO** connects to **SDMMC**.\n* **GPIO** connects to **GPIO x10**.\n* **I2C_GP** connects to **Crypto Auth. ATECC608A**.\n* **I2C_PM** connects to **PMIC**.\n* **Watchdog / Boot Select, Power Control** connects to **Lite BMC**, which connects to the **NXP iMX6** block.\n* **RTC** connects to the **NXP iMX6** block.\n* The **NXP iMX6** block connects to the four **DDR3L x16** blocks.\n* The **NXP iMX6** block connects to **eMCC 16/32/64GB**.\n* The **NXP iMX6** block connects to **30-pin debug**.](.smarc-lec-imx6r2-user-s-guide-final/da19723a4a41c6863bf6cf3275281da2d1cf01d3e8d490a9383d538a13bd6d05.jpg) Figure 1 – Module function diagram # 4. Pinout and Signal Descriptions # 4.1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1. Those signals not supported on LEC-iMX6R2 are strikethrough STRIKETHROUGH ![TOP Side\nP1 P74 P75 P156\nKey](.smarc-lec-imx6r2-user-s-guide-final/1d2b8ceba85caf2ca8a133e0152834f34e2249aeaff1f86700b48211e8b1d920.jpg) ![BOTTOM Side\nS156 S76 S75 S1\nKey](.smarc-lec-imx6r2-user-s-guide-final/f2fc4d67cbdbf588605b558e6b321da5e56fba43a565f0a785146b233f1119c7.jpg) Figure 2 – Module top/botom side pin numbering
P-PinPrimary (Top) Side
P1SMB_ALERT_1V8#
P2GND
P3CSI1_CK+
P4CSI1_CK-
P5GBE1_SDP
P6GBE0_SDP
P7CSI1_RX0+
P8CSI1_RX0-
P9GND
P10CSI1_RX1+
P11CSI1_RX1-
P12GND
P13CSI1_RX2+
P14CSI1_RX2-
P15GND
P16CSI1_RX3+
P17CSI1_RX3-
P18GND
P19GBE0_MDI3-
P20GBE0_MDI3+
P21GBE0_LINK100#
P22GBE0_LINK1000#
P23GBE0_MDI2-
P24GBE0_MDI2+
P25GBE0_LINK_ACT#
P26GBE0_MDI1-
P27GBE0_MDI1+
P28GBE0_CTREF
P29GBE0_MDIO-
P30GBE0_MDIO+
P31SPI0_CS1# note 2
P32GND
P33SDIO_WP
P34SDIO_CMD
P35SDIO_CD#
S-PinSecondary (Bottom) Side
S1CSI1_TX+ / I2C_CAM1_CK
S2CSI1_TX- / I2C_CAM1_DAT
S3GND
S4RSVD
S5CSI0_TX- / I2C_CAM0_CK
S6CAM_MCK
S7CSI0_TX+ / I2C_CAM0_DAT
S8CSI0_CK+
S9CSI0_CK-
S10GND
S11CSI0_RX0+
S12CSI0_RX0-
S13GND
S14CSI0_RX1+
S15CSI0_RX1-
S16GND
S17GBE1_MDI0+
S18GBE1_MDI0-
S19GBE1_LINK100#
S20GBE1_MDI1+
S21GBE1_MDI1-
S22GBE1_LINK1000#
S23GBE1_MDI2+
S24GBE1_MDI2-
S25GND
S26GBE1_MDI3+
S27GBE1_MDI3-
S28GBE1_CTREF
S29PCIE_D_TX+ / SERDES_1_TX+
S30PCIE_D_TX- / SERDES_1_TX-
S31GBE1_LINK_ACT#
S32PCIE_D_RX+ / SERDES_1_RX+
S33PCIE_D_RX- / SERDES_1_RX-
S34GND
S35USB4+
S36USB4-
P-PinPrimary (Top) Side
P36SDIO_CK
P37SDIO_PWR_EN
P38GND
P39SDIO_D0
P40SDIO_D1
P41SDIO_D2
P42SDIO_D3
P43SPI0_CS0# note 2
P44SPI0_CK note 2
P45SPI0_DIN note 2
P46SPI0_DO note 2
P47GND
P48SATA_TX+
P49SATA_TX-
P50GND
P51SATA_RX+
P52SATA_RX-
P53GND
P54ESPI_CS0# / SPI1_CS0#
P55ESPI_CS1# / SPI1_CS1#
P56ESPI_CK / SPI1_CK
P57ESPI_IO_1 / SPI1_DIN
P58ESPI_IO_0 / SPI1_DO
P59GND
P60USB0+
P61USB0-
P62USB0_EN_OC#
P63USB0_VBUS_DET
P64USB0_OTG_ID
P65USB1+
P66USB1-
P67USB1_EN_OC#
P68GND
P69USB2+
P70USB2-
P71USB2_EN_OC#
S-PinSecondary (Bottom) Side
S37USB3_VBUS_DET
S38AUDIO_MCK
S39I2S0_LRCK
S40I2S0_SDOUT
S41I2S0_SDIN
S42I2S0_CK
S43ESPI_ALERT0#
S44ESPI_ALERT1#
S45MDIO_CLK
S46MDIO_DAT
S47GND
S48I2C_GP_CK
S49I2C_GP_DAT
S50HDA_SYNC / I2S2_LRCK
S51HDA_SDO / I2S2_SDOUT
S52HDA_SDI / I2S2_SDIN
S53HDA_CK / I2S2_CK
S54SATA_ACT#
S55USB5_EN_OC#
S56ESPI_IO_2
S57ESPI_IO_3
S58ESPI_RESET#
S59USB5+
S60USB5-
S61GND
S62USB3_SSTX+
S63USB3_SSTX-
S64GND
S65USB3_SSRX+
S66USB3_SSRX-
S67GND
S68USB3+
S69USB3-
S70GND
S71USB2_SSTX+
S72USB2_SSTX-
P-PinPrimary (Top) Side
P72RSVD
P73RSVD
P74USB3_EN_OC#
Key
P75PCIE_A_RST#
P76USB4_EN_OC#
P77PCIE_B_CKREQ#
P78PCIE_A_CKREQ#
P79GND
P80PCIE_C_REFCK+
P81PCIE_C_REFCK-
P82GND
P83PCIE_A_REFCK+
P84PCIE_A_REFCK-
P85GND
P86PCIE_A_RX+
P87PCIE_A_RX-
P88GND
P89PCIE_A_TX+
P90PCIE_A_TX-
P91GND
P92HDMI_D2+ / DP1_LANE0+
P93HDMI_D2- / DP1_LANE0-
P94GND
P95HDMI_D1+ / DP1_LANE1+
P96HDMI_D1- / DP1_LANE1-
P97GND
P98HDMI_D0+ / DP1_LANE2+
P99HDMI_D0- / DP1_LANE2-
P100GND
P101HDMI_CK+ / DP1_LANE3+
P102HDMI_CK- / DP1_LANE3-
P103GND
S-PinSecondary (Bottom) Side
S73GND
S74USB2_SSRX+
S75USB2_SSRX-
Key
S76PCIE_B_RST#
S77PCIE_C_RST#
S78PCIE_C_RX+/SERDES_2_RX+
S79PCIE_C_RX-/SERDES_2_RX-
S80GND
S81PCIE_C_TX+/SERDES_2_TX+
S82PCIE_C_TX-/SERDES_2_TX-
S83GND
S84PCIE_B_REFCK+
S85PCIE_B_REFCK-
S86GND
S87PCIE_B_RX+
S88PCIE_B_RX-
S89GND
S90PCIE_B_TX+
S91PCIE_B_TX-
S92GND
S93DPO_LANE0+
S94DPO_LANE0-
S95DPO_AUX_SEL
S96DPO_LANE1+
S97DPO_LANE1-
S98DPO_HPD
S99DPO_LANE2+
S100DPO_LANE2-
S101GND
S102DPO_LANE3+
S103DPO_LANE3-
S104USB3_OTG_ID
P-PinPrimary (Top) Side
P104HDMI_HPD / DP1_HPD
P105HDMI_CTRL_CK / DP1_AUX+
P106HDMI_CTRL_DAT / DP1_AUX-
P107DP1_AUX_SEL
P108GPIO0 / CAM0_PWR#
P109GPIO1 / CAM1_PWR#
P110GPIO2 / CAM0_RST#
P111GPIO3 / CAM1_RST#
P112GPIO4 / HDA_RST#
P113GPIO5 / PWM_OUT
P114GPIO6 / TACHIN
P115GPIO7
P116GPIO8
P117GPIO9
P118GPIO10
P119GPIO11
P120GND
P121I2C_PM_CK
P122I2C_PM_DAT
P123BOOT_SEL0#
P124BOOT_SEL1#
P125BOOT_SEL2#
P126RESET_OUT#
P127RESET_IN#
P128POWER_BTN#
P129SERO_TX
P130SERO_RX
P131SERO_RTS#
P132SERO_CTS#
P133GND
P134SER1_TX
P135SER1_RX
P136SER2_TX
P137SER2_RX
P138SER2_RTS#
S-PinSecondary (Bottom) Side
S105DP0_AUX+
S106DP0_AUX-
S107LCD1_BKLT_EN
S108LVDS1_CK+/eDP1_AUX+/DSI1_CLK+
S109LVDS1_CK-/ eDP1_AUX-/DSI1_CLK-
S110GND
S111LVDS1_0+/ eDP1_TX0+/DSI1_D0+
S112LVDS1_0-/ eDP1_TX0-/DSI1_D0-
S113eDP1_HPD/DSI1_TE
S114LVDS1_1+/ eDP1_TX1+/DSI1_D1+
S115LVDS1_1-/ eDP1_TX1-/DSI1_D1-
S116LCD1_VDD_EN
S117LVDS1_2+/ eDP1_TX2+/DSI1_D2+
S118LVDS1_2-/ eDP1_TX2-/DSI1_D2-
S119GND
S120LVDS1_3+/ eDP1_TX3+/DSI1_D3+
S121LVDS1_3-/ eDP1_TX3-/DSI1_D3-
S122LCD1_BKLT_PWM
S123GPIO13
S124GND
S125LVDS0_0+/ eDP0_TX0+/DSI0_D0+
S126LVDS0_0-/ eDP0_TX0-/DSI0_D0-
S127LCD0_BKLT_EN
S128LVDS0_1+/ eDP0_TX1+/DSI0_D1+
S129LVDS0_1-/ eDP0_TX1-/DSI0_D1-
S130GND
S131LVDS0_2+/eDP0_TX2+/DSI0_D2+
S132LVDS0_2-/eDP0_TX2-/DSI0_D2-
S133LCD0_VDD_EN
S134LVDS0_CK+/eDP0_AUX/DSI0_CLK+
S135LVDS0_CK-/eDP0_AUX-/DSI0_CLK-
S136GND
S137LVDS0_3+/ eDP0_TX3+/DSI0_D3+
S138LVDS0_3-/ eDP0_TX3-/DSI0_D3-
S139I2C_LCD_CK
P-PinPrimary (Top) Side
P139SER2_CTS#
P140SER3_TX
P141SER3_RX
P142GND
P143CAN0_TX
P144CAN0_RX
P145CAN1_TX
P146CAN1_RX
P147VDD_IN
P148VDD_IN
S-PinSecondary (Bottom) Side
S140I2C_LCD_DAT
S141LCD0_BKLT_PWM
S142GPIO12
S143GND
S144eDP0_HPD / DSIO_TE
S145WDT_TIME_OUT#
S146PCIE_WAKE#
S147VDD_RTC
S148LID#
S149SLEEP#
P-PinPrimary (Top) Side
P149VDD_IN
P150VDD_IN
P151VDD_IN
P152VDD_IN
P153VDD_IN
P154VDD_IN
P155VDD_IN
P156VDD_IN
S-PinSecondary (Bottom) Side
S150VIN_PWR_BAD#
S151CHARGING#
S152CHARGER_PRSNT#
S153CARRIER_STBY#
S154CARRIER_PWR_ON
S155FORCE_RECOV#
S156BATLOW#
S157TEST#
S158GND
![The image displays a red icon resembling a document or a note. It features a square shape with rounded corners and a folded bottom-right corner. Inside the border, there are two horizontal red lines centered horizontally, representing lines of text or a list.](.smarc-lec-imx6r2-user-s-guide-final/5087ba3d53ad032c68701daf5d7b398299381c855894fe70b6f5f73fa187bf6e.jpg) Note 1: Secondary LAN connected to the USB hub # 4.2 Signal Terminology Descriptions Meaning of the terms used for signal description tables
TermDescription
IInput to the module
OOutput from the module
O ODOpen drain output from the module
I ODOpen drain input to the module, with mandatory PU (pull up) on module
ODOpen drain
I/OBi-directional Input/Output
PUPU (pull-up) resistor on module
PDPD (pull-down) resistor on module
VDD_INMain power source from carrier to module
CMOSLogic input or output
GBE MDIDifferential analog signaling for Gigabit Media Dependent Interface
LVDS DPLow Voltage Differential Signal for DisplayPort interface
LVDS D-PHYLow Voltage Differential Signal for MIPI CSI-2 cameras and DSI displays
LVDS M-PHYLow Voltage Differential Signal for MIPI CSI-3 cameras
LVDS LCDLow Voltage Differential Signal for LCD displays
LVDS PCIELow Voltage Differential Signal for PCIe
LVDS SATALow Voltage Differential Signal for SATA
TMDS HDMITransition Minimized Differential Signal for HDMI displays
USBDC coupled differential signaling for traditional (non-Superspeed) USB signals
USB SSDifferential signal for SuperSpeed USB signals
USB VBUS 5V5V tolerant input for USB VBUS detection
3.3V3.3V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
1.8V1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
3.3Vsb3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
1.8Vsb1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
# 4.3 Signal Description by function # 4.3.1 The First Display Interface The first display interface is a group of 30-pins that is split into a channel 0 and channel 1. The SMARC specification allows to support either dual channel LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display type such as DSI and eDP is also permitted. Below tables show which display ports are supported on this particular module
Pin #LVDS NameMIPI DSI NameeDP Name
S125LVDS0_0+DSI0_D0+eDP0_TX0+
S126LVDS0_0-DSI0_D0-eDP0_TX0-
S128LVDS0_1+DSI0_D1+eDP0_TX1+
S129LVDS0_1 -DSI0_D1-eDP0_TX1-
S131LVDS0_2+DSI0_D2+eDP0_TX2+
S132LVDS0_2-DSI0_D2-eDP0_TX2-
S137LVDS0_3+DSI0_D3+eDP0_TX3+
S138LVDS0_3-DSI0_D3-eDP0_TX3-
S134LVDS0_CK+DSI0_CLK+eDP0_AUX+
S135LVDS0_CK-DSI0_CLK-eDP0_AUX-
S133LCD0_VDD_ENLCD0_VDD_ENLCD0_VDD_EN
S127LCD0_BKLT_ENLCD0_BKLT_ENLCD0_BKLT_EN
S141LCD0_BKLT_PWMLCD0_BKLT_PWMLCD0_BKLT_PWM
S144DSI0_TEeDP0_HPD
S139I2C_LCD_CKI2C_LCD_CKI2C_LCD_CK
S140I2C_LCD_DATI2C_LCD_DATI2C_LCD_DAT
Pin #LVDS NameMIPI DSI NameeDP Name
S111LVDS1_0+DSI1_D0+eDP1_TX0+
S112LVDS1_0-DSI1_D0-eDP1_TX0-
S114LVDS1_1+DSI1_D1+eDP1_TX1+
S115LVDS1_1 -DSI1_D1-eDP1_TX1-
S117LVDS1_2+DSI1_D2+eDP1_TX2+
S118LVDS1_2-DSI1_D2-eDP1_TX2-
S120LVDS1_3+DSI1_D3+eDP1_TX3+
S121LVDS1_3-DSI1_D3-eDP1_TX3-
S108LVDS1_CK+DSI1_CLK+eDP1_AUX+
S109LVDS1_CK-DSI1_CLK-eDP1_AUX-
S116LCD1_VDD_ENLCD1_VDD_ENLCD1_VDD_EN
S107LCD1_BKLT_ENLCD1_BKLT_ENLCD1_BKLT_EN
S122LCD1_BKLT_PWMLCD1_BKLT_PWMLCD1_BKLT_PWM
S113DSI1_TEeDP1_HPD
4.3.1.1 LVDS0/LVDS1 mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
LVDS0_0+S125Primary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS0_0-S126
LVDS0_1+S128
LVDS0_1 -S129
LVDS0_2+S131
LVDS0_2-S132
LVDS0_3+S137
LVDS0_3-S138
LVDS0_CK+S134Primary LVDS channel differential pair clock linesO LVDS LCDRuntime
LVDS0_CK-S135
LCD0_VDD_ENS133Primary LVDS channel power enable, active highO CMOS1.8VRuntime
LCD0_BKLT_ENS127Primary LVDS channel backlight enable, active highO CMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary LVDS channel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
LVDS1_0+S111Secondary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS1_0-S112
LVDS1_1+S114
LVDS1_1 -S115
LVDS1_2+S117
LVDS1_2-S118
LVDS1_3+S120
LVDS1_3-S121
LVDS1_CK+S108Secondary LVDS channel differential pair clock lines.O LVDS LCDRuntime
LVDS1_CK-S109
LCD1_VDD_ENS116Secondary panel power enable, active highO CMOS1.8VRuntime
LCD1_BKLT_ENS107Secondary panel backlight enable, active highO CMOS1.8VRuntime
LCD1_BKLT_PWMS122Secondary panel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
4.3.1.2 DSI mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
DSI0_D0+S125Primary DSI panel differential pair data linesO LVDS D-PHYRuntimeBuild option
DSI0_D0-S126
DSI0_D1+S128
DSI0_D1-S129
DSI0_D2+S131
DSI0_D2-S132
DSI0_D3+S137
DSI0_D3-S138
DSI0_CLK+S134Primary DSI panel differential pair clock lines.O LVDS D-PHYRuntimeBuild option
DSI0_CLK-S135
LCD0_VDD_ENS133Primary panel power enable, active highO CMOS1.8VRuntime
LCD0_BKLT_ENS127Primary panel backlight enable, active highO CMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary panel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
DSI0_TES144Primary DSI panel tearing effect signalI CMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
# 4.3.2 Second & Third Display Interface
Pin #HDMI signal namesDP++ signal names
P92HDMI_D2+DP1_LANE0+
P93HDMI_D2-DP1_LANE0-
P95HDMI_D1+DP1_LANE1+
P96HDMI_D1-DP1_LANE1-
P98HDMI_D0+DP1_LANE2+
P99HDMI_D0-DP1_LANE2-
P101HDMI_CK+DP1_LANE3+
P102HDMI_CK-DP1_LANE3-
S105HDMI_CTRL_CKDP1_AUX+
S106HDMI_CTRL_DATDP1_AUX-
P104HDMI_HPDDP1_HPD
P107-DP1_AUX_SEL
Pin #DP++ signal names
P92DPO_LANE0+
P93DPO_LANE0-
P95DPO_LANE1+
P96DPO_LANE1-
P98DPO_LANE2+
P99DPO_LANE2-
P101DPO_LANE3+
P102DPO_LANE3-
S105DPO_AUX+
S106DPO_AUX-
P104DPO_HPD
P107DPO_AUX_SEL
![The image displays a red icon resembling a document or memo pad. It features a thick red outline forming a square shape with the bottom-right corner curled upwards. Inside the outline, there are two horizontal red lines centered vertically.](.smarc-lec-imx6r2-user-s-guide-final/8ae2bee0667adbe399110fea512b1b450b622eb102a53dc64b859f755bcfce14.jpg) Note: DisplayPort is not supported # 4.3.2.1 HDMI
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
HDMI_D2+P92HDMI port, differential pair data linesO TMDS HDMIRuntimeAC coupled off module
HDMI_D2-P93
HDMI_D1+P95
HDMI_D1-P96
HDMI_D0+P98
HDMI_D0-P99
HDMI_CK+P101HDMI port, differential pair clock linesO TMDS HDMIRuntimeAC coupled off module
HDMI_CK-P102
HDMI_CTRL_CKP105I2C_CLK line dedicated to HDMIO OD COMS1.8VRuntimePU 2.2Level shifter FET and 5V PU resistor shall be placed between the module and the HDMI connector.
HDMI_CTRL_DATP106I2C_DAT line dedicated to HDMII/O OD COMS1.8VRuntimePU 2.2KLevel shifter FET and 5V PU resistor shall be placed between the module and the HDMI connector.
HDMI_HPDP104HDMI Hot plug active high detection signal that serves as an interrupt requestI CMOS1.8VStandbyModule must tolerate high level in stand-by mode
# 4.3.3 MIPI Camera support 4.3.3.1 MIPI CSI0
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CSI0_RX0+CSI0_RX0-CSI0_RX1+CSI0_RX1-S11S12S14S15CSI0 differential input (point to point)I-LVDS-D-PHY/I-LVDS-M-PHY-Runtime--
CSI0_CK+CSI0_CK-S8S9CSI0 differential clock input (point to point)I-LVDS-D-PHY--Runtime--
I2C_CAM0_DAT/CSI0_TX-S7I2C data for serial camera data support link or differential data laneI/O OD-CMOS/O-LVDS-M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 uses I2C_CAM0_DATMIPI-CSI 3.0 uses CSIO_TX-
I2C_CAM0_CK/CSI0_TX+S5I2C clock for serial camera data support link or differential data laneO-OD-CMOS/O-LVDS-M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 uses I2C_CAM0_CKMIPI-CSI 3.0 uses CSIO_TX+
CAM0_PWR#/GPIO0P108Camera 0 Power Enable, active low output.O-CMOS1.8VRuntime--
CAM0_RST#/GPIO2P110Camera 0 reset, active low outputO-CMOS1.8VRuntime--
CAM_MCKS6Master clock outputO-CMOS1.8VRuntimeThis signal is used by both CSI0 and CSI1
4.3.3.2 MIPI CSI1 (Camera)
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CSI1_RX0+P7CSI1 differential input (point to point)I LVDS D-PHY / I LVDS M-PHYRuntimeSolo / Dualite limited to 2 data lines
CSI1_RX0-P8
CSI1_RX1+P10
CSI1_RX1-P11
CSI1_RX2+P13
CSI1_RX2-P14
CSI1_RX3+P16
CSI1_RX3-P17
CSI1_CK+P3CSI1 differential clock input (point to point)I LVDS D-PHYRuntime
CSI1_CK-P4
I2C_CAM1_DAT / CSI1_TX-S2I2C data for serial camera data support link or differential data laneI/O OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_DAT MIPI-CSI 3.0 mode uses CSI1_TX-
I2C_CAM1_CK / CSI1_TX+S1I2C clock for serial camera data support link or differential data laneO OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_CK MIPI-CSI 3.0 mode uses CSI1_TX+
CAM1_PWR# / GPIO1P109Camera 0 Power Enable, active low output.O CMOS1.8VRuntimeCAM1_PWR# is default, GPIO1 can be enabled through DVT
CAM1_RST# / GPIO3P111Camera 0 reset, active low outputO CMOS1.8VRuntimeCAM1_PWR# is default, GPIO3 can be enabled through DVT
CAM_MCKS6Master clock outputO CMOS1.8VRuntimeThis signal is used by both CSI0 and CSI1
4.3.4 I2S (audio)
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2S0_LRCKS39I2S0 Left & Right synchronization clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S0_SDOUTS40I2S0 Digital audio OutputO CMOS1.8VRuntime
I2S0_SDINS41I2S0 Digital audio InputI CMOS1.8VRuntime
I2S0_CKS42I2S0 Digital audio clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_LRCKS50I2S2 Left & Right synchronization clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_SDOUTS51I2S2 Digital audio OutputO CMOS1.8VRuntime
I2S2_SDINS52I2S2 Digital audio InputI CMOS1.8VRuntime
I2S2_CKS53I2S2 Digital audio clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
AUDIO_MCKS38Master clock output to I2S codec(s)O CMOS1.8VRuntime
![The image features a red icon on a white background depicting a document or page symbol. It has a folded corner at the top right and contains two horizontal lines inside the outline, resembling text.](.smarc-lec-imx6r2-user-s-guide-final/ce9fcd09b3b50366d9c433b5c347bbd3db1c650204a27247809a7433cab7552f.jpg) Note: support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification # 4.3.5 USB ports
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
USB0+USB0-P60P61USB differential data pairs for port 0I/OUSBUSBRuntimeFrom SOC
USB0_EN_OC#P62USB over-current sense for port 0I/O OD CMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB0_VBUS_DETP63USB port 0 host power detection, when this port is used as a device.I USB VBUS 5VUSB VBUS 5VRuntimeCan be connected to a USB client port VBUS pin
USB0_OTG_IDP64Input pin to announce OTG device insertion on USB 2.0 portICMOS3.3Vsb / 3.3VRuntime
USB1+USB1-P65P66USB differential data pairs for port 1I/OUSBUSBRuntimeFrom USB HUB
USB1_EN_OC#P67USB over-current sense for port 1I/O OD CMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB2+USB2-P69P70USB differential data pairs for port 2I/OUSBUSBRuntimeFrom USB HUB
USB2_SSRX+USB2_SSRX-S74S75Receive signal differential pairs for SuperSpeed on port 2↓USB SSUSB SSRuntime-
USB2_SSTX+USB2_SSTX-S71S72Transmit signal differential pairs for SuperSpeed on port 2QUSB SSUSB SSRuntime-
USB2_EN_OC#P71USB over-current sense for port 2I/O OD CMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB3+USB3-S68S69USB differential data pairs for port 3I/OUSBUSBRuntimeFrom USB HUB
USB3_SSRX+USB3_SSRX-S65S66Receive signal differential pairs for SuperSpeed on port 3↓USB SSUSB SSRuntime-
USB3_SSTX+USB3_SSTX-S62S63Transmit signal differential pairs for SuperSpeed on port 3OUSB_SSUSB_SSRuntime-
USB3_EN_OC#P74USB over-current sense for port 3I/O OD CMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB3_VBUS_DETS37USB port 3 host power detection, when this port is used as a device.↑USB_VBUS5VUSBVBUS 5VRuntime--
USB3_OTG_IDS104Input pin to announce OTG device insertion on USB 3.0 port↓CMOS3.3Vsb / 3.3VRuntime--
USB4+USB4-S35S36USB differential data pairs for port 4I/OUSBUSBRuntime
USB4_EN_OC#P76USB over-current sense for port 4I/O ODCMOS3.3Vsb /3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB5+USB5-S59S60USB differential data pairs for port 5I/OUSBUSBStandby-
USB5_EN_OC#S55USB over-current sense for port 5I/O ODCMOS-3.3Vsb /3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over current situation.
![The image displays a document icon characterized by a white rectangle with rounded corners and a thick red outline. The top-right corner is folded down. Inside the shape, two horizontal red lines are stacked vertically in the center.](.smarc-lec-imx6r2-user-s-guide-final/8092413df6bb8059a7c58b35df1738918cedc6d55ab17238a030d0b228ee74a7.jpg) Note: USB0 is directly connected to the SOC, USB1/2/3/4 have shared bandwidth through a HUB, USB5 is not supported # 4.3.6 PCIe Ports The module supports two PCIe Gen 2.1 ports (PCIE\_A and PCIE\_B).
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
PCIE_A_TX+PCIE_A_TX-P89P90Differential PCIe link A transmit data pairO LVDSPCIERuntimeSeries AC coupled on module
PCIE_A_RX+PCIE_A_RX-P86P87Differential PCIe link A receive data pairI LVDSPCIERuntimeSeries AC coupled off module
PCIE_A_REFCK+PCIE_A_REFCK-P83P84Differential PCIe Link A reference clock outputO LVDSPCIERuntime
PCIE_A_RST#P75PCIe Port A reset outputOCMOS3.3VRuntime
PCIE_A_CKREQ#P78PCIe Port A clock request+OD-CMOS3.3VRuntime-No need for this signal because module provides onboard PCIe clock
PCIE_B_TX+PCIE_B_TX-S90S91Differential PCIe link B transmit data pair-O LVDSPCIE-Runtime-Series AC coupled on module
PCIE_B_RX+PCIE_B_RX-S87S88Differential PCIe link B receive data pair-I LVDSPCIE-Runtime-Series AC coupled off module
PCIE_B_REFCK+PCIE_B_REFCK-S84S85Differential PCIe Link B reference clock output-O LVDSPCIE-Runtime--
PCIE_B_RST#S76PCIe Port B reset output-O-CMOS3.3VRuntime--
PCIE_B_CKREQ#P77PCIe Port B clock request+OD-CMOS3.3VRuntimeNo need for this signal because module provides onboard PCIe clock
PCIE_C_TX+PCIE_C_TX-S81S82Differential PCIe link C transmit data pair-O LVDSPCIE-Runtime-Series AC coupled on module
PCIE_C_RX+PCIE_C_RX-S78S79Differential PCIe link C receive data pair-I LVDSPCIE-Runtime-Series AC coupled off module
PCIE_C_REFCK+PCIE_C_REFCK-P80P81Differential PCIe Link C reference clock output-O LVDSPCIE-Runtime--
PCIE_C_RST#S77PCIe Port C reset output-O-CMOS3.3VRuntime--
PCIE_D_TX+PCIE_D_TX-S29S30Differential PCIe link D transmit data pair-O-LVDS-PCIE-Runtime-Series AC coupled on module
PCIE_D_RX+PCIE_D_RX-S32S33Differential PCIe link D receive data pair-I-LVDS-PCIE-Runtime-Series AC coupled off module
PCIE_WAKE#S146PCIe wake up interrupt to host – common to PCIe links A, B, C, DIOD CMOS3.3VRuntimePU 10k
![The image displays a red icon resembling a document or page. It features a thick red border with a folded corner at the bottom right. Inside the border are two horizontal red lines of unequal length, the top one being longer than the bottom one.](.smarc-lec-imx6r2-user-s-guide-final/b8dc8f2bbdb84791f7be9b18539842a25169294e0324edcb25dd75893e0948c0.jpg) Note: Module provides PCIe clock generators for PCIE\_A so no external clock source on the carrier is needed 4.3.7 SATA Ports
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SATA0_TX+SATA0_TX-P48P49Serial ATA channel 0, Transmit Output differential pair.O SATARuntimeSeries AC coupled on Module 10 nF
SATA0_RX+SATA0_RX-P51P52Serial ATA channel 0, Receive Input differential pair.I SATARuntimeSeries AC coupled on Module 10 nF
SATA_ACT#S54SATA activity indicatorO ODCMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
# 4.3.8 LAN ports # 4.3.8.1 First LAN port The first LAN port is derived from the SOCs RGMII interface
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE0_MD10+P30Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:GBE MDIRuntimeTwisted pair signals for external transformer.
GBE0_MD10-P29
GBE0_MD11+P27
GBE0_MD11-P26
GBE0_MD12+P24
GBE0_MD12-P231000 100 10
GBE0_MD13+P20MDI[0]+/- B1_DA+/- TX+/- TX+/-
GBE0_MD13-P19MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
GBE0_LINK100#P21Link Speed Indication LED for GBE 0 100MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_LINK1000#P22Link Speed Indication LED for GBE 0 1000MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_LINK_ACT#P25Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on ActivityO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_CTREFP28Center Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)Analog0 to 3.3V maxRuntime--
GBE0_SDPP6IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VRuntime
# 4.3.8.2 Second LAN port Second LAN port is derived from USB hub
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE1_MDI0+S17Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:GBE MDIRuntimeTwisted pair signals for external transformer.
GBE1_MDI0-S18
GBE1_MDI1+S20
GBE1_MDI1-S21
GBE1_MDI2+S23
GBE1_MDI2-S241000 100 10MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-
GBE1_MDI3+S26
GBE1_MDI3-S27
GBE1_LINK100#S19Link Speed Indication LED for GBE 1 100MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_LINK1000#S22Link Speed Indication LED for GBE 1 1000MbpsO OD CMOS3.3VRuntime-Shall be able to sink 24mA or more Carrier LED current
GBE1_LINK_ACT#S31Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on ActivityO OD CMOS3.3VRuntime-Shall be able to sink 24mA or more Carrier LED current
GBE1_CTREFS28Center Tap reference voltage for Carrier board Ethernet magnetic ‘(if required by the Module GBE PHY)’Analog0 to 3.3V maxRuntime
GBE1_SDPP5IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VRuntime
4.3.9 SDIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SDIO_D0P39SDIO Data lines. These signals operate in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_D1P40
SDIO_D2P41
SDIO_D3P42
SDIO_WPP33SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CMDP34SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_CD#P35SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CKP36SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.O CMOS1.8V or 3.3VRuntime
SDIO_PWR_ENP37SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.O CMOS3.3VRuntime-should be driven low in STB Mode by the module
# 4.3.10 SPI & ESPI 4.3.11 SPI0
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SPI0_CS0#P43SPI0 Master Chip Select 0O CMOS1.8VStandbyThis signal can be used to select carrier SPI as boot device
SPI0_CS1#P31SPI0 Master Chip Select 1O CMOS1.8VStandby
SPI0_CKP44SPI0 ClockO CMOS1.8VStandby-
SPI0_DINP45SPI0 Master input / Slave outputI CMOS1.8VStandbyalso referred to as MISO
SPI0_DOP46SPI0 Master output / Slave inputO CMOS1.8VStandbyalso referred to as MOSI
SPI1_CS0#P54SPI1 Master Chip Select 0O CMOS1.8VStandby-See ESPI
SPI1_CS1#P55SPI1 Master Chip Select 1O CMOS1.8VStandby-See ESPI
SPI1_CKP56SPI1 ClockO CMOS1.8VStandby-See ESPI
SPI1_DINP57SPI1 Master input / Slave outputI CMOS1.8VStandby-See ESPI
SPI1_DOP58SPI1 Master output / Slave inputO CMOS1.8VStandby-See ESPI
![The image displays a square icon with a folded top-right corner, outlined in a thick red border. Inside the white square, there are two horizontal red lines centered vertically. This is the icon for Google Docs.](.smarc-lec-imx6r2-user-s-guide-final/6deb28a81f23fb2d7a645bc634ca71380bbb775c1307b8735d18b52ecffb89bc.jpg) Note: SPI0 is free to use on the carrier but support only one device through CS0 SPI1 supports a CAN bus controller on the module through CS0, that leaves CS1 free for a device on the carrier 4.3.12 ESPI
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
ESPI_CS0#P54ESPI1 Master Chip Select 0O CMOS1.8VStandby
ESPI_CS1#P55ESPI1 Master Chip Select 1O CMOS1.8VStandby
ESPI_CKP56ESPI Master Clock outputO CMOS1.8VStandby
ESPI_RESET#S58ESPI ResetO CMOS1.8VStandbyReset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves
ESPI_ALERT0#ESPI_ALERT1#S43S44ESPI ALERTI-OD CMOS1.8VStandbyThis pin is used by eSPI slave to request service from eSPI.master.Alert# is an open-drain output from the slave.This pin is optional for Single Master-Single Slave configuration where I/O[1] can be used to signal the Alert event.
ESPI_IO_0ESPI_IO_1ESPI_IO_2ESPI_IO_3P58P57S56S57ESPI Master Data Input / Output.-I/O CMOS1.8VStandbyESPI_IO_0 can also be used as SPI1_DO (MOSI)ESPI_IO_1 can also be used as SPI1_DIN (MISO)In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO).
![The image displays a red icon representing a document or page. It features a thick red outline forming a rectangle with rounded corners. Inside the outline, there are two horizontal red lines centered vertically, resembling lines of text on a page.](.smarc-lec-imx6r2-user-s-guide-final/1997e170ad472238e0063456c7cb9a35bded8943263c5e17135742f0211731d9.jpg) Note: On NXP i.MX8M parts ECSPI is used (Enhanced Configurable Serial Peripheral Interface) # 4.4 General Purpose I2C The SMARC specification supports a total of 6 different I2C busses on its pinout. Most of these busses are designated for specific functions such as I2C for camera management, I2C for EDID on HDMI, LVDS panels or I2C for PMIC. Just one I2C bus is marked as General purpose
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2C_GP_DATS49General purpose I2C data signalI/O OD CMOS1.8VRuntimePU 2k2
I2C_GP_CKS48General purpose I2C clock signalO OD CMOS1.8VRuntimePU 2k2
Most of the other I2C busses are described in their designated function tables rather than in a single big list. Below is an overview of all I2C busses and where to find them.
NamePin #DescriptionWhere to find
I2C_LCD_DATS140DDC data line used for flat panel detection and controlLVDS / DSI / eDP tables
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlLVDS / DSI / eDP tables
HDMI_CTRL_CKP105I2C_CLK line dedicated to HDMIHDMI table
HDMI_CTRL_DATP106I2C_DAT line dedicated to HDMIHDMI table
I2C_CAM0_DATS7I2C data for serial camera data support linkMIPI CSI table
I2C_CAM0_CKS5I2C clock for serial camera data support linkMIPI CSI table
I2C_CAM1_DATS2I2C data for serial camera data support linkMIPI CSI table
I2C_CAM1_CKS1I2C clock for serial camera data support linkMIPI CSI table
I2C_PM_DATP122Power management I2C bus DATA (SMBus for x86)Power and System Management
I2C_PM_CKP121Power management I2C bus CLK (SMBus for x86)Power and System Management
4.4.1 GPIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GPIO0 / CAM0_PWR#P108General purpose I/O pin 0.I/O CMOS1.8VRuntimePU 470K on the Module.Default use is GPIO0, alternative use is Camera 0 Power Enable - active low, through DTS
GPIO1 / CAM1_PWR#P109General purpose I/O pin 1.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS
GPIO2 / CAM0_RST#P110General purpose I/O pin 2.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO2, alternative use is Camera 0 Reset - active low, through DTS
GPIO3 / CAM1_RST#P111General purpose I/O pin 3.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS
GPIO4 / HDA_RST#P112General purpose I/O pin 4.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO5 / PWM_OUTP113General purpose I/O pin 5.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO6P114General purpose I/O pin 6.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO7P115General purpose I/O pin 7.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO8P116General purpose I/O pin 8.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO9P117General purpose I/O pin 9.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO10P118General purpose I/O pin 10.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO11P119General purpose I/O pin 11.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO12S142General purpose I/O pin 12I/O CMOS1.8VRuntimePU 470K on the Module
GPIO13S123General purpose I/O pin 13I/O CMOS1.8VRuntimePU 470K on the Module
4.4.2 UART
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SER0_TXP129Asynchronous serial data output port 0O CMOS1.8VRuntime
SER0_RXP130Asynchronous serial data input port 0I CMOS1.8VRuntime
SER0_RTS#P131"Request to Send" handshake line for port 0O CMOS1.8VRuntime
SER0_CTS#P132"Clear to Send" handshake line for port 0I CMOS1.8VRuntime
SER1_TXP134Asynchronous serial data output port 1O CMOS1.8VRuntime
SER1_RXP135Asynchronous serial data input port 1I CMOS1.8VRuntime
SER2_TXP136Asynchronous serial data output port 2O CMOS1.8VRuntime--
SER2_RXP137Asynchronous serial data input port 2I CMOS1.8VRuntime--
SER2_RTS#P138"Request to Send" handshake line for port 2O CMOS1.8VRuntime--
SER2_CTS#P139"Clear to Send" handshake line for port 2I CMOS1.8VRuntime--
SER3_TXP140Asynchronous serial data output port 3O CMOS1.8VRuntime
SER3_RXP141Asynchronous serial data input port 3I CMOS1.8VRuntime
Four asynchronous serial ports are supported. The ports are designated SER0 – SER3. Ports SER0 and SER2 are 4 wire ports, (2 data - and 2 handshake lines). Ports SER1 and SER3 are 2 wire ports (data only). # 4.4.3 CAN bus
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CAN0_TXP143CAN port 0 Transmit outputO CMOS1.8VRuntime
CAN0_RXP144CAN port 0 Receive inputI CMOS1.8VRuntime
CAN1_TXP145CAN port 1 Transmit outputO CMOS1.8VRuntime
CAN1_RXP146CAN port1 Receive inputI CMOS1.8VRuntime
# 4.4.4 Miscellaneous
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
TEST#S157Held low by Carrier to invoke Module vendor specific test function(s).ICMOS1.8VRuntimePU 47Module must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation
WDT_TIME_OUT#S145Watch-Dog-Timer Output, low active.OCMOS1.8VRuntimeDriven only during runtime
4.4.5 Power and System Management
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BATLOW#S156Battery low indication to Module.Carrier to float the line in inactive state.IOD CMOS1.8 to 5VStandby/SleepPU 10kDriven by OD on Carrier
CARRIER_PWR_ONS154Carrier Board circuits (apart from power management and power path circuits)Should Notbe powered up until the Module asserts the CARRIER_PWR_ON signal.OCMOS1.8Vsb / 1.8VStandbyOn x86 designs this pin should utilize a standby related power signal i.e.RSM_RST# or SLP_A# signal.
CARRIER_STBY#S153The ModuleShalldrive this signal low when the system is in a standby power state.OCMOS1.8VStandbyOn x86 designs this pin should utilize the SUS_S3# signal.
CHARGER_PRSNT#S152Held low by Carrier if DC input for battery charger is present.IOD CMOS1.8 to 5VStandby/SleepPU 10kDriven by OD on Carrier.
CHARGING#S151Held low by Carrier during battery charging.Carrier to float the line when charge is complete.IOD CMOS1.8 to 5VStandby/SleepPU 10kDriven by OD on Carrier.
VIN_PWR_BAD#S150Power bad indication from Carrier Board.Module and Carrier power supplies (other than Module and Carrier power supervisory circuits)Shall Notbe enabled while this signal is held low by the Carrier.IOD CMOSVDD_INPU 10kModule must implement PU but actual value is depended on particular Module design. Driven by OD on Carrier
SLEEP#S149Sleep indicator from Carrier Board.Maybesourced from user Sleep button or Carrier logic.Carrier to float the line in in-active state. Active low, level sensitive.Should be de-bounced on the Module.IOD CMOS1.8 to 5VStandbyPU 10kDriven by OD on Carrier.
LID#S148Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive.Should be de-bounced on the Module.IOD CMOS1.8 to 5VStandbyPU 10kDriven by OD on Carrier.
POWER_BTN#P128Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive.Should be debounced on the Module.IOD CMOS1.8 to 5VSleepPU 10kDriven by OD on Carrier.
RESET_OUT#P126General purpose reset output to Carrier board.O CMOS1.8VRuntime
RESET_IN#P127Reset input from Carrier Board. Carrier drives low to force a Module reset, floats the line otherwise. This signal Shall be level triggered during bootup to allow to stop booting of the module. After bootup it May act as an edge triggered signal.I OD CMOS1.8 to 5VStandbyPU 10kDriven by OD on Carrier.
I2C_PM_DATP122Power management I2C bus DATAI/O OD CMOS1.8VRuntimePU 2k2On x86 systems these serve as SMB DATA.Pulled up on module.
I2C_PM_CKP121Power management I2C bus CLKO OD CMOS1.8VRuntimePU 2k2On x86 systems these serve as SMB CLK.Pulled up on module.
SMB_ALERT_1V8#P1SMBus Alert# (interrupt) signalI OD CMOS1.8VRuntimePU 2k2only used on x86 design
# 4.4.6 DB30 Multipurpose Connector FPC Connector type : HIROSE,FH12-30S-0.5SH(55) ![PIN No. 1\n⑤\n''\n0.15 ±0.05\n±0.2 A\n③\nPIN No. n\n④\n①\n②\nA'](.smarc-lec-imx6r2-user-s-guide-final/4a3b4b7026833cc8daad76bc7bc8d37f725345173739a297ab2a379c540b2ef0.jpg) DB30 connector brings out the following type of signals SPI0 bus JTAG to SOC Boot Select strap pins BMC programming interface Serial port 4.4.7 Boot Select
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BOOT_SEL0#P123Input straps determine the Module bootI OD CMOS1.8VsbStandbyPU 4.7KDriven by OD on Carrier.Pulled up on module.Only booting from EMMc and SDcard is supported
BOOT_SEL1#P124
BOOT_SEL2#P125
FORCE_RECOV#S155I OD CMOS1.8VsbStandbyPU 10K-Driven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.
4.4.8 Power
NamePin #DescriptionI/O TypePower Rail / TolerancePU / PDComments
VDD_INP147, P148, P149, P150, P151, P152, P153, P154, P155, P156Module power input voltage 4.75 min to 5.25V max3 to 5.25V / 5V
GNDP2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158Module signal and power return, and GND referenceGround
VDD_RTCS147Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.[2 to 3.25] / 3.25V
4.5 SMARC pin to controller mapping
PinSMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
P1SMB_ALERT_1V8#--
P2GND--
P3CSI1_CK+In-LVDS D-PHYi.MX6 QP/Q/DP/D/DL/SCSI_CLK0P-NVCC_MIPI
P4CSI1_CK-In-LVDS D-PHYi.MX6 QP/Q/DP/D/DL/SCSI_CLK0M-NVCC_MIPI
P5GBE1_SDP--
P6GBE0_SDP--
P7CSI1_RX0+In-LVDS D-PHYi.MX6 QP/Q/DP/D/DL/SCSI_D0P-NVCC_MIPI
P8CSI1_RX0-In-LVDS D-PHYi.MX6 QP/Q/DP/D/DL/SCSI_D0M-NVCC_MIPI
P9GND--
P10CSI1_RX1+In-LVDS D-PHYi.MX6 QP/Q/DP/D/DL/SCSI_D1P-NVCC_MIPI
P11CSI1_RX1-In-LVDS D-PHYi.MX6 QP/Q/DP/D/DL/SCSI_D1M-NVCC_MIPI
P12GND--
P13CSI1_RX2+In-LVDS D-PHYi.MX6 QP/Q/DP/DCSI_D2P-NVCC_MIPI
P14CSI1_RX2-In-LVDS D-PHYi.MX6 QP/Q/DP/DCSI_D2M-NVCC_MIPI
P15GND--
P16CSI1_RX3+In-LVDS D-PHYi.MX6 QP/Q/DP/DCSI_D3P-NVCC_MIPI
P17CSI1_RX3-In-LVDS D-PHYi.MX6 QP/Q/DP/DCSI_D3M-NVCC_MIPI
P18GND--
P19GBE0_MDI3-Bi-Dir-GBE MDIAR8035-AL1BTRXN3-NVCC_RGMII
P20GBE0_MDI3+Bi-Dir-GBE MDIAR8035-AL1BTRXP3-NVCC_RGMII
P21GBE0_LINK100#Out/OD-CMOS/3.3VAR8035-AL1BLED_10_100-NVCC_RGMII
P22GBE0_LINK1000#Out/OD-CMOS/3.3VAR8035-AL1BLED_1000-NVCC_RGMII
P23GBE0_MDI2-Bi-Dir-GBE MDIAR8035-AL1BTRXN2-NVCC_RGMII
P24GBE0_MDI2+Bi-Dir-GBE MDIAR8035-AL1BTRXP2-NVCC_RGMII
P25GBE0_LINK_ACT#Out/OD-CMOS/3.3VAR8035-AL1BLED_ACT-NVCC_RGMII
P26GBE0_MDI1-Bi-Dir-GBE MDIAR8035-AL1BTRXN1-NVCC_RGMII
P27GBE0_MDI1+Bi-Dir-GBE MDIAR8035-AL1BTRXP1-NVCC_RGMII
P28GBE0_CTREF--
P29GBE0_MD10-Bi-Dir-GBE MDIAR8035-AL1BTRXN0-NVCC_RGMII
P30GBE0_MD10+Bi-Dir-GBE MDIAR8035-AL1BTRXP0-NVCC_RGMII
P31SPI0_CS1#Out-CMOS/1.8Vi.MX6DISP0_DAT4Alt2NVCC_LCD
P32GND--
P33SDIO_WPIn-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SGPIO_2Alt6NVCC_GPIO
P34SDIO_CMDBi-Dir-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SSD2_CMDAlt0NVCC_SD2
P35SDIO_CD#In-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SGPIO_4Alt6NVCC_SD2
P36SDIO_CKOut-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SSD2_CLKAlt0NVCC_SD2
P37SDIO_PWR_ENOut-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SKEY_COL2Alt5NVCC_GPIO
P38GND--CMOS/3.3V
P39SDIO_D0Bi-Dir-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SSD2_DAT0Alt0NVCC_SD2
P40SDIO_D1Bi-Dir-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SSD2_DAT1Alt0NVCC_SD2
P41SDIO_D2Bi-Dir-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SSD2_DAT2Alt0NVCC_SD2
P42SDIO_D3Bi-Dir-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SSD2_DAT3Alt0NVCC_SD2
P43SPI0_CS0#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT3Alt2NVCC_LCD
P44SPI0_CKOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT0Alt2NVCC_LCD
P45SPI0_DINIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT2Alt2NVCC_LCD
P46SPI0_DOOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT1Alt2NVCC_LCD
P47GND--
P48SATA_TX+Outserial-0.1uSATAi.MX6 QP/Q/DP/DSATA_TXP-SATA_VPH
P49SATA_TX-Outserial-0.1uSATAi.MX6 QP/Q/DP/DSATA_TXM-SATA_VPH
P50GND--
P51SATA_RX+Inserial-0.1uSATAi.MX6 QP/Q/DP/DSATA_RXP-SATA_VPH
P52SATA_RX-Inserial-0.1uSATAi.MX6 QP/Q/DP/DSATA_RXM-SATA_VPH
P53GND--
P54ESPI_CS0# / SPI1_CS0#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_RWAlt2NVCC_EIM1
P55ESPI_CS1# / SPI1_CS1#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_LBAAlt2NVCC_EIM1
P56ESPI_CK / SPI1_CKOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_CS0Alt2NVCC_EIM1
P57ESPI_IO_1 / SPI1_DINIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_OEAlt2NVCC_EIM1
P58ESPI_IO_0 / SPI1_DOOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_CS1Alt2NVCC_EIM1
P59GND--
P60USB0+Bi-Dir-USBi.MX6 QP/Q/DP/D/DL/SUSB_OTG_DP-VDD_USB_CAP
P61USB0-Bi-Dir-USBi.MX6 QP/Q/DP/D/DL/SUSB_OTG_DN-VDD_USB_CAP
P62USB0_EN_OC#InPU-10KCMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SENET_RXD0Alt5NVCC_ENET
P63USB0_VBUS_DETPWR-USB VBUS/5Vi.MX6 ??USB_OTG_VBUS--
P64USB0_OTG_IDIn-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SENET_RX_ERAlt0NVCC_ENET
P65USB1+Bi-Dir-USBLAN9514-JZXUSBDP2--
P66USB1-Bi-Dir-USBLAN9514-JZXUSBDM2--
P67USB1_EN_OC#InPU-10KCMOS/3.3VLAN9514-JZXPRTCTL2--
P68GND--
P69USB2+Bi-Dir-USBLAN9514-JZXUSBDP3--
P70USB2-Bi-Dir-USBLAN9514-JZXUSBDM3--
P71USB2_EN_OC#InPU-10KCMOS/3.3VLAN9514-JZXPRTCTL3--
P72RSVD--
P73RSVD--
P74USB3_EN_OC#InPU-10KCMOS/3.3VLAN9514-JZXPRTCTL4--
P75PCIE_A_RST#Out-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SGPIO_17Alt5NVCC_GPIO
P76USB4_EN_OC#InPU-10KCMOS/3.3VLAN9514-JZXPRTCTL5--
P77PCIE_B_CREQ#--
P78PCIE_A_CREQ#--
P79GND--
P80PCIE_C_REFCK+--
P81PCIE_C_REFCK---
P82GND--
P83PCIE_A_REFCK+Outserial-0.1u, PD-49.9PCIei.MX6 QP/Q/DP/D/DL/SCLK1_P-VDD_HIGH_CAP
P84PCIE_A_REFCK-Outserial-0.1u, PD-49.9PCIei.MX6 QP/Q/DP/D/DL/SCLK1_N-VDD_HIGH_CAP
P85GND--
P86PCIE_A_RX+Inserial-0RPCIei.MX6 QP/Q/DP/D/DL/SPCIE_RXP-PCIE_VPH
P87PCIE_A_RX-Inserial-0RPCIei.MX6 QP/Q/DP/D/DL/SPCIE_RXM-PCIE_VPH
P88GND--
P89PCIE_A_TX+Outserial-0.1uPCIei.MX6 QP/Q/DP/D/DL/SPCIE_TXP-PCIE_VPH
P90PCIE_A_TX-Outserial-0.1uPCIei.MX6 QP/Q/DP/D/DL/SPCIE_TXM-PCIE_VPH
P91GND--
P92HDMI_D2+ / DP1_LANE0+Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_D2P-HDMI_VPH
P93HDMI_D2- / DP1_LANE0-Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_D2M-HDMI_VPH
P94GND--
P95HDMI_D1+ / DP1_LANE1+Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_D1P-HDMI_VPH
P96HDMI_D1- / DP1_LANE1-Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_D1M-HDMI_VPH
P97GND--
P98HDMI_D0+ / DP1_LANE2+Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_D0P-HDMI_VPH
P99HDMI_D0- / DP1_LANE2-Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_D0M-HDMI_VPH
P100GND--
P101HDMI_CK+ / DP1_LANE3+Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_CLKP-HDMI_VPH
P102HDMI_CK- / DP1_LANE3-Out-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_CLKM-HDMI_VPH
P103GND--
P104HDMI_HPD / DP1_HPDIn-HDMIi.MX6 QP/Q/DP/D/DL/SHDMI_HPD-HDMI_VPH
P105HDMI_CTRL_CK / DP1_AUX+OutPU-1.5KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_COL3Alt2NVCC_GPIO
P106HDMI_CTRL_DAT / DP1_AUX-Bi-DirPU-1.5KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_ROW3Alt2NVCC_GPIO
P107DP1_AUX_SEL--
P108GPIO0 / CAM0_PWR#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_A25Alt5NVCC_EIM0
P109GPIO1 / CAM1_PWR#OutPU-470KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT13Alt5NVCC_LCD
P110GPIO2 / CAM0_RST#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT12Alt5NVCC_LCD
P111GPIO3 / CAM1_RST#OutPU-470KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT14Alt5NVCC_LCD
P112GPIO4 / HDA_RST#Bi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT15Alt5NVCC_LCD
P113GPIO5 / PWM_OUTOutPU-470KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD1_DAT1Alt2NVCC_SD1
P114GPIO6 / TACHINBi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD1_DAT0Alt5NVCC_SD1
P115GPIO7Bi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT17Alt5NVCC_LCD
P116GPIO8Bi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT18Alt5NVCC_LCD
P117GPIO9Bi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT19Alt5NVCC_LCD
P118GPIO10Bi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT20Alt5NVCC_LCD
P119GPIO11Bi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT21Alt5NVCC_LCD
P120GND--
P121I2C_PM_CKOutPU-1KI2C2i.MX6 QP/Q/DP/D/DL/SEIM_EB2Alt6NVCC_EIM0
P122I2C_PM_DATBi-DirPU-1KI2C2i.MX6 QP/Q/DP/D/DL/SEIM_D16Alt6NVCC_EIM0
P123BOOT_SEL0#InPU-4.7KCMOS/1.8VBMCPB3--
P124BOOT_SEL1#InPU-4.7KCMOS/1.8VBMCPB5--
P125BOOT_SEL2#InPU-4.7KCMOS/1.8VBMCPA2--
P126RESET_OUT#Out-CMOS/1.8VBMCPC4--
P127RESET_IN#InPU-10KCMOS/1.8VBMCPC12--
P128POWER_BTN#In-CMOS/1.8VBMCPA11--
P129SER0_TXOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD3_DAT7Alt1NVCC_SD3
P130SER0_RXIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD3_DAT6Alt1NVCC_SD3
P131SER0_RTS#In-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_D20Alt4NVCC_EIM0
P132SER0_CTS#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_D19Alt4NVCC_EIM0
P133GND--
P134SER1_TXOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_D26Alt4NVCC_EIM0
P135SER1_RXIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_D27Alt4NVCC_EIM0
P136SER2_TXIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_COL1Alt4NVCC_GPIO
P137SER2_RXOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_ROW1Alt4NVCC_GPIO
P138SER2_RTS#In-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_COL4Alt4NVCC_GPIO
P139SER2_CTS#Out-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_ROW4Alt4NVCC_GPIO
P140SER3_TXOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_COL0Alt4NVCC_GPIO
P141SER3_RXIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SKEY_ROW0Alt4NVCC_GPIO
P142GND--
P143CAN0_TXOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD3_CMDAlt2NVCC_SD3
P144CAN0_RXIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD3_CLKAlt2NVCC_SD3
P145CAN1_TXOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD3_DAT0Alt2NVCC_SD3
P146CAN1_RXIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SSD3_DAT1Alt2NVCC_SD3
P147VDD_INPWR
P148VDD_INPWR
P149VDD_INPWR
P150VDD_INPWR
P151VDD_INPWR
P152VDD_INPWR
P153VDD_INPWR
P154VDD_INPWR
P155VDD_INPWR
P156VDD_INPWR
S1CSI1_TX+ / I2C_CAM1_CKInPU-2.2KI2C1i.MX6 QP/Q/DP/D/DL/SCSI0_DAT9Alt4NVCC_CSI
S2CSI1_TX- / I2C_CAM1_DATInPU-2.2KI2C1i.MX6 QP/Q/DP/D/DL/SCSI0_DAT8Alt4NVCC_CSI
S3GND--
S4RSVD--
S5CSI0_TX- / I2C_CAM0_CK--
S6CAM_MCKOutserial-0RCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SGPIO_0Alt0NVCC_GPIO
S7CSI0_TX+ / I2C_CAM0_DAT--
S8CSI0_CK+--
S9CSI0_CK---
S10GND--
S11CSI0_RX0+--
S12CSI0_RX0---
S13GND--
S14CSI0_RX1+--
S15CSI0_RX1---
S16GND--
S17GBE1_MDI0+Bi-DirPU-49.9RRGMIILAN9514-JZXTXP--
S18GBE1_MDI0-Bi-DirPU-49.9RRGMIILAN9514-JZXTXN--
S19GBE1_LINK100#Outserial-0RRGMIILAN9514-JZXnSPD_LED/GPIO2--
S20GBE1_MDI1+Bi-DirPU-49.9RRGMIILAN9514-JZXRXP--
S21GBE1_MDI1-Bi-DirPU-49.9RRGMIILAN9514-JZXRXN--
S22GBE1_LINK1000#----
S23GBE1_MDI2+--
S24GBE1_MDI2---
S25GND--
S26GBE1_MDI3+--
S27GBE1_MDI3---
S28GBE1_CTREF--
S29PCIE_D_TX+ / SERDES_1_TX+--
S30PCIE_D_TX- / SERDES_1_TX---
S31GBE1_LINK_ACT#Outserial-0RGMIILAN9514-JZXnLNKA_LED/GPIO1--
S32PCIE_D_RX+ / SERDES_1_RX+----
S33PCIE_D_RX- / SERDES_1_RX-----
S34GND--
S35USB4+Bi-Dir-USBLAN9514-JZXUSBDP5--
S36USB4-Bi-Dir-USBLAN9514-JZXUSBDM5--
S37USB3_VBUS_DET----
S38AUDIO_MCKOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SGPIO_3Alt4NVCC_GPIO
S39I2S0_LRCKBi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SCSI0_DAT6Alt4NVCC_CSI
S40I2S0_SDOUTOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SCSI0_DAT5Alt4NVCC_CSI
S41I2S0_SDINIn-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SCSI0_DAT7Alt4NVCC_CSI
S42I2S0_CKBi-Dir-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SCSI0_DAT4Alt4NVCC_CSI
S43ESPI_ALERT0#--
S44ESPI_ALERT1#--
S45MDIO_CLK--
S46MDIO_DAT--
S47GND--
S48I2C_GP_CKOutPU-2.2KI2C3i.MX6 QP/Q/DP/D/DL/SEIM_D17Alt6NVCC_EIM0
S49I2C_GP_DATBi-DirPU-2.2KI2C3i.MX6 QP/Q/DP/D/DL/SEIM_D16Alt6NVCC_EIM0
S50HDA_SYNC / I2S2_LRCK--
S51HDA_SDO / I2S2_SDOUT--
S52HDA_SDI / I2S2_SDIN--
S53HDA_CK / I2S2_CK--
S54SATA_ACT#Out-CMOS/3.3Vi.MX6 QP/Q/DP/D/DL/SDISP0_DAT23Alt5NVCC_LCD
S55USB5_EN_OC#--
S56ESPI_IO_2--
S57ESPI_IO_3--
S58ESPI_RESET#Out-CMOS/1.8VBMCPC4--
S59USB5+--
S60USB5---
S61GND--
S62USB3_SSTX+--
S63USB3_SSTX---
S64GND--
S65USB3_SSRX+--
S66USB3_SSRX---
S67GND--
S68USB3+Bi-Dir-USBLAN9514-JZXUSBDP4--
S69USB3-Bi-Dir-USBLAN9514-JZXUSBDM4--
S70GND--
S71USB2_SSTX+--
S72USB2_SSTX---
S73GND--
S74USB2_SSRX+--
S75USB2_SSRX---
S76PCIE_B_RST#--
S77PCIE_C_RST#--
S78PCIE_C_RX+ / SERDES_2_RX+--
S79PCIE_C_RX- / SERDES_2_RX---
S80GND--
S81PCIE_C_TX+ / SERDES_2_TX+--
S82PCIE_C_TX- / SERDES_2_TX---
S83GND--
S84PCIE_B_REFCK+--
S85PCIE_B_REFCK---
S86GND--
S87PCIE_B_RX+--
S88PCIE_B_RX---
S89GND--
S90PCIE_B_TX+--
S91PCIE_B_TX---
S92GND--
S93DP0_LANE0+--
S94DP0_LANE0---
S95DP0_AUX_SEL--
S96DP0_LANE1+--
S97DP0_LANE1---
S98DP0_HPD--
S99DP0_LANE2+--
S100DP0_LANE2---
S101GND--
S102DP0_LANE3+--
S103DP0_LANE3---
S104USB3_OTG_ID--
S105DP0_AUX+--
S106DP0_AUX---
S107LCD1_BKLT_EN--
S108LVDS1_CK+ / eDP1_AUX+ / DSI1_CLK+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_CLK_P-NVCC_LVDS_2P5
S109LVDS1_CK- / eDP1_AUX- / DSI1_CLK-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_CLK_N-NVCC_LVDS_2P5
S110GND--
S111LVDS1_0+ / eDP1_TX0+ / DSI1_D0+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX0_P-NVCC_LVDS_2P5
S112LVDS1_0- / eDP1_TX0- / DSI1_D0-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX0_N-NVCC_LVDS_2P5
S113eDP1_HPD / DSI1_TE--
S114LVDS1_1+ / eDP1_TX1+ / DSI1_D1+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX1_P-NVCC_LVDS_2P5
S115LVDS1_1- / eDP1_TX1- / DSI1_D1-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX1_N-NVCC_LVDS_2P5
S116LCD1_VDD_EN--
S117LVDS1_2+ / eDP1_TX2+ / DSI1_D2+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX2_P-NVCC_LVDS_2P5
S118LVDS1_2- / eDP1_TX2- / DSI1_D2-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX2_N-NVCC_LVDS_2P5
S119GND--
S120LVDS1_3+ / eDP1_TX3+ / DSI1_D3+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX3_P-NVCC_LVDS_2P5
S121LVDS1_3- / eDP1_TX3- / DSI1_D3-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS1_TX3_N-NVCC_LVDS_2P5
S122LCD1_BKLT_PWM--
S123GPIO13--
S124GND--
S125LVDS0_0+ / eDP0_TX0+ / DSIO_D0+Outserial-0RLVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX0_P-NVCC_LVDS_2P5
S126LVDS0_0- / eDP0_TX0- / DSIO_D0-Outserial-0RLVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX0_N-NVCC_LVDS_2P5
S127LCD0_BKLT_ENOutserial-0RCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_D31Alt5NVCC_EIM0
S128LVDS0_1+ / eDP0_TX1+ / DSIO_D1+Outserial-0RLVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX1_P-NVCC_LVDS_2P5
S129LVDS0_1- / eDP0_TX1- / DSIO_D1-Outserial-0RLVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX1_N-NVCC_LVDS_2P5
S130GND--
S131LVDS0_2+ / eDP0_TX2+ / DSIO_D2+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX2_P-NVCC_LVDS_2P5
S132LVDS0_2- / eDP0_TX2- / DSIO_D2-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX2_N-NVCC_LVDS_2P5
S133LCD0_VDD_ENOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SENET_TXD0Alt5NVCC_ENET
S134LVDS0_CK+ / eDP0_AUX+ / DSIO_CLK+Outserial-0RLVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_CLK_P-NVCC_LVDS_2P5
S135LVDS0_CK- / eDP0_AUX- / DSIO_CLK-Outserial-0RLVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_CLK_N-NVCC_LVDS_2P5
S136GND--
S137LVDS0_3+ / eDP0_TX3+ / DSIO_D3+Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX3_P-NVCC_LVDS_2P5
S138LVDS0_3- / eDP0_TX3- / DSIO_D3-Out-LVDSi.MX6 QP/Q/DP/D/DL/SLVDS0_TX3_N-NVCC_LVDS_2P5
S139I2C_LCD_CKOutPU-1KI2C2i.MX6 QP/Q/DP/D/DL/SEIM_EB2Alt6NVCC_EIM0
S140I2C_LCD_DATBi-DirPU-1KI2C2i.MX6 QP/Q/DP/D/DL/SEIM_D16Alt6NVCC_EIM0
S141LCD0_BKLT_PWMOut-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SGPIO_9Alt4NVCC_GPIO
S142GPIO12In-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SDISPO_DAT11Alt5NVCC_LCD
S143GND--
S144eDP0_HPD / DSIO_TE--
S145WDT_TIME_OUT#OutPD-100KCMOS/1.8VBMCPC7--
S146PCIE_WAKE#In-CMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SCSI0_DATA_ENAlt5NVCC_CSI
S147VDD_RTCPWR--
S148LID#InPU-4.7KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SGPIO_7Alt5NVCC_GPIO
S149SLEEP#InPU-4.7KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SNANDF_D7Alt5NVCC_NANDF
S150VIN_PWR_BAD#InPU-10KCMOS/1.8VBMCPB7--
S151CHARGING#OutPU-68KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SEIM_D23Alt5NVCC_EIM0
S152CHARGER_PRSNT#OutPU-100KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SNANDF_D6Alt5NVCC_NANDF
S153CARRIER_STBY#Out-CMOS/1.8VBMCPB1--
S154CARRIER_PWR_ON_B (BMC)Out-CMOS/1.8VBMCPB6--
S155FORCE_RECOV_BInPU-4.7KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SBOOT_MODE0/1Alt0VDD_SNVS_IN
S156BATLOW_BOutPU-68KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SNANDF_RB0Alt5NVCC_NANDF
S157TEST_BInPU-4.7KCMOS/1.8Vi.MX6 QP/Q/DP/D/DL/SGPIO_8Alt5NVCC_GPIO
S158GND--
# 5. Software Support # 5.1.1 Uboot / Yocto Goto : https://github.com/adlink Yocto source-code and compiling instructions are available # 5.1.2 Ubuntu Build instruction from source, are available on Github # 5.1.3 Android Goto : https://github.com/adlink Android source-code and compiling instructions are available ![Search or jump to...\nPull requests Issues Marketplace Explore\nADLINK Technology Inc.\nhttps://www.adlinktech.com/en/index.aspx\nRepositories 5 Packages People 2 Teams Settings\nPinned repositories Customize pinned repositories\nmeta-adlink-x86-64bit\nSingle Yocto layer for all Intel x86 64-bit based\nComputer on Modules (COM Express, SMARC, Q7,\nETX)\nShell ★1 ★2\nmeta-adlink-nxp\nSingle Yocto layer for iMX6 & iMX8M based\nComputer on Modules. (SMARC)\nBitBake ★1\nmeta-adlink-rockchip\nmeta-adlink-sema\nSEMA layer for Yocto\nC ★1\nbios-utility\nProvide the utility of AMI BIOS setup menu\nconfiguration ★2](.smarc-lec-imx6r2-user-s-guide-final/4e7eeaa88872ff9c8117d4226a0e219ee8855b0eddd43b191a5f9817e1eb422e.jpg) # 6. Mechanical ![Module Primary (Top) Side\n4X Ø6\n4X Ø2.70\nTHROUGH\n78\n82\n50\n46\n12\n7.70\n6.20\n3.30\n3.10\n0\n1.25 PIN P1\n74 PINS\nP1 - P74\n82 PINS\nP75 - P156\n39](.smarc-lec-imx6r2-user-s-guide-final/67bdf04e7e1c7ab5161339b772bf306919b64de1b691642435346c6c5374105b.jpg) ![1.00 PIN S1\n75 PINS\nS1- S75\n83 PINS\nS76- S158\n110\n542\n540\nModule Primary (Bottom) Side](.smarc-lec-imx6r2-user-s-guide-final/3e1f8bfaee0cef1229b9229840545a9f1d7f4c13abb021a0b3c61a92cd7f2a0b.jpg) ![FULLRAD\n73X0.50\n81X0.50\n156X0.35\n(3.30)\nP74\nP75\n3.10 TYP\n1.00\n1.25\n1.25\nDETAILA\nTOP SIDE](.smarc-lec-imx6r2-user-s-guide-final/be063ea894cae51c48add7d5a8e0869fc49eea1068dd1e991fb0e380a9df7eee.jpg) ![1.70\n(6.20)\n(1.50)\n2X R0.50\nDETAILD\nNOTCH. 2 PLACES](.smarc-lec-imx6r2-user-s-guide-final/d611748e80ec793c74250785397dd573122cc529bf2bad52ebefb648134fae3e.jpg) ![P74\nP75\nTOP SIDE\n0.25\nS76\nBOTTOM SIDE\nPIN ALIGNMENTDETAIL](.smarc-lec-imx6r2-user-s-guide-final/a0ac3778303dd5cc30106dd6330cb3a970d7d928a4198fa79e524e2f9aae69a9.jpg) ![74X0.50\n3.10 TYP\nS75\nS76\n1\n1\n82X0.50\n158X0.35\nDETAILB\nBOTTOM SIDE](.smarc-lec-imx6r2-user-s-guide-final/382e8495a9316f9c07f4255af3ad4d080d8c78accd695c99c861a408978a19da.jpg) ![This is a black and white technical line drawing labeled 'CHAMFEREDGE DETAIL' at the bottom. It depicts a cross-section of a slot or groove with the following dimensions:\n- A top dimension line indicates a width of '1.20±0.1'.\n- A vertical dimension line on the left indicates a depth of '0.18' for the upper straight section.\n- An angled line on the right indicates a slope of '45°'.](.smarc-lec-imx6r2-user-s-guide-final/f9b258f8e059e437a4d3526b572179771d88ccb341aa36ebcddc38a6ed3b3dbe.jpg) ![3.00 MAX\nCOMPONENT HEIGHT\n(TOP SIDB)\n1.30 MAX\nCOMPONENT HEIGHT\n(BOTTOM SIDB)](.smarc-lec-imx6r2-user-s-guide-final/4c149ac1fb15436b4fde47ff979bda034174b274b8502833e9e2356b32d79016.jpg) # 7. Thermal Solutions 7.1.1 Heatsink : THS ![This image is a technical engineering drawing of a heatsink, presented in four distinct views.\n\n* **Top Left (Side Profile):** A cross-sectional view showing the fins. Vertical dimension lines indicate a total height of **12** and a base thickness of **3**.\n* **Top Right (Isometric):** A 3D perspective view showing the rectangular plate, four corner mounting holes, a central square recess, and fins running along one edge.\n* **Bottom Left (Back View):** A plan view of the flat side. Horizontal dimension **74** indicates width, and vertical dimension **34** indicates height. Smaller dimensions of **4** indicate the distance from the edges to the mounting holes. A square cutout is visible near the bottom center, and a notch is at the top left.\n* **Bottom Right (Front/Fin View):** A view of the finned face. Horizontal dimension **82** indicates width, and vertical dimension **42** indicates height. A callout line points to a mounting hole with the text **ø2.7mm x 4pcs**.](.smarc-lec-imx6r2-user-s-guide-final/1266cb644c75b95aa3285e83d12da359efd23145bcdce66449f9f3e5884e1608.jpg) 7.1.2 Heatspreader : HTS ![The image displays technical engineering drawings for a component labeled **2 Heatsreader : HTS** in red text. It features four distinct views with dimensions and annotations:\n\n* **Top Right (Isometric View):** Shows the 3D shape of the heatsink with a central square recess and four corner mounting posts. A leader line points to the threads with the text '**M3 x 4pcs**'.\n* **Top Left (Side Profile):** Shows the thickness profile with vertical dimensions of '**6**' and '**3**'. An angle of '**90°**' is indicated at the corner edge.\n* **Bottom Left (Front View):** Labeled '**THS**'. It shows the layout of mounting holes and a central square cutout with dimensions including widths of '**74**' and '**68**', vertical distances of '**34**', '**24**', and '**9**', and horizontal offsets of '**4**' and '**14**'.\n* **Bottom Right (Side View):** Shows a side profile with dimensions of width '**82**' and height '**42**'. A leader line points to the mounting holes with the text '**ø2.7mm x 4pcs**'.](.smarc-lec-imx6r2-user-s-guide-final/b15f0240e48e657c1b9d325a30029c11bb5930d28053fcee0a72f865e9370b65.jpg)
HTS-sIMX6R2-SDLHeatspreader for LEC-iMXR2 solo/DualliteTHS-sIMX6R2-SDLLow profile heatsink for LEC-iMX6R2 Solo/DualLite
HTS-sIMX6R2-DQPHeatspreader for LEC-iMX8R2 Dual/QuadTHS-sIMX6R2-DQPLow profile heatsink for LEC-iMX6R2 with Dual/Quad
[🔗 Link to the original document](.smarc-lec-imx6r2-user-s-guide-final/smarc-lec-imx6r2-user-s-guide-final.pdf)