# LEC-IMX8M Plus User’s Guide NXP ![Close-up of a blue printed circuit board with integrated circuits and gold connectors (no readable text or symbols)](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/900ccf4a2b0ec207dad0fe7908be8c8a889f40b29dd1304a281fe9a53a048d81.jpg) Revision History
RevisionDescriptionDateAuthor
1.0Initial release2023-04-20CC
1.1I2C pin info corrected2023-06-14CC
1.2Pin-to-controller mapping updated2024-06-06CC
1.3Thermal solution illustration updated2024-10-23CC
1.4Pin-to-controller mapping updated2024-11-28AL
1.5Video, extension busses, and system storage updated2025-04-09AL
1.6Pinout and signal descriptions updated2025-07-18AL
1.7Pinout and signal descriptions updated2025-10-30AL
1.8Specifications updated2025-11-04AL
# Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![The image displays a standard yellow triangular warning sign with a thick black border. Centered inside the triangle is a large black exclamation mark. The sign is set against a white background, with black vertical bars visible on the far left and right edges.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/781a2c65ec395baa014ed71141e816faa3939145fa8a8d2de4e628b16877b598.jpg) California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. ![The image features a black and white graphic. The upper section displays a line drawing of a wheeled trash bin with a lid, which is crossed out by a large 'X'. Below this symbol is a solid black rectangular bar.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/4d6de1072a47543347c99c73d39debfd689ed2a270853a8c8e3c1056e1c7a5e0.jpg) # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. # Copyright © 2025 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: • Keep equipment away from water or liquid sources; • Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![The image displays a simple icon resembling a document or memo pad. It features a thick red outline with a folded bottom-right corner. Inside the white background, there are two horizontal red lines centered within the upper portion of the shape. There is no text in the image.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/136c347810abfdc4ad8faae31c69e6921d75af1c52c789fa589663ab034865b7.jpg) Note: This information adds clarity or specifics to text and illustrations. ![The image displays a yellow triangular warning sign containing a white exclamation mark in the center, set against a white background.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/11a63cf962337dd128291684711c961813d237ec8d61ac634e966b7314d8144f.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image shows a red triangular warning sign with a white exclamation point in the center.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/477f3eaa38863ff2a2dbb402950b3ecdf818f7a75ed3dc3174b8bd8e528d833e.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. # Getting Service Ask an Expert: https://www.adlinktech.com/en/Askanexpert # ADLINK Technology, Inc. No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan Tel: +886-3-216-5088 Fax: +886-3-328-5706 Email: service@adlinktech.com # Ampro ADLINK Technology, Inc. 6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com # ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com # ADLINK Technology GmbH Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. # Table of Contents Revision History .. Preface . 1. Introduction .. . 9 1.1 LEC-iMX8M Plus... ..9 1.2 The SMARC Form Factor ... ..9 2. Specifications....... ..10 2.1 Core System.. ... 10 2.2 Video... .. 11 2.3 Audio ... ... 12 2.4 Dual Ethernet.. .. 12 2.5 1216 M.2 LGA Wi-Fi (optional) ... .. 13 2.6 Extension Busses.. ... 13 2.7 Board Controller... ... 14 2.8 System Storage .. ... 15 2.9 SEMA® Board Management Controller ... .. 15 2.10 Debug Header .... ... 15 2.11 Boot Modes .. ... 15 2.12 Power.... .... 16 2.13 Mechanical and Environmental . .. 16 3. Block Diagram .............. .17 4. Pinout and Signal Descriptions ....... ...18 4.1 Pin Summary ... .. 18 4.2 Signal Terminology Descriptions... . 22 4.3 Signal Description by Function.. .. 23 4.3.1 The First Display Interface . . 23 4.3.2 Second & Third Display Interfaces .. .. 26 4.3.3 MIPI Camera Support... .. 28 4.3.4 I2S (Audio) ... . 30 4.3.5 USB Ports.. . 31 4.3.6 PCIe Ports ... .. 33 4.3.7 SATA Ports... . 34 4.3.8 LAN Ports... .. 35 4.3.9 SDIO... . 37 4.3.10 SPI and ESPI... ... 38 4.4 General Purpose I2C. . 40 4.4.1 GPIO... . 41 4.4.2 UART... .... 42 4.4.3 CAN Bus ... .... 43 4.4.4 Miscellaneous ... .... 43 4.4.5 Power and System Management .. .... 44 4.4.6 DB30 Multipurpose Connector . .... 45 4.4.7 Boot Select... ....... 46 4.4.8 Power .. .... 47 4.5 SMARC Pin-to-controller Mapping... .. 48 5. Software Support .......... ..64 5.1 Uboot / Yocto ... . 64 5.2 Ubuntu .... . 64 5.3 Android... . 64 6. Mechanical.... ..65 7. Thermal Solutions... ..66 # List of Figures Figure 1 – Module function diagram... 17 Figure 2 – Module top/botom side pin numbering . .18 Figure 3 – Mechanical dimensions ......... ..65 Figure 4 – Thermal solutions... ...66 # 1. Introduction # 1.1 LEC-iMX8M Plus ADLINK LEC-iMX8MP is a SMARC module based on NXP iMX8M Plus (4-core Arm Cortex-A53) processor with an optional Neural Processing Unit (NPU) operating at up to 2.3 TOPS. It is the first SMARC Revision 2.1 module focusing on machine learning and vision, advanced multimedia, and industrial IoT, and with high reliability. The module also supports dual-image signal processors and 2x camera inputs for an effective vision system, and is especially suited for applications such as smart home, smart city, and industrial 4.0. # 1.2 The SMARC Form Factor The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor Computer on Module definition targeting applications that require low power and high performance at low costs. Typically under 6W, the modules often utilize ARM and other alternative low-power option CPUs, and are used in many familiar handheld devices, such as tablet computers and smart phones. Two module sizes are defined in SMARC: 82 mm x 50 mm and 82 mm x 80 mm. The module PCBs have 314 edge fingers that mate with a low-profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321 pin connector, with 7 pins used by the key). SMARC modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the module. Modules are used with application-specific carrier boards that implement other features such as audio codecs, touch controllers, wireless devices, etc. The modular approach allows scalability, faster time to market and upgradability while still maintaining low costs, low power, and small physical size. ![The image features the text 'SGeT' in a bold, sans-serif font. The letters 'S', 'G', and 'T' are yellow, while the lowercase letter 'e' is magenta and overlaps the bottom right section of the 'T'.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/6981cd7621788f66d0651238196ae9bec4874ab885043d50e01a5c76f52a2075.jpg) STANDARDIZATION GROUPFOR EMBEDDED TECHNOLOGIES SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html # 2. Specifications # 2.1 Core System # SoC NXP iMX8M Plus series, available with standard (0°C to 70°C) or extreme rugged (-40°C to 85°C) operating temperature • i.MX8M-plus Quad NPU 4x Arm Cortex-A53 at 1.6 to 1.8GHz, 1x Arm Cortex-M7, NPU, GPU, VPU Decode/Encode • i.MX8M-plus Quad 4x Arm Cortex-A53 at 1.6 to 1.8GHz, 1x Arm Cortex-M7, GPU, VPU Decode/Encode • i.MX8M-plus QuadLite 4x Arm Cortex-A53 at 1.6 to 1.8GHz, 1x Arm Cortex-M7 # L2 Cache 32KB I-cache, 32KB D-cache (A53), 512KB L2 Cache (ECC) # Memory 2/4/8GB LPDDR4 memory down (inline ECC) # Security CryptoAuthentication™ Device, Microchip ATECC608A (optional) • Cryptographic co-processor with secure hardware-based key storage • Protected storage for up to 16 Keys, certificates or data ECDH: FIPS SP800-56A Elliptic Curve Diffie-Hellman NIST standard P256 elliptic curve support • SHA-256 & HMAC hash including off-chip context save/restore • AES-128: encrypt/decrypt, galois field multiply for GCM • TPM 2.0 Device, ST Microelectronics ST33HTPH2X32AHD5 (optional) Compliant with Trusted Computing Group (TCG) Trusted Platform Module (TPM) Library specifications 2.0, Level 0, Revision 138 and TCG PC Client Specific TPM Platform Specifications 1.03 • Fault-tolerant firmware loader that keeps the TPM fully functional when the loading process is interrupted (self-recovery) • SP800-193 compliant for protection, detection, and recovery requirements # 2.2 Video LEC-iMX8M Plus supports 1K-capable HDMI 2.0a, a single/dual channel 24-bit LVDS, and a 4-lane DSI. # GPU Core Vivante GC7000UL 3D GC520L 2D # GPU/VPU Features GPU: 2 shaders, OpenGL ES 1.1, 2.9, 3.0, OpenCL 1.2, OpenGL 3.0, and Vulkan, up to 1080p FHD resolutions VPU : 1080p60 HEVC/H.265, H.264, VP9 Decoder | 1080p60 AVC/H.264/ HEVC/H.265 encoder # NPU (optional) 2.3 TOP/s Neural Network performance Keyword detect, noise reduction, beamforming, Speech recognition (i.e., Deep Speech 2), Image recognition (i.e. ResNet-50) # HDMI HDMI 2.0a supporting resolutions up to 4K at 60Hz # LVDS LVDS single/dual channel 24-bit at max. 1920×080 at 60Hz # MIPI DSI DSI 4 lanes at max. 1080p@60fps display output (multiplexed with LVDS signal) # Camera Support Compatible with MIPI Alliance Interface specification v2.1 2x MIPI-CSI2 camera inputs, 1x 4-lane and 1x 2-lane # 2.3 Audio Supports I2S audio codec interface, audio ADC and DAC (located on carrier) # 2.4 Dual Ethernet # Primary LAN Gigabit Ethernet controller with support for TSN in addition to Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588 Supports 10/100/1000Mbps data transfer rates, both full-duplex and half-duplex # Secondary LAN Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588 Supports 10/100/1000Mbps data transfer rates, both full-duplex and half-duplex # 2.5 1216 M.2 LGA Wi-Fi (optional) Optional Wi-Fi LGA module support In case of non-populated part, the footprint is still there and visible Only Azurewave AW-CM276NF has been validated during DVT but other M.2 LGA modules could also be compatible if they use the same standard interfaces, as listed below SDIO0 (main Wi-Fi interface) UART1 (main Bluetooth interface) PCM ( Bluetooth audio transfer interface ) ![The image displays a digital icon resembling a document or file. It features a red outline of a square with rounded corners and a folded top-right corner (a 'dog-ear'). Inside the red border, against a white background, are two horizontal red lines stacked vertically, resembling an equals sign.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/4df7c0f76a1f35796f5e367eba893d92e6682f176e68fe23cf25167be2f9eec6.jpg) \- Note : AW-CM276F has been pre-certified by Azurewave for several countries and regions, ADLINK can assist in final device certification if applicable. FCC ID: UAY-W8997-M1216 # 2.6 Extension Busses # PCIe 2x PCI Express Gen2 x1 interfaces or 1x PCI Express Gen3 (BOM option) # USB CT temp 2x USB 3.0/2.0, 3x USB 2.0, 1x USB2.0 OTG ER temp 1x USB 3.0, 1x USB2.0 OTG # UART 4x UART interface SER0, SER2 (Tx/Rx/CTS/RTS) and SER1, SER3(optional) (Tx/Rx) 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) Programmable baud rates up to 4 Mbps. # CAN bus 2x CAN2.0B only or mixed CAN2.0B and CAN FD mode, data bit rate of up to 8 Mbps # SPI 2x SPI # I2S I2S interface (codec on carrier) # I2C 5x I2C interfaces Supports 7-bit and 10-bit address mode Software programmable clock frequency: 100 kbit/s in Standard-mode, 400 kbit/s in Fast-mode • 1 Mbit/s in Fast-mode Plus # GPIO 14x GPIO with interrupt # 2.7 Board Controller BMC lite for power sequence SEMA BMC Error Code
Exception CodeError Code
0NOERROR
2NO_VIN
3NO_SDM_RESIN_N
4NO_SDM_RESIN_N
# 2.8 System Storage # SDIO 1x SDIO (4-bit) compatible up to version 3.0. # eMMC Soldered on module 16GB to 256GB (build option), available in either standard or -40 to 85o C temperature range Compatible with eMMC specification 5.1 # 2.9 SEMA® Board Management Controller Voltage/current monitoring, boot configuration, logistics and forensic information, flat panel control, watchdog timer # 2.10 Debug Header 30-pin multipurpose flat cable connector for use with optional DB-30 debug module Provides JTAG, BMC access; UART, power test points; diagnostic LEDs, Power, Reset, Boot configuration # 2.11 Boot Modes eMMC and SD card boot modes are supported # 2.12 Power # Supply Voltage 4.75V – 5.25V # 2.13 Mechanical and Environmental # Form Factor SGET SMARC Specifications v2.1 # Dimension SMARC small size module, 82mm x 50mm # Operating Temperature Standard: 0°C to 60°C Rugged: -40°C to 85°C (optional) # Humidity 5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # 3. Block Diagram ![The diagram illustrates the signal flow for an **NXP iMX 8M Plus** processor (central pink block).\n\n**Left Column (Signal List):**\nThe left side lists various interface signals: LVDS0 / DSIO, LVDS1, HDMI, CSI0, CSI1, USB0, USB1, USB2, USB3, USB4, USB5, GbE0, GbE1, PCIeA, PCIeB, CAN0, CAN1, SPI0, SPI1, UART0, UART1, UART2, I2S0, SDIO, I2C_PM, I2C_GP, I2C_LCD, I2C_CAM0, I2C_CAM1, and GPIO.\n\n**Intermediary Blocks & Connections:**\n* **MIPI MUX:** Connects LVDS0 / DSIO and LVDS1 (left) to the LVDS0, DSIO, and LVDS1 pins on the NXP chip.\n* **USB HUB:** Labeled 'USB HUB 2x USB 3.0/2.0 3x USB 2.0'. It connects USB0, USB1, and USB2 (left) to the USB1 2.0 (OTG) and USB2 3.0 (Host) pins on the NXP chip.\n* **LAN PHY:** Two blocks connect GbE0 to RGMII0 and GbE1 to RGMII1.\n* **PCIe Switch:** Connects PCIeA and PCIeB (left) to the 1x PCIe x1 pin on the NXP chip.\n* **PMIC:** Connects to I2C1, I2C2, and I2C3. It receives inputs from I2C_PM and I2C_GP.\n* **GPIO Expander1, GPIO Expander2, LITE BMC:** Connected to the GPIO signal and the I2C5/I2C6 lines.\n\n**NXP iMX 8M Plus Pins (Right side of central block):**\nDirect connections include HDMI (to HDMI 2.0a), CSI (to MIPI CSI 2-lanes and 4-lanes), CAN0/CAN1, SPI0/SPI1 (to ECSPI1/ECSPI2), UART0/1/2 (to UART2/3/4), and I2S0 (to I2S0).\n\n**External Components (Rightmost column):**\n* **DRAM** connects to **LPDDR4 x32**.\n* **SDHC3** connects to **eMMC 5.1**.\n* **UART1, SDIO0, PCM** connect to **Wi-Fi/BT**.\n* A **30-pin debug** block is connected via a line.\n\n**Bottom Components:**\nAt the bottom, blocks for **TPM**, **Crypto Auth. ATECC608A**, **RTC**, and **PCIe CLK** are connected near the I2C5 and I2C6 lines.\n\n**Text Note:**\nBottom right text reads: 'USB configuration for ER parts USB0 USB2.0/OTG USB2 USB3.0 No USB HUB'.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/09ec02486797fb24163d944a2d852e433f4ede90f2d0dcd7acb690f75757bd9d.jpg) Figure 1 – Module function diagram # 4. Pinout and Signal Descriptions # 4.1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1. Those signals not supported on LEC-iMX8M plus are strikethrough STRIKETHROUGH ![Top Side\nP1 P74 P75 P156\nKey](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/92d3271a072079ef01eaf442c49b3e8d42bbbeccd72201fd21c3ad25198c2083.jpg) ![Bottom Side\nS156 S76 S75 S1 Key](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/88ebfc704dfb84697e42a7872121618f5ea963fb872110de671c2d2fc85bdf49.jpg) Figure 2 – Module top/botom side pin numbering
P-PinPrimary (Top) Side
P1SMB_ALERT_1V8#
P2GND
P3CSI1_CK+
P4CSI1_CK-
P5GBE1_SDP
P6GBE0_SDP
P7CSI1_RX0+
P8CSI1_RX0-
P9GND
P10CSI1_RX1+
P11CSI1_RX1-
P12GND
P13CSI1_RX2+
P14CSI1_RX2-
P15GND
P16CSI1_RX3+
P17CSI1_RX3-
P18GND
P19GBE0_MDI3-
P20GBE0_MDI3+
P21GBE0_LINK100#
P22GBE0_LINK1000#
P23GBE0_MDI2-
P24GBE0_MDI2+
P25GBE0_LINK_ACT#
P26GBE0_MDI1-
P27GBE0_MDI1+
P28GBE0_CTREF
P29GBE0_MDIO-
P30GBE0_MDIO+
P31SPI0_CS1-
P32GND
P33SDIO_WP
P34SDIO_CMD
S-PinSecondary (Bottom) Side
S1CSI1_TX+ / I2C_CAM1_CK
S2CSI1_TX- / I2C_CAM1_DAT
S3GND
S4RSVD
S5CSI0_TX- / I2C_CAM0_CK
S6CAM_MCK
S7CSI0_TX+ / I2C_CAM0_DAT
S8CSI0_CK+
S9CSI0_CK-
S10GND
S11CSI0_RX0+
S12CSI0_RX0-
S13GND
S14CSI0_RX1+
S15CSI0_RX1-
S16GND
S17GBE1_MDIO+
S18GBE1_MDIO-
S19GBE1_LINK100#
S20GBE1_MDI1+
S21GBE1_MDI1-
S22GBE1_LINK1000#
S23GBE1_MDI2+
S24GBE1_MDI2-
S25GND
S26GBE1_MDI3+
S27GBE1_MDI3-
S28GBE1_CTREF
S29PCIE_D_TX+ / SERDES 1_TX+
S30PCIE_D_TX- / SERDES 1_TX-
S31GBE1_LINK_ACT#
S32PCIE_D_RX+ / SERDES 1_RX+
S33PCIE_D_RX- / SERDES 1_RX-
S34GND
S35USB4+
P-PinPrimary (Top) Side
P35SDIO_CD#
P36SDIO_CK
P37SDIO_PWR_EN
P38GND
P39SDIO_D0
P40SDIO_D1
P41SDIO_D2
P42SDIO_D3
P43SPI0_CS0#
P44SPI0_CK
P45SPI0_DIN
P46SPI0_DO
P47GND
P48SATA_TX+
P49SATA_TX-
P50GND
P51SATA_RX+
P52SATA_RX-
P53GND
P54ESPI_CS0# / SPI1_CS0#
P55ESPI_CS1# / SPI1_CS1#
P56ESPI_CK / SPI1_CK
P57ESPI_IO_1 / SPI1_DIN
P58ESPI_IO_0 / SPI1_DO
P59GND
P60USB0+
P61USB0-
P62USB0_EN_OC#
P63USB0_VBUS_DET
P64USB0_OTG_ID
P65USB1+
P66USB1-
P67USB1_EN_OC#
P68GND
P69USB2+
S-PinSecondary (Bottom) Side
S36USB4-
S37USB3_VBUS_DET
S38AUDIO_MCK
S39I2S0_LRCK
S40I2S0_SDOUT
S41I2S0_SDIN
S42I2S0_CK
S43ESPI_ALERT0#
S44ESPI_ALERT1#
S45MDIO_CLK
S46MDIO_DAT
S47GND
S48I2C_GP_CK
S49I2C_GP_DAT
S50HDA_SYNC / I2S2_LRCK
S51HDA_SDO / I2S2_SDOUT
S52HDA_SDI / I2S2_SDIN
S53HDA_CK / I2S2_CK
S54SATA_ACT#
S55USB5_EN_OC
S56ESPI_IO_2
S57ESPI_IO_3
S58ESPI_RESET#
S59USB5+
S60USB5-
S61GND
S62USB3_SSTX+
S63USB3_SSTX-
S64GND
S65USB3_SSRX+
S66USB3_SSRX-
S67GND
S68USB3+
S69USB3-
S70GND
P-PinPrimary (Top) Side
P70USB2-
P71USB2_EN_OC#
P72RSVD
P73RSVD
P74USB3_EN_OC#
Key
P75PCIE_A_RST#
P76USB4_EN_OC#
P77PCIE_B_CKREQ#
P78PCIE_A_CKREQ#
P79GND
P80PCIE_C_REFCK+
P81PCIE_C_REFCK-
P82GND
P83PCIE_A_REFCK+
P84PCIE_A_REFCK-
P85GND
P86PCIE_A_RX+
P87PCIE_A_RX-
P88GND
P89PCIE_A_TX+
P90PCIE_A_TX-
P91GND
P92HDMI_D2+ / DP1_LANE0+
P93HDMI_D2- / DP1_LANE0-
P94GND
P95HDMI_D1+ / DP1_LANE1+
P96HDMI_D1- / DP1_LANE1-
P97GND
P98HDMI_D0+ / DP1_LANE2+
P99HDMI_D0- / DP1_LANE2-
P100GND
P101HDMI_CK+ / DP1_LANE3+
S-PinSecondary (Bottom) Side
S71USB2_SSTX+
S72USB2_SSTX-
S73GND
S74USB2_SSRX+
S75USB2_SSRX-
Key
S76PCIE_B_RST#
S77PCIE_C_RST#
S78PCIE_C_RX+/SERDES_2_RX+
S79PCIE_C_RX-/SERDES_2_RX-
S80GND
S81PCIE_C_TX+/SERDES_2_TX+
S82PCIE_C_TX-/SERDES_2_TX-
S83GND
S84PCIE_B_REFCK+
S85PCIE_B_REFCK-
S86GND
S87PCIE_B_RX+
S88PCIE_B_RX-
S89GND
S90PCIE_B_TX+
S91PCIE_B_TX-
S92GND
S93DPO_LANE0+
S94DPO_LANE0-
S95DPO_AUX_SEL
S96DPO_LANE1+
S97DPO_LANE1-
S98DPO_HPD
S99DPO_LANE2+
S100DPO_LANE2-
S101GND
S102DPO_LANE3+
P-PinPrimary (Top) Side
P102HDMI_CK- / DP1_LANE3-
P103GND
P104HDMI_HPD / DP1_HPD
P105HDMI_CTRL_CK / DP1_AUX+
P106HDMI_CTRL_DAT / DP1_AUX-
P107DP1_AUX_SEL
P108GPIO0 / CAM0_PWR#
P109GPIO1 / CAM1_PWR#
P110GPIO2 / CAM0_RST#
P111GPIO3 / CAM1_RST#
P112GPIO4 / HDA_RST#
P113GPIO5 / PWM_OUT
P114GPIO6 / TACHIN
P115GPIO7
P116GPIO8
P117GPIO9
P118GPIO10
P119GPIO11
P120GND
P121I2C_PM_CK
P122I2C_PM_DAT
P123BOOT_SEL0#
P124BOOT_SEL1#
P125BOOT_SEL2#
P126RESET_OUT#
P127RESET_IN#
P128POWER_BTN#
P129SERO_TX
P130SERO_RX
P131SERO_RTS#
P132SERO_CTS#
P133GND
P134SER1_TX
P135SER1_RX
P136SER2_TX
S-PinSecondary (Bottom) Side
S103DP0_LANE3-
S104USB3_OTG_ID
S105DP0_AUX+
S106DP0_AUX-
S107LCD1_BKLT_EN
S108LVDS1_CK+/eDP1_AUX+/DSI1_CLK+
S109LVDS1_CK-/ eDP1_AUX-/DSI1_CLK-
S110GND
S111LVDS1_0+/ eDP1_TX0+/DSI1_D0+
S112LVDS1_0-/ eDP1_TX0-/DSI1_D0-
S113eDP1_HPD/DSI1_TE
S114LVDS1_1+/ eDP1_TX1+/DSI1_D1+
S115LVDS1_1-/ eDP1_TX1-/DSI1_D1-
S116LCD1_VDD_EN
S117LVDS1_2+/ eDP1_TX2+/DSI1_D2+
S118LVDS1_2-/ eDP1_TX2-/DSI1_D2-
S119GND
S120LVDS1_3+/ eDP1_TX3+/DSI1_D3+
S121LVDS1_3-/ eDP1_TX3-/DSI1_D3-
S122LCD1_BKLT_PWM
S123GPIO13
S124GND
S125LVDS0_0+/ eDP0_TX0+/DSI0_D0+
S126LVDS0_0-/ eDP0_TX0-/DSI0_D0-
S127LCD0_BKLT_EN
S128LVDS0_1+/ eDP0_TX1+/DSI0_D1+
S129LVDS0_1-/ eDP0_TX1-/DSI0_D1-
S130GND
S131LVDS0_2+/eDP0_TX2+/DSI0_D2+
S132LVDS0_2-/ eDP0_TX2-/DSI0_D2-
S133LCD0_VDD_EN
S134LVDS0_CK+/eDP0_AUX/DSI0_CLK+
S135LVDS0_CK-/eDP0_AUX-/DSI0_CLK-
S136GND
S137LVDS0_3+/ eDP0_TX3+/DSI0_D3+
P-PinPrimary (Top) Side
P137SER2_RX
P138SER2_RTS#
P139SER2_CTS#
P140SER3_TX
P141SER3_RX
P142GND
P143CAN0_TX
P144CAN0_RX
P145CAN1_TX
P146CAN1_RX
P147VDD_IN
S-PinSecondary (Bottom) Side
S138LVDS0_3- / eDP0_TX3- / DSI0_D3-
S139I2C_LCD_CK
S140I2C_LCD_DAT
S141LCD0_BKLT_PWM
S142GPIO12
S143GND
S144eDP0_HPD / DSI0_TE
S145WDT_TIME_OUT#
S146PCIE_WAKE#
S147VDD_RTC
S148LID#
P-PinPrimary (Top) Side
P148VDD_IN
P149VDD_IN
P150VDD_IN
P151VDD_IN
P152VDD_IN
P153VDD_IN
P154VDD_IN
P155VDD_IN
P156VDD_IN
S-PinSecondary (Bottom) Side
S149SLEEP#
S150VIN_PWR_BAD#
S151CHARGING#
S152CHARGER_PRSNT#
S153CARRIER_STBY#
S154CARRIER_PWR_ON
S155FORCE_RECOV#
S156BATLOW#
S157TEST#
S158GND
![The image shows a red outline icon of a document with a folded top-right corner. Inside the white space, there are two horizontal red lines. There is no text.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/0426f258a7d24b47d5d4a2d27459b8b49dabefa57644a8b485684aae8718409d.jpg) Note: DSI0 is pin-shared with LVDS0 # 4.2 Signal Terminology Descriptions Meaning of the terms used for signal description tables. Signals described in the specification but not supported on the LEC-iMX8M Plus are marked with strikethrough STRIKETHROUGH
TermDescription
IInput to the module
OOutput from the module
O ODOpen drain output from the module
I ODOpen drain input to the module, with mandatory PU (pull up) on module
ODOpen drain
I/OBi-directional Input/Output
PUPU (pull-up) resistor on module
PDPD (pull-down) resistor on module
VDD_INMain power source from carrier to module
CMOSLogic input or output
GBE MDIDifferential analog signaling for Gigabit Media Dependent Interface
LVDS DPLow Voltage Differential Signal for DisplayPort interface
LVDS D-PHYLow Voltage Differential Signal for MIPI CSI-2 cameras and DSI displays
LVDS M-PHYLow Voltage Differential Signal for MIPI CSI-3 cameras
LVDS LCDLow Voltage Differential Signal for LCD displays
LVDS PCIELow Voltage Differential Signal for PCIe
LVDS SATALow Voltage Differential Signal for SATA
TMDS HDMITransition Minimized Differential Signal for HDMI displays
USBDC coupled differential signaling for traditional (non-Superspeed) USB signals
USB SSDifferential signal for SuperSpeed USB signals
USB VBUS 5V5V tolerant input for USB VBUS detection
3.3V3.3V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
1.8V1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
3.3Vsb3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
1.8Vsb1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
# 4.3 Signal Description by Function # 4.3.1 The First Display Interface The first display interface is a group of 30-pins that is split into channel 0 and channel 1. The SMARC specification allows support for dual channel LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display types such as DSI and eDP is also permitted. Below tables show which display ports are supported on this particular module.
Pin #LVDS NameMIPI DSI NameeDP Name
S125LVDS0_0+DSI0_D0+eDP0_TX0+
S126LVDS0_0-DSI0_D0-eDP0_TX0-
S128LVDS0_1+DSI0_D1+eDP0_TX1+
S129LVDS0_1 -DSI0_D1-eDP0_TX1-
S131LVDS0_2+DSI0_D2+eDP0_TX2+
S132LVDS0_2-DSI0_D2-eDP0_TX2-
S137LVDS0_3+DSI0_D3+eDP0_TX3+
S138LVDS0_3-DSI0_D3-eDP0_TX3-
S134LVDS0_CK+DSI0_CLK+eDP0_AUX+
S135LVDS0_CK-DSI0_CLK-eDP0_AUX-
S133LCD0_VDD_ENLCD0_VDD_ENLCD0_VDD_EN
S127LCD0_BKLT_ENLCD0_BKLT_ENLCD0_BKLT_EN
S141LCD0_BKLT_PWMLCD0_BKLT_PWMLCD0_BKLT_PWM
S144DSI0_TEeDP0_HPD
S139I2C_LCD_CKI2C_LCD_CKI2C_LCD_CK
S140I2C_LCD_DATI2C_LCD_DATI2C_LCD_DAT
Pin #LVDS NameMIPI DSI NameeDP Name
S111LVDS1_0+DSI1_D0+eDP1_TX0+
S112LVDS1_0-DSI1_D0-eDP1_TX0-
S114LVDS1_1+DSI1_D1+eDP1_TX1+
S115LVDS1_1 -DSI1_D1-eDP1_TX1-
S117LVDS1_2+DSI1_D2+eDP1_TX2+
S118LVDS1_2-DSI1_D2-eDP1_TX2-
S120LVDS1_3+DSI1_D3+eDP1_TX3+
S121LVDS1_3-DSI1_D3-eDP1_TX3-
S108LVDS1_CK+DSI1_CLK+eDP1_AUX+
S109LVDS1_CK-DSI1_CLK-eDP1_AUX-
S116LCD1_VDD_ENLCD1_VDD_ENLCD1_VDD_EN
S107LCD1_BKLT_ENLCD1_BKLT_ENLCD1_BKLT_EN
S122LCD1_BKLT_PWMLCD1_BKLT_PWMLCD1_BKLT_PWM
S113DSI1_TEeDP1_HPD
![The image features a red icon of a document with a folded top-right corner. Inside the outline, there are two horizontal red lines stacked vertically.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/45cb3a868cfc884958c8f0f3578d3aa5887622e2b833652bd1d3802f50025327.jpg) # Note: 1. LVDS0/LVDS1 are standard supported on the module. 2. DSI0 can be used but will disable the LVDS0 port, DSI1 is not supported. 4.3.1.1 LVDS0/LVDS1 mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
LVDS0_0+S125Primary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS0_0-S126
LVDS0_1+S128
LVDS0_1 -S129
LVDS0_2+S131
LVDS0_2-S132
LVDS0_3+S137
LVDS0_3-S138
LVDS0_CK+S134Primary LVDS channel differential pair clock linesO LVDS LCDRuntime
LVDS0_CK-S135
LCD0_VDD_ENS133Primary LVDS channel power enable, active highO CMOS1.8VRuntime
LCD0_BKLT_ENS127Primary LVDS channel backlight enable, active highO CMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary LVDS channel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
LVDS1_0+S111Secondary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS1_0-S112
LVDS1_1+S114
LVDS1_1 -S115
LVDS1_2+S117
LVDS1_2-S118
LVDS1_3+S120
LVDS1_3-S121
LVDS1_CK+S108Secondary LVDS channel differential pair clock lines.O LVDS LCDRuntime
LVDS1_CK-S109
LCD1_VDD_ENS116Secondary panel power enable, active highO CMOS1.8VRuntime
LCD1_BKLT_ENS107Secondary panel backlight enable, active highO CMOS1.8VRuntime
LCD1_BKLT_PWMS122Secondary panel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
4.3.1.2 DSI mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
DSI0_D0+S125Primary DSI panel differential pair data linesO LVDSD-PHYRuntimeBuild option
DSI0_D0-S126
DSI0_D1+S128
DSI0_D1-S129
DSI0_D2+S131
DSI0_D2-S132
DSI0_D3+S137
DSI0_D3-S138
DSI0_CLK+S134Primary DSI panel differential pair clock lines.O LVDSD-PHYRuntimeBuild option
DSI0_CLK-S135
LCD0_VDD_ENS133Primary panel power enable, active highOCMOS1.8VRuntime
LCD0_BKLT_ENS127Primary panel backlight enable, active highOCMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary panel brightness control through pulse width modulation (PWM)OCMOS1.8VRuntime
DSI0_TES144Primary DSI panel tearing effect signalICMOS1.8VRuntimePD 1M
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O ODCMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO ODCMOS1.8VRuntimePU 2k2
# 4.3.2 Second & Third Display Interfaces
Pin #HDMI signal namesDP++ signal names
P92HDMI_D2+DP1_LANE0+
P93HDMI_D2-DP1_LANE0-
P95HDMI_D1+DP1_LANE1+
P96HDMI_D1-DP1_LANE1-
P98HDMI_D0+DP1_LANE2+
P99HDMI_D0-DP1_LANE2-
P101HDMI_CK+DP1_LANE3+
P102HDMI_CK-DP1_LANE3-
S105HDMI_CTRL_CKDP1_AUX+
S106HDMI_CTRL_DATDP1_AUX-
P104HDMI_HPDDP1_HPD
P107-DP1_AUX_SEL
Pin #DP++ signal names
P92DPO_LANE0+
P93DPO_LANE0-
P95DPO_LANE1+
P96DPO_LANE1-
P98DPO_LANE2+
P99DPO_LANE2-
P101DPO_LANE3+
P102DPO_LANE3-
S105DPO_AUX+
S106DPO_AUX-
P104DPO_HPD
P107DPO_AUX_SEL
![The image shows a red outline icon of a document or page with a folded bottom-right corner. Inside the outline, two horizontal red lines are centered horizontally.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/ae95bc67c40783de51d2c0d4c4187025735eba072d4a5d5914f0ff065618a632.jpg) Note: DisplayPort is not supported on both second and third display interfaces # 4.3.2.1 HDMI
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
HDMI_D2+P92HDMI port, differential pair data linesO TMDS HDMIRuntime
HDMI_D2-P93
HDMI_D1+P95
HDMI_D1-P96
HDMI_D0+P98
HDMI_D0-P99
HDMI_CK+P101HDMI port, differential pair clock linesO TMDS HDMIRuntime
HDMI_CK-P102
HDMI_CTRL_CKP105I2C_CLK line dedicated to HDMIO OD COMS1.8VRuntimePU 100KLevel shifter FET and 5V PU resistor shall be placed between the module and the HDMI connector.
HDMI_CTRL_DATP106I2C_DAT line dedicated to HDMII/O OD COMS1.8VRuntimePU 100KLevel shifter FET and 5V PU resistor shall be placed between the module and the HDMI connector.
HDMI_HPDP104HDMI Hot plug active high detection signal that serves as an interrupt requestI CMOS1.8VRuntimePD 1MModule must tolerate high level in stand-by mode
# 4.3.3 MIPI Camera Support 4.3.3.1 MIPI CSI0
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CSI0_RX0+S11CSI0 differential input (point to point)I LVDS D-PHY / I LVDS M-PHYRuntime
CSI0_RX0-S12
CSI0_RX1+S14
CSI0_RX1-S15
CSI0_CK+S8CSI0 differential clock input (point to point)I LVDS D-PHYRuntime
CSI0_CK-S9
I2C_CAM0_DAT / CSIO_TX-S7I2C data for serial camera data support link or differential data laneI/O OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 uses I2C_CAM0_DAT MIPI-CSI 3.0 uses CSIO_TX-
I2C_CAM0_CK / CSIO_TX+S5I2C clock for serial camera data support link or differential data laneO OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 uses I2C_CAM0_CK MIPI-CSI 3.0 uses CSIO_TX+
CAM0_PWR# / GPIO0P108Camera 0 Power Enable, active low output.O CMOS1.8VRuntimeShared with GPIO0
CAM0_RST# / GPIO2P110Camera 0 Reset, active low outputO CMOS1.8VRuntimeShared with GPIO2
CAM_MCKS6Master clock outputO CMOS1.8VRuntimeThis signal is used by both CSIO and CSI1
4.3.3.2 MIPI CSI1 (Camera)
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CSI1_RX0+P7CSI1 differential input (point to point)I LVDS D-PHY / I LVDS M-PHYRuntime
CSI1_RX0-P8
CSI1_RX1+P10
CSI1_RX1-P11
CSI1_RX2+P13
CSI1_RX2-P14
CSI1_RX3+P16
CSI1_RX3-P17
CSI1_CK+P3CSI1 differential clock input (point to point)I LVDS D-PHYRuntime
CSI1_CK-P4
I2C_CAM1_DAT / CSI1_TX-S2I2C data for serial camera data support link or differential data laneI/O OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_DAT MIPI-CSI 3.0 mode uses CSI1_TX-
I2C_CAM1_CK / CSI1_TX+S1I2C clock for serial camera data support link or differential data laneO OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_CK MIPI-CSI 3.0 mode uses CSI1_TX+
CAM1_PWR# / GPIO1P109Camera 1 Power Enable, active low output.O CMOS1.8VRuntimeShared with GPIO1
CAM1_RST# / GPIO3P111Camera 1 Reset, active low outputO CMOS1.8VRuntimeShared with GPIO3
CAM_MCKS6Master clock outputO CMOS1.8VRuntimeThis signal is used by both CSI0 and CSI1
4.3.4 I2S (Audio)
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2S0_LRCKS39I2S0 Left & Right synchronization clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S0_SDOUTS40I2S0 Digital audio OutputO CMOS1.8VRuntime
I2S0_SDINS41I2S0 Digital audio InputI CMOS1.8VRuntime
I2S0_CKS42I2S0 Digital audio clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_LRCKS50I2S2 Left & Right synchronization clockI/O CMOS1.8VRuntime-Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_SDOUTS51I2S2 Digital audio OutputO CMOS1.8VRuntime--
I2S2_SDINS52I2S2 Digital audio InputI CMOS1.8VRuntime--
I2S2_CKS53I2S2 Digital audio clockI/O CMOS1.8VRuntime-Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
AUDIO_MCKS38Master clock output to I2S codec(s)O CMOS1.8VRuntime--
![The image displays a red outline icon resembling a document or page with the top right corner folded over. Inside the outline, there are two horizontal lines centered vertically, representing text. There is no text present in the image.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/98795d4199ed15a5a1d74b8d8ee34723c8fbd3c0c5284928d7f03f790bfbb106.jpg) Note: support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification 4.3.5 USB Ports
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
USB0+USB0-P60P61USB differential data pairs for port 0I/O USBUSBStandbyFrom SOC
USB0_EN_OC#P62USB over-current sense for port 0I/O OD CMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB0_VBUS_DETP63USB port 0 host power detection, when this port is used as a device.I USB VBUS 5VUSB VBUS 5VStandbyCan be connected to a USB client port VBUS pin
USB0_OTG_IDP64Input pin to announce OTG device insertion on USB 2.0 portI CMOS3.3Vsb / 3.3VStandby
USB1+USB1-P65P66USB differential data pairs for port 1I/O USBUSBStandbyFrom USB HUB
USB1_EN_OC#P67USB over-current sense for port 1I/O OD CMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB2+USB2-P69P70USB differential data pairs for port 2I/O USBUSBStandbyFrom USB HUB
USB2_SSRX+USB2_SSRX-S74S75Receive signal differential pairs for SuperSpeed on port 2I USB SSUSB SSStandby-
USB2_SSTX+USB2_SSTX-S71S72Transmit signal differential pairs for SuperSpeed on port 2O USB SSUSB SSStandby-
USB2_EN_OC#P71USB over-current sense for port 2I/O OD CMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB3+USB3-S68S69USB differential data pairs for port 3I/OUSBUSBStandbyFrom USB HUB
USB3_SSRX+USB3_SSRX-S65S66Receive signal differential pairs for SuperSpeed on port 3IUSB SSUSB SSStandby
USB3_SSTX+USB3_SSTX-S62S63Transmit signal differential pairs for SuperSpeed on port 3OUSB SSUSB SSStandby
USB3_EN_OC#P74USB over-current sense for port 3I/O OD CMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB3_VBUS_DETS37USB port 3 host power detection, when this port is used as a device.↑USB VBUS 5VUSB VBUS 5VStandby--
USB3_OTG_IDS104Input pin to announce OTG device insertion on USB 3.0 port↓CMOS3.3Vsb / 3.3VStandby--
USB4+USB4-S35S36USB differential data pairs for port 4I/OUSBUSBStandby
USB4_EN_OC#P76USB over-current sense for port 4I/O ODCMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
USB5+USB5-S59S60USB differential data pairs for port 5I/OUSBUSBStandby
USB5_EN_OC#S55USB over-current sense for port 5I/O ODCMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.
![The image displays a red icon resembling a document or page with a folded bottom-right corner. Inside the red outline, there are two horizontal red lines centered vertically. The interior of the shape is white.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/77599cc2cdef9447af4353b1d3e55806402d890a9b8308e400d125ff54036785.jpg) # Note: 1. USB0 is directly connected to the SoC. USB1/2/3/4/5 share bandwidth through a HUB. 2. Extreme rugged (-ER) parts have no USB hub populated. # 4.3.6 PCIe Ports The module supports 2x PCIe Gen 2.1 ports (PCIE\_A and PCIE\_B).
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
PCIE_A_TX+PCIE_A_TX-P89P90Differential PCIe link A transmit data pairO LVDSPCIERuntimeSeries AC coupled on module
PCIE_A_RX+PCIE_A_RX-P86P87Differential PCIe link A receive data pairI LVDSPCIERuntimeSeries AC coupled off module
PCIE_A_REFCK+PCIE_A_REFCK-P83P84Differential PCIe Link A reference clock outputO LVDSPCIERuntime
PCIE_A_RST#P75PCIe Port A reset outputOCMOS3.3VRuntime
PCIE_A_CKREQ#P78PCIe Port A clock requestIODCMOS3.3VRuntimePU >10KNo need for this signal because module provides onboard PCIe clock
PCIE_B_TX+PCIE_B_TX-S90S91Differential PCIe link B transmit data pairO LVDSPCIERuntimeSeries AC coupled on module
PCIE_B_RX+PCIE_B_RX-S87S88Differential PCIe link B receive data pairI LVDSPCIERuntimeSeries AC coupled off module
PCIE_B_REFCK+PCIE_B_REFCK-S84S85Differential PCIe Link B reference clock outputO LVDSPCIERuntime
PCIE_B_RST#S76PCIe Port B reset outputOCMOS3.3VRuntime
PCIE_B_CKREQ#P77PCIe Port B clock requestIODCMOS3.3VRuntimePU >10KNo need for this signal because module provides onboard PCIe clock
PCIE_C_TX+PCIE_C_TX-S81S82Differential PCIe link C transmit data pair-O LVDSPCIE-Runtime-Series AC coupled on module
PCIE_C_RX+PCIE_C_RX-S78S79Differential PCIe link C receive data pair-I LVDSPCIE-Runtime-Series AC coupled off module
PCIE_C_REFCK+PCIE_C_REFCK-P80P81Differential PCIe Link C reference clock output-O LVDSPCIE-Runtime--
PCIe_C_RST#S77PCIe Port C reset output-0 -CMOS3.3VRuntime--
PCIE_D_TX+PCIE_D_TX-S29S30Differential PCIe link D transmit data pair-O-LVDS-PCIE-Runtime-Series AC coupled on module
PCIE_D_RX+PCIE_D_RX-S32S33Differential PCIe link D receive data pair-I-LVDS-PCIE-Runtime-Series AC coupled off module
PCIE_WAKE#S146PCIe wake up interrupt to host – common to PCIe links A, B, C, DI ODCMOS3.3VRuntimePU 10k
![The image displays a red icon on a white background. The icon is shaped like a document or page with a folded bottom-right corner. Inside the document outline, there are two horizontal red lines stacked vertically, centered within the shape.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/405dac122011a8397340ce9be292e3fa7f3aa384ec6b99eb0b5be49fcd0015ae.jpg) Note: Module provides PCIe clock generators for PCIE\_A and PCIE\_B so no external clock source on the carrier is needed # 4.3.7 SATA Ports This design does not support SATA ports # 4.3.8 LAN Ports # 4.3.8.1 First LAN Port The first LAN port is derived from the SoC’s RGMII0 interface
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE0_MDI0+P30Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:GBE MDIStandbyTwisted pair signals for external transformer.
GBE0_MDI0-P29
GBE0_MDI1+P27
GBE0_MDI1-P26
GBE0_MDI2+P24
GBE0_MDI2-P23100010010
GBE0_MDI3+P20MDI[0]+/-B1_DA+/-TX+/-TX+/-
GBE0_MDI3-P19MDI[1]+/-B1_DB+/-RX+/-RX+/-
MDI[2]+/-B1_DC+/-
MDI[3]+/-B1_DD+/-
GBE0_LINK100#P21Link Speed Indication LED for GBE 0 100MbpsO OD CMOS3.3VStandbyShall be able to sink 24mA or more Carrier LED current
GBE0_LINK1000#P22Link Speed Indication LED for GBE 0 1000MbpsO OD CMOS3.3VStandbyShall be able to sink 24mA or more Carrier LED current
GBE0_LINK_ACT#P25Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on ActivityO OD CMOS3.3VStandbyShall be able to sink 24mA or more Carrier LED current
GBE0_CTREFP28Center-Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)Analog0 to 3.3V maxStandby--
GBE0_SDPP6IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VStandby
# 4.3.8.2 Second LAN Port The Second LAN port is derived from the SoC’s RGMII1interface
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE1_MDI0+S17Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:GBE MDIStandbyTwisted pair signals for external transformer.
GBE1_MDI0-S18
GBE1_MDI1+S20
GBE1_MDI1-S21
GBE1_MDI2+S23
GBE1_MDI2-S241000 100 10MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-
GBE1_MDI3+S26
GBE1_MDI3-S27
GBE1_LINK100#S19Link Speed Indication LED for GBE 1 100MbpsO OD CMOS3.3VStandbyShall be able to sink 24mA or more Carrier LED current
GBE1_LINK1000#S22Link Speed Indication LED for GBE 1 1000MbpsO OD CMOS3.3VStandbyShall be able to sink 24mA or more Carrier LED current
GBE1_LINK_ACT#S31Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on ActivityO OD CMOS3.3VStandbyShall be able to sink 24mA or more Carrier LED current
GBE1_CTREFS28Center-Tap reference voltage for Carrier board Ethernet magnetic `(if required by the Module GBE PHY)`Analog0 to 3.3V maxStandby
GBE1_SDPP5IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VStandby
4.3.9 SDIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SDIO_D0P39SDIO Data lines. These signals operate in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_D1P40
SDIO_D2P41
SDIO_D3P42
SDIO_WPP33SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CMDP34SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_CD#P35SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CKP36SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.O CMOS1.8V or 3.3VRuntime
SDIO_PWR_ENP37SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.O CMOS3.3VRuntimeshould be driven low in STB Mode by the module
# 4.3.10 SPI and ESPI 4.3.10.1 SPI0
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SPI0_CS0#P43SPI0 Master Chip Select 0O CMOS1.8VStandbyThis signal can be used to select carrier SPI as boot device
SPI0_CS1#P31SPI0 Master Chip Select 1O CMOS1.8VStandby
SPI0_CKP44SPI0 ClockO CMOS1.8VStandby
SPI0_DINP45SPI0 Master input / Slave outputI CMOS1.8VStandbyalso referred to as MISO
SPI0_DOP46SPI0 Master output / Slave inputO CMOS1.8VStandbyalso referred to as MOSI
SPI1_CS0#P54SPI1 Master Chip Select 0O CMOS1.8VStandby-See ESPI
SPI1_CS1#P55SPI1 Master Chip Select 1O CMOS1.8VStandby-See ESPI
SPI1_CKP56SPI1 ClockO CMOS1.8VStandby-See ESPI
SPI1_DINP57SPI1 Master input / Slave outputI CMOS1.8VStandby-See ESPI
SPI1_DOP58SPI1 Master output / Slave inputO CMOS1.8VStandby-See ESPI
![This image displays a red icon on a white background. The icon depicts a stylized document or piece of paper with a folded corner at the top right. Inside the red outline of the paper are two horizontal red bars representing lines of text.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/2d8dbf7dce450e6ba6dd821e70537a88634fb3b3c3d3d61a6ce93837300e1280.jpg) Note: SPI0/1 is free to use on the carrier. 4.3.10.2 ESPI
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
ESPI_CS0#P54ESPI1 Master Chip Select 0O CMOS1.8VStandby-
ESPI_CS1#P55ESPI1 Master Chip Select 1O CMOS1.8VStandby-
ESPI_CKP56ESPI Master Clock outputO CMOS1.8VStandby-
ESPI_RESET#S58ESPI ResetO CMOS1.8VStandby-Reset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves
ESPI_ALERT0#S43ESPI ALERTIOD CMOS1.8VStandby-This pin is used by eSPI slave to request service from eSPI.master.Alert# is an open drain output from the slave.This pin is optional for Single Master Single Slave configuration where I/O[1] can be used to signal the Alert event.
ESPI_ALERT1#S44
ESPI_IO_0P58ESPI Master Data Input / Output.-I/O CMOS1.8VStandby-ESPI_IO_0 can also be used as SPI1_DO (MOSI)ESPI_IO_1 can also be used as SPI1_DIN (MISO)In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI slave output (MISO).
ESPI_IO_1P57
ESPI_IO_2S56
ESPI_IO_3S57
![The image displays a simple, flat-style icon in red. It depicts a rectangular document or piece of paper with the top-right corner folded down. Inside the outline of the paper, two thick horizontal lines are centered, resembling lines of text.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/7df8794ac9dce1a17df79968e4b64ad2e3ba28e84d1733dfd7db09cb0406cb44.jpg) Note: On NXP i.MX8M Plus, part SPI is used # 4.4 General Purpose I2C The SMARC specification supports a total of 6 different I2C busses on its pinout. Most of these busses are designated for specific functions such as I2C for camera management, I2C for EDID on HDMI, LVDS panels or I2C for PMIC. Only one I2C bus is marked as General purpose
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2C_GP_DATS49General purpose I2C data signalI/O OD CMOS1.8VRuntimePU 2k2
I2C_GP_CKS48General purpose I2C clock signalO OD CMOS1.8VRuntimePU 2k2
Most of the other I2C busses are described in their designated function tables as opposed to a combined list. Below is an overview of all I2C busses and where to find them.
NamePin #DescriptionWhere to find
I2C_LCD_DATS140DDC data line used for flat panel detection and controlLVDS / DSI / eDP tables
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlLVDS / DSI / eDP tables
HDMI_CTRL_CKP105I2C_CLK line dedicated to HDMIHDMI table
HDMI_CTRL_DATP106I2C_DAT line dedicated to HDMIHDMI table
I2C_CAM0_DATS7I2C data for serial camera data support linkMIPI CSI table
I2C_CAM0_CKS5I2C clock for serial camera data support linkMIPI CSI table
I2C_CAM1_DATS2I2C data for serial camera data support linkMIPI CSI table
I2C_CAM1_CKS1I2C clock for serial camera data support linkMIPI CSI table
I2C_PM_DATP122Power management I2C bus DATA (SMBus for x86)Power and System Management
I2C_PM_CKP121Power management I2C bus CLK (SMBus for x86)Power and System Management
4.4.1 GPIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GPIO0 / CAM0_PWR#P108General purpose I/O pin 0.I/O CMOS1.8VRuntimePU 470K on the Module.Default use is GPIO0, alternative use is Camera 0 Power Enable - active low, through DTS
GPIO1 / CAM1_PWR#P109General purpose I/O pin 1.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS
GPIO2 / CAM0_RST#P110General purpose I/O pin 2.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO2, alternative use is Camera 0 Reset - active low, through DTS
GPIO3 / CAM1_RST#P111General purpose I/O pin 3.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS
GPIO4 / HDA_RST#P112General purpose I/O pin 4.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO5 / PWM_OUTP113General purpose I/O pin 5.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO6 / TACHINP114General purpose I/O pin 6.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO7P115General purpose I/O pin 7.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO8P116General purpose I/O pin 8.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO9P117General purpose I/O pin 9.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO10P118General purpose I/O pin 10.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO11P119General purpose I/O pin 11.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO12S142General purpose I/O pin 12I/O CMOS1.8VRuntimePU 470K on the Module
GPIO13S123General purpose I/O pin 13I/O CMOS1.8VRuntimePU 470K on the Module
4.4.2 UART
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SER0_TXP129Asynchronous serial data output port 0O CMOS1.8VRuntime
SER0_RXP130Asynchronous serial data input port 0I CMOS1.8VRuntimePU 100k
SER0_RTS#P131"Request to Send" handshake line for port 0O CMOS1.8VRuntime
SER0_CTS#P132"Clear to Send" handshake line for port 0I CMOS1.8VRuntimePU 100k
SER1_TXP134Asynchronous serial data output port 1O CMOS1.8VRuntime
SER1_RXP135Asynchronous serial data input port 1I CMOS1.8VRuntimePU 100k
SER2_TXP136Asynchronous serial data output port 2O CMOS1.8VRuntime--
SER2_RXP137Asynchronous serial data input port 2I CMOS1.8VRuntimePU 100k-
SER2_RTS#P138"Request to Send" handshake line for port 2O CMOS1.8VRuntime--
SER2_CTS#P139"Clear to Send" handshake line for port 2I CMOS1.8VRuntimePU 100k-
SER3_TXP140Asynchronous serial data output port 3O CMOS1.8VRuntime-
SER3_RXP141Asynchronous serial data input port 3I CMOS1.8VRuntime-
4.4.3 CAN Bus
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CAN0_TXP143CAN port 0 Transmit outputO CMOS1.8VRuntime
CAN0_RXP144CAN port 0 Receive inputI CMOS1.8VRuntime
CAN1_TXP145CAN port 1 Transmit outputO CMOS1.8VRuntime
CAN1_RXP146CAN port1 Receive inputI CMOS1.8VRuntime
4.4.4 Miscellaneous
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
TEST#S157Held low by Carrier to invoke Module vendor specific test function(s).I CMOS1.8VRuntimePU on Module. Driven by OD on CarrierModule must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation
WDT_TIME_OUT#S145Watch-Dog-Timer Output, low active.O CMOS1.8VRuntimeDriven only during runtime
4.4.5 Power and System Management
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BATLOW#S156Battery low indication to Module. Carrier to float the line in inactive state.I OD CMOS1.8VStandby / SleepPU 10KDriven by OD on Carrier. Pulled up on module.
CARRIER_PWR_ONS154Carrier board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.O CMOS1.8Vsb / 1.8VStandby1.8Vsb is only used for signaling, not a power source to the module
CARRIER_STBY#S153The Module shall drive this signal low when the system is in a standby power state.O CMOS1.8Vsb / 1.8VStandby
CHARGER_PRSNT#S152Held low by Carrier if DC input for battery charger is present.I OD CMOS1.8VStandby / SleepPU 10KDriven by OD on Carrier. Pulled up on module.
CHARGING#S151Held low by Carrier during battery charging. Carrier to float the line when charge is complete.I OD CMOS1.8VStandby / SleepPU 10KDriven by OD on Carrier. Pulled up on module.
VIN_PWR_BAD#S150Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.I OD CMOSVDD_INRuntimePU 10KDriven by OD on Carrier Module must implement PU but actual value is depended on particular module design.
SLEEP#S149Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state.Active low, level sensitive. Should be de-bounced on the Module.I OD CMOS1.8VStandbyPU 10KDriven by OD on Carrier. Pulled up on module.
LID#S148Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.I OD CMOS1.8VStandbyPU 10KDriven by OD on Carrier. Pulled up on module.
POWER_BTN#P128Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.I OD CMOS1.8VSleepPU 10KDriven by OD on Carrier. Pulled up on module.
RESET_OUT#P126General purpose reset output to Carrier board.O CMOS1.8VStandby
RESET_IN#P127Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.I OD CMOS1.8VStandbyPU 10KDriven by OD on Carrier. Pulled up on module.
I2C_PM_DATP122Power management I2C bus DATAI/O OD CMOS1.8VStandby / SleepPU 2k2On x86 systems these serve as SMB DATA. Pulled up on module.
I2C_PM_CKP121Power management I2C bus CLKO OD CMOS1.8VStandby / SleepPU 2k2On x86 systems these serve as SMB CLK. Pulled up on module.
SMB_ALERT_1V8#P1SMBus Alert# (interrupt) signalI OD CMOS1.8VStandby / SleepPU 2k2only used on x86 design
# 4.4.6 DB30 Multipurpose Connector FPC Connector: HIROSE,FH12-30S-0.5SH(55) ![PIN No. 1\n5\n0.15±0.85\n0.2 A\nPIN No. n\n3\n4\n①\n②\nA\nB](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/07bfeacba9eccabc92a16e10a3b9927bab56e11455949748a2c7ada118cc41eb.jpg) DB30 connector brings out the following type of signals SPI0 bus JTAG to SOC Boot Select strap pins BMC programming interface Serial port 4.4.7 Boot Select
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BOOT_SEL0#P123Input straps determine the Module bootI OD CMOS1.8VsbStandbyPU 10KDriven by OD on Carrier.Pulled up on module.Only booting from EMMc and SDcard is supported
BOOT_SEL1#P124
BOOT_SEL2#P125
FORCE_RECOV#S155I OD CMOS1.8VsbStandbyPU 10KDriven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.
4.4.8 Power
NamePin #DescriptionI/O TypePower Rail / TolerancePU / PDComments
VDD_INP147, P148, P149, P150, P151, P152, P153, P154, P155, P156Module power input voltage 4.75 min to 5.25V maxP Not defined within Signal Terminology Descriptions. Should we define a specific rail?3 to 5.25V / 5V
GNDP2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158Module signal and power return, and GND referenceP Not defined within Signal Terminology Descriptions. Should we define a specific rail?Ground
VDD_RTCS147Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.P Not defined within Signal Terminology Descriptions. Should we define a specific rail?[2 to 3.25] / 3.25V
4.5 SMARC Pin-to-controller Mapping
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
P1SMB_ALERT#In/ODPU-2.2KGPIO / 1.8VGPIO Expander (U2606)I/O14-VDD_1V8
P2GND-------
P3CSI1_CK+In-CSI D-PHYi.MX 8MPMIPI_CSI2_CLK_P-VDD_MIPI_1P8
P4CSI1_CK-In-CSI D-PHYi.MX 8MPMIPI_CSI2_CLK_N-VDD_MIPI_1P8
P5GBE1_SDPIn/Out-GPIO/3.3VDP83867 (U1601)GPIO_0-VDD_3V3
P6GBE0_SDPIn/Out-GPIO/3.3VDP83867 (U1501)GPIO_0-VDD_3V3
P7CSI1_RX0+In-CSI D-PHYi.MX 8MPMIPI_CSI2_D0_P-VDD_MIPI_1P8
P8CSI1_RX0-In-CSI D-PHYi.MX 8MPMIPI_CSI2_D0_N-VDD_MIPI_1P8
P9GND-------
P10CSI1_RX1+In-CSI D-PHYi.MX 8MPMIPI_CSI2_D1_P-VDD_MIPI_1P8
P11CSI1_RX1-In-CSI D-PHYi.MX 8MPMIPI_CSI2_D1_N-VDD_MIPI_1P8
P12GND-------
P13CSI1_RX2+In-CSI D-PHYi.MX 8MPMIPI_CSI2_D2_P-VDD_MIPI_1P8
P14CSI1_RX2-In-CSI D-PHYi.MX 8MPMIPI_CSI2_D2_N-VDD_MIPI_1P8
P15GND-------
P16CSI1_RX3+In-CSI D-PHYi.MX 8MPMIPI_CSI2_D3_P-VDD_MIPI_1P8
P17CSI1_RX3-In-CSI D-PHYi.MX 8MPMIPI_CSI2_D3_N-VDD_MIPI_1P8
P18GND-------
P19GBE0_MDI3-Bi-Dir-GBE MDIDP83867 (U1501)TD_M_D-VDDIO
P20GBE0_MDI3+Bi-Dir-GBE MDIDP83867 (U1501)TD_P_D-VDDIO
P21GBE0_LINK100#Out/OD-GPIO / 3.3VDP83867 (U1501)LED_1-VDDIO
P22GBE0_LINK1000#Out/OD-GPIO / 3.3VDP83867 (U1501)LED_2-VDDIO
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
P23GBE0_MDI2-Bi-Dir-GBE MDIDP83867 (U1501)TD_M_C-VDDIO
P24GBE0_MDI2+Bi-Dir-GBE MDIDP83867 (U1501)TD_P_C-VDDIO
P25GBE0_LINK_ACT#Out/OD-GPIO / 3.3VDP83867 (U1501)LED_0-VDDIO
P26GBE0_MDI1-Bi-Dir-GBE MDIDP83867 (U1501)TD_M_B-VDDIO
P27GBE0_MDI1+Bi-Dir-GBE MDIDP83867 (U1501)TD_P_B-VDDIO
P28GBE0_CTREFPWR------
P29GBE0_MDIO-Bi-Dir-GBE MDIDP83867 (U1501)TD_M_A-VDDIO
P30GBE0_MDIO+Bi-Dir-GBE MDIDP83867 (U1501)TD_P_A-VDDIO
P31SPI0_CS1#---N.C.N.C.--
P32GND-------
P33SDIO_WPIn/ODPU-10KSD2 / 3.3Vi.MX 8MPSD2_WPALT5NVCC_SD2
P34SDIO_CMDBi-Dir-SD2 / 3.3Vi.MX 8MPSD2_CMDALT5NVCC_SD2
P35SDIO_CD#In/ODPU-10KSD2 / 3.3Vi.MX 8MPSD2_CDALT5NVCC_SD2
P36SDIO_CKOut-SD2 / 3.3Vi.MX 8MPSD2_CLKALT5NVCC_SD2
P37SDIO_PWR_ENOut-GPIO / 3.3Vi.MX 8MPSD2_RESETALT5NVCC_SD2
P38GND-------
P39SDIO_D0Bi-Dir-SD2 / 3.3Vi.MX 8MPSD2_DATA0ALT5NVCC_SD2
P40SDIO_D1Bi-Dir-SD2 / 3.3Vi.MX 8MPSD2_DATA1ALT5NVCC_SD2
P41SDIO_D2Bi-Dir-SD2 / 3.3Vi.MX 8MPSD2_DATA2ALT5NVCC_SD2
P42SDIO_D3Bi-Dir-SD2 / 3.3Vi.MX 8MPSD2_DATA3ALT5NVCC_SD2
P43SPI0_CS0#Out-SPI / 1.8Vi.MX 8MPECSPI1_SS0ALT5NVCC_ECSPI_HDMI
P44SPI0_CKOut-SPI / 1.8Vi.MX 8MPECSPI1_SCLKALT5NVCC_ECSPI_HDMI
P45SPI0_DINIn-SPI / 1.8Vi.MX 8MPECSPI1_MISOALT5NVCC_ECSPI_HDMI
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
P46SPI0_DOOut-SPI / 1.8Vi.MX 8MPECSPI1_MOSIALT5NVCC_ECSPI_HDMI
P47GND-------
P48SATA_TX+---N.C.N.C.--
P49SATA_TX----N.C.N.C.--
P50GND-------
P51SATA_RX+---N.C.N.C.--
P52SATA_RX----N.C.N.C.--
P53GND-------
P54ESPI_CS0# / SPI1_CS0#Out-SPI / 1.8Vi.MX 8MPECSPI2_SS0ALT5NVCC_ECSPI_HDMI
P55ESPI_CS1# / SPI1_CS1#---N.C.N.C.--
P56ESPI_CK / SPI1_CKOut-SPI / 1.8Vi.MX 8MPECSPI2_SCLKALT5NVCC_ECSPI_HDMI
P57ESPI_IO_1 / SPI1_DINIn-SPI / 1.8Vi.MX 8MPECSPI2_MISOALT5NVCC_ECSPI_HDMI
P58ESPI_IO_0 / SPI1_DOOut-SPI / 1.8Vi.MX 8MPECSPI2_MOSIALT5NVCC_ECSPI_HDMI
P59GND-----
P60USB0+Bi-Dir-USBi.MX 8MPUSB1_D_PVDD_USB_3P3
P61USB0-Bi-Dir-USBi.MX 8MPUSB1_D_NVDD_USB_3P3
P62USB0_EN_OC#In/Out ODPU-10KGPIO / 1.8Vi.MX 8MPSAI1_TXD6ALT5NVCC_SAI1_SAI5
P63USB0_VBUS_DETPWR-USBi.MX 8MPUSB1_VBUS-VDD_USB_3P3
P64USB0_OTG_IDIn-USBi.MX 8MPUSB1_ID-VDD_USB_3P3
P65USB1+Bi-Dir-USBUSB Hub (FL5500)D_DP4-VDD_3V3_HUB
P66USB1-Bi-Dir-USBUSB Hub (FL5500)D_DM4-VDD_3V3_HUB
P67USB1_EN_OC#In/Out ODPU-10KGPIO / 3.3VUSB Hub (FL5500)X_GPIO_BUS_4-VDD_3V3_HUB
P68GND-----
P69USB2+Bi-Dir-USBUSB Hub (FL5500)D_DP0-VDD_3V3_HUB
P70USB2-Bi-Dir-USBUSB Hub (FL5500)D_DM0-VDD_3V3_HUB
P71USB2_EN_OC#In/Out ODPU-10KGPIO / 3.3VUSB Hub (FL5500)X_OVC-VDD_3V3_HUB
P72RSVD---N.C.N.C.
P73RSVD---N.C.N.C.
P74USB3_EN_OC#In/Out ODPU-10KGPIO / 3.3VUSB Hub (FL5500)X_GPIO_BUS_1-VDD_3V3_HUB
P75PCIE_A_RST#Out-GPIO / 3.3VPCIe Switch (PI7C9X2G304EV)DWNRST_1VDD_3V3
P76USB4_EN_OC#In/Out ODPU-10KGPIO / 3.3VUSB Hub (FL5500)X_GPIO_BUS_5-VDD_3V3_HUB
P77PCIE_B_CKREQ#In/Out ODPU-10KGPIO / 3.3VPCIe Switch (PI7C9X2G304EV)CLKREQ_1-VDD_3V3
P78PCIE_A_CKREQ#In/Out ODPU-10KGPIO / 3.3VPCIe Switch (PI7C9X2G304EV)CLKREQ_2-VDD_3V3
P79GND-------
P80PCIE_C_REFCK+Out--N.C.N.C.--
P81PCIE_C_REFCK-Out--N.C.N.C.--
P82GND-------
P83PCIE_A_REFCK+Out-PCIePCIe Switch (PI7C9X2G304EV)REFCLKO_P1-VDD_3V3
P84PCIE_A_REFCK-Out-PCIePCIe Switch (PI7C9X2G304EV)REFCLKO_N1-VDD_3V3
P85GND------
P86PCIE_A_RX+In-PCIePCIe Switch (PI7C9X2G304EV)PERP1-VDD_3V3
P87PCIE_A_RX-In-PCIePCIe Switch (PI7C9X2G304EV)PERN1-VDD_3V3
P88GND-------
P89PCIE_A_TX+OutSerial-0.1uFPCIePCIe Switch (PI7C9X2G304EV)PETP1-VDD_3V3
P90PCIE_A_TX-SMARC Signal NameOutModule DirectionSerial-0.1uFModule TerminationPCIeType/TolerancePCIe Switch (PI7C9X2G304EV)ControllerPETN1Controller Pin Name-I/O Mux defaultVDD_3V3Power Rail
P91GND-----
P92HDMI_D2+ / DP1_LANE0+Out-HDMIi.MX 8MPHDMI_TX2_P-VDD_HDMI_1P8
P93HDMI_D2- / DP1_LANE0-Out-HDMIi.MX 8MPHDMI_TX2_N-VDD_HDMI_1P8
P94GND-------
P95HDMI_D1+ / DP1_LANE1+Out-HDMIi.MX 8MPHDMI_TX1_PVDD_HDMI_1P8
P96HDMI_D1- / DP1_LANE1-Out-HDMIi.MX 8MPHDMI_TX1_NVDD_HDMI_1P8
P97GND-------
P98HDMI_D0+ / DP1_LANE2+Out-HDMIi.MX 8MPHDMI_TX0_P-VDD_HDMI_1P8
P99HDMI_D0- / DP1_LANE2-Out-HDMIi.MX 8MPHDMI_TX0_N-VDD_HDMI_1P8
P100GND-------
P101HDMI_CK+ / DP1_LANE3+Out-HDMIi.MX 8MPHDMI_TXC_P-VDD_HDMI_1P8
P102HDMI_CK- / DP1_LANE3-Out-HDMIi.MX 8MPHDMI_TXC_N`VDD_HDMI_1P8
P103GND-------
P104HDMI_HPD / DP1_HPDInPD-1MHDMIi.MX 8MPHDMI_HPDALT5NVCC_ECSPI_HDMI
P105HDMI_CTRL_CK / DP1_AUX+OutPU-100KHDMIi.MX 8MPHDMI_DDC_SCLALT5NVCC_ECSPI_HDMI
P106HDMI_CTRL_DAT / DP1_AUX-Bi-DirPU-100KHDMIi.MX 8MPHDMI_DDC_SDAALT5NVCC_ECSPI_HDMI
P107DP1_AUX_SEL-------
P108GPIO0 / CAM0_PWR#In/OutPU-470KGPIO / 1.8Vi.MX 8MPNAND_DATA00ALT5NVCC_NAND
P109GPIO1 / CAM1_PWR#In/OutPU-470KGPIO / 1.8Vi.MX 8MPNAND_DATA01ALT5NVCC_NAND
P110GPIO2 / CAM0_RST#In/OutPU-470KGPIO / 1.8Vi.MX 8MPGPIO1_IO06ALT0NVCC_GPIO1
P111GPIO3 / CAM1_RST#In/OutPU-470KGPIO / 1.8Vi.MX 8MPGPIO1_IO07ALT0NVCC_GPIO1
P112GPIO4 / HDA_RST#In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O0-VDD_1V8
P113GPIO5 / PWM_OUTIn/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O1-VDD_1V8
P114GPIO6 / TACHINIn/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O2-VDD_1V8
P115GPIO7In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O3-VDD_1V8
P116GPIO8In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O4-VDD_1V8
P117GPIO9In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O5-VDD_1V8
P118GPIO10In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O6-VDD_1V8
P119GPIO11In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O7-VDD_1V8
P120GND-----
P121I2C_PM_CKOutPU-2.2KI2C / 1.8i.MX 8MPI2C1_SCLALT5NVCC_I2C_UART
P122I2C_PM_DATBi-DirPU-2.2KI2C / 1.8i.MX 8MPI2C1_SDAALT5NVCC_I2C_UART
P123BOOT_SEL0#In/ODPU-10kGPIO / 1.8VBMCPB3-P_+1V8SMC
P124BOOT_SEL1#In/ODPU-10kGPIO / 1.8VBMCPB5-P_+1V8SMC
P125BOOT_SEL2#In/ODPU-10kGPIO / 1.8VBMCPA2-P_+1V8SMC
P126RESET_OUT#Out-GPIO / 1.8VBMCPC4-P_+1V8SMC
P127RESET_IN#In/ODPU-10KGPIO / 1.8VBMCPC12-P_+1V8SMC
P128POWER_BTN#In/ODPU-10KGPIO / 1.8VBMCPA11-P_+1V8SMC
P129SER0_TXOut-UART / 1.8Vi.MX 8MPUART2_TXDALT5NVCC_I2C_UART
P130SER0_RXInPU-100KUART / 1.8Vi.MX 8MPUART2_RXDALT5NVCC_I2C_UART
P131SER0_RTS#Out-UART / 1.8Vi.MX 8MPSD1_DATA4ALT5NVCC_SD1
P132SER0_CTS#InPU-100KUART / 1.8Vi.MX 8MPSD1_DATA5ALT5NVCC_SD1
P133GND-------
P134SER1_TXOut-UART / 1.8Vi.MX 8MPNAND_CE0_BALT5NVCC_NAND
P135SER1_RXInPU-100KUART / 1.8Vi.MX 8MPNAND_ALEALT5NVCC_NAND
P136SER2_TXOut-UART / 1.8Vi.MX 8MPUART4_TXDALT5NVCC_I2C_UART
P137SER2_RXInPU-100KUART / 1.8Vi.MX 8MPUART4_RXDALT5NVCC_I2C_UART
P138SER2_RTS#Out-UART / 1.8Vi.MX 8MPNAND_DATA03ALT5NVCC_NAND
P139SER2_CTS#InPU-100KUART / 1.8Vi.MX 8MPNAND_DATA02ALT5NVCC_NAND
P140SER3_TXOut-UART / 1.8Vi.MX 8MPUART1_TXDALT5NVCC_I2C_UART
P141SER3_RXInPU-100KUART / 1.8Vi.MX 8MPUART1_RXDALT5NVCC_I2C_UART
P142GND-------
P143CAN0_TXOut-CAN / 1.8Vi.MX 8MPSPDIF_TXALT5NVCC_SAI2_SAI3_SPDIF
P144CAN0_RXIn-CAN / 1.8Vi.MX 8MPSPDIF_RXALT5NVCC_SAI2_SAI3_SPDIF
P145CAN1_TXOut-CAN / 1.8Vi.MX 8MPSAI5_RXD3ALT5NVCC_SAI1_SAI5
P146CAN1_RXIn-CAN / 1.8Vi.MX 8MPSAI2_MCLKALT5NVCC_SAI2_SAI3_SPDIF
P147VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P148VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P149VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P150VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P151VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P152VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P153VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P154VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P155VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
P156VDD_INPWR--From Carrier board--4.75 ~ 5.25 V
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S1CSI1_TX+/I2C_CAM1_CKInPU-2.2KI2C / 1.8i.MX 8MPSAI5_RXD0ALT5NVCC_SAI1_SAI5
S2CSI1_TX-/I2C_CAM1_DATBi-DirPU-2.2KI2C / 1.8i.MX 8MPSAI5_MCLKALT5NVCC_SAI1_SAI5
S3GND-------
S4RSVDIn--N.C.N.C.--
S5CSI0_TX-/I2C_CAM0_CKOutPU-2.2KI2C / 1.8i.MX 8MPI2C3_SCLALT5NVCC_I2C_UART
S6CAM_MCKOut-GPIO / 1.8Vi.MX 8MPGPIO1_IO15ALT0NVCC_GPIO1
S7CSI0_TX+/I2C_CAM0_DATBi-DirPU-2.2KI2C / 1.8i.MX 8MPI2C3_SDAALT5NVCC_I2C_UART
S8CSI0_CK+In-MIPI-CSIi.MX 8MPMIPI_CSI1_CLK_P-VDD_MIPI_1P8
S9CSI0_CK-In-MIPI-CSIi.MX 8MPMIPI_CSI1_CLK_N-VDD_MIPI_1P8
S10GND-------
S11CSI0_RX0+In-MIPI-CSIi.MX 8MPMIPI_CSI1_D0_P-VDD_MIPI_1P8
S12CSI0_RX0-In-MIPI-CSIi.MX 8MPMIPI_CSI1_D0_N-VDD_MIPI_1P8
S13GND-------
S14CSI0_RX1+In-MIPI-CSIi.MX 8MPMIPI_CSI1_D1_P-VDD_MIPI_1P8
S15CSI0_RX1-In-MIPI-CSIi.MX 8MPMIPI_CSI1_D1_N-VDD_MIPI_1P8
S16GND-------
S17GBE1_MDIO+Bi-Dir-GBE MDIDP83867(U1601)TD_P_A-VDDIO
S18GBE1_MDIO-Bi-Dir-GBE MDIDP83867(U1601)TD_M_A-VDDIO
S19GBE1_LINK100#Out-GPIO / 3.3VDP83867(U1601)LED_1-VDDIO
S20GBE1_MDI1+Bi-Dir-GBE MDIDP83867(U1601)TD_P_B-VDDIO
S21GBE1_MDI1-Bi-Dir-GBE MDIDP83867(U1601)TD_M_B-VDDIO
S22GBE1_LINK1000#Out-GPIO / 3.3VDP83867(U1601)LED_2-VDDIO
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S23GBE1_MDI2+Bi-Dir-GBE MDIDP83867 (U1601)TD_P_C-VDDIO
S24GBE1_MDI2-Bi-Dir-GBE MDIDP83867 (U1601)TD_M_C-VDDIO
S25GND-------
S26GBE1_MDI3+Bi-Dir-GBE MDIDP83867 (U1601)TD_P_D-VDDIO
S27GBE1_MDI3-Bi-Dir-GBE MDIDP83867 (U1601)TD_M_D-VDDIO
S28GBE1_CTREFPWR------
S29PCIE_D_TX+/SERDES_1_TX+---N.C.N.C.--
S30PCIE_D_TX-/SERDES_1_TX----N.C.N.C.--
S31GBE1_LINK_ACT#Out-GPIO / 3.3VDP83867 (U1601)LED_0--
S32PCIE_D_RX+/SERDES_1_RX+---N.C.N.C.--
S33PCIE_D_RX-/SERDES_1_RX----N.C.N.C.--
S34GND-----
S35USB4+Bi-Dir-USBUSB Hub (FL5500)D_DP5--
S36USB4-Bi-Dir-USBUSB Hub (FL5500)D_DM5--
S37USB3_VBUS_DET---N.C.N.C.--
S38AUDIO_MCKOut-SAI / 1.8Vi.MX 8MPSAI3_MCLKALT5NVCC_SAI2_SAI3_SPDIF
S39I2S0_LRCKBi-Dir-SAI / 1.8Vi.MX 8MPSAI3_TXFSALT5NVCC_SAI2_SAI3_SPDIF
S40I2S0_SDOUTOut-SAI / 1.8Vi.MX 8MPSAI3_TXDALT5NVCC_SAI2_SAI3_SPDIF
S41I2S0_SDINIn-SAI / 1.8Vi.MX 8MPSAI3_RXDALT5NVCC_SAI2_SAI3_SPDIF
S42I2S0_CKBi-Dir-SAI / 1.8Vi.MX 8MPSAI3_TXCALT5NVCC_SAI2_SAI3_SPDIF
S43ESPI_ALERT0#---N.C.N.C.--
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S44ESPI_ALERT1#---N.C.N.C.--
S45MDIO_CLK---N.C.N.C.--
S46MDIO_DAT---N.C.N.C.--
S47GND-------
S48I2C_GP_CKOutPU-2.2KI2C / 1.8i.MX 8MPI2C2_SCLALT5NVCC_I2C_UART
S49I2C_GP_DATBi-DirPU-2.2KI2C / 1.8i.MX 8MPI2C2_SDAALT5NVCC_I2C_UART
S50HDA_SYNC / I2S2_LRCK---N.C.N.C.--
S51HDA_SDO / I2S2_SDOUT---N.C.N.C.--
S52HDA_SDI / I2S2_SDIN---N.C.N.C.--
S53HDA_CK / I2S2_CK---N.C.N.C.--
S54SATA_ACT#---N.C.N.C.--
S55USB5_EN_OC#In/Out ODPU-10KGPIO / 3.3VUSB Hub (FL5500)X_GPIO_BUS_2-VDD_3V3_HUB
S56ESPI_IO_2---N.C.N.C.--
S57ESPI_IO_3---N.C.N.C.--
S58ESPI_RESET#---N.C.N.C.--
S59USB5+Bi-Dir-USBUSB Hub (FL5500)D_DP2-VDD_3V3_HUB
S60USB5-Bi-Dir-USBUSB Hub (FL5500)D_DM2-VDD_3V3_HUB
S61GND-------
S62USB3_SSTX+OutSerial-0.1uFUSBUSB Hub (FL5500)D_SSTXP_1_1-VDD_3V3_HUB
S63USB3_SSTX-OutSerial-0.1uFUSBUSB Hub (FL5500)D_SSTXN_1_1-VDD_3V3_HUB
S64GND-------
S65USB3_SSRX+In-USBUSB Hub (FL5500)D_SSRXP_1_1-VDD_3V3_HUB
S66USB3_SSRX-In-USBUSB Hub (FL5500)D_SSRXN_1_1-VDD_3V3_HUB
S67GND-------
S68USB3+Bi-Dir-USBUSB Hub (FL5500)D_DP1-VDD_3V3_HUB
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S69USB3-Bi-Dir-USBUSB Hub (FL5500)D_DM1-VDD_3V3_HUB
S70GND-------
S71USB2_SSTX+OutSerial-0.1uFUSBUSB Hub (FL5500)D_SSTXP_1_0-VDD_3V3_HUB
S72USB2_SSTX-OutSerial-0.1uFUSBUSB Hub (FL5500)D_SSTXN_1_0-VDD_3V3_HUB
S73GND-------
S74USB2_SSRX+In-USBUSB Hub (FL5500)D_SSRXP_1_0-VDD_3V3_HUB
S75USB2_SSRX-In-USBUSB Hub (FL5500)D_SSRXN_1_0-VDD_3V3_HUB
S76PCIE_B_RST#Out-GPIO / 3.3VPCIe Switch (PI7C9X2G304EV)DWNRST_2VDD_3V3
S77PCIE_C_RST#---N.C.N.C.--
S78PCIE_C_RX+ / SERDES_2_RX+---N.C.N.C.--
S79PCIE_C_RX- / SERDES_2_RX----N.C.N.C.--
S80GND-------
S81PCIE_C_TX+ / SERDES_2_TX+---N.C.N.C.--
S82PCIE_C_TX- / SERDES_2_TX----N.C.N.C.--
S83GND-------
S84PCIE_B_REFCK+Out-PCIePCIe Switch (PI7C9X2G304EV)REFCLKO_P2-VDD_3V3
S85PCIE_B_REFCK-Out-PCIePCIe Switch (PI7C9X2G304EV)REFCLKO_N2-VDD_3V3
S86GND------
S87PCIE_B_RX+In-PCIePCIe Switch (PI7C9X2G304EV)PERP2-VDD_3V3
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S88PCIE_B_RX-In-PCIePCIe Switch (PI7C9X2G304EV)PERN2-VDD_3V3
S89GND-------
S90PCIE_B_TX+OutSerial-0.1uFPCIePCIe Switch (PI7C9X2G304EV)PETP2-VDD_3V3
S91PCIE_B_TX-OutSerial-0.1uFPCIePCIe Switch (PI7C9X2G304EV)PETN2-VDD_3V3
S92GND-------
S93DP0_LANE0+---N.C.N.C.--
S94DP0_LANE0----N.C.N.C.--
S95DP0_AUX_SEL---N.C.N.C.--
S96DP0_LANE1+---N.C.N.C.--
S97DP0_LANE1----N.C.N.C.--
S98DP0_HPD---N.C.N.C.--
S99DP0_LANE2+---N.C.N.C.--
S100DP0_LANE2--------
S101GND-------
S102DP0_LANE3+---N.C.N.C.--
S103DP0_LANE3----N.C.N.C.--
S104USB3_OTG_ID---N.C.N.C.--
S105DP0_AUX+---N.C.N.C.--
S106DP0_AUX----N.C.N.C.--
S107LCD1_BKLT_ENOutPD-10KGPIO / 1.8Vi.MX 8MPGPIO1_IO00ALT0NVCC_GPIO1
S108LVDS1_CK+/ eDP1_AUX+/ DSI1_CLK+Out-LVDSi.MX 8MPLVDS1_CLK_P-VDD_LVDS_1P8
S109LVDS1_CK-/ eDP1_AUX-/ DSI1_CLK-Out-LVDSi.MX 8MPLVDS1_CLK_N-VDD_LVDS_1P8
S110GND-------
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S111LVDS1_0+ / eDP1_TX0+ / DSI1_D0+Out-LVDSi.MX 8MPLVDS1_D0_P-VDD_LVDS_1P8
S112LVDS1_0- / eDP1_TX0- / DSI1_D0-Out-LVDSi.MX 8MPLVDS1_D0_N-VDD_LVDS_1P8
S113eDP1_HPD / DSI1_TE---N.C.N.C.--
S114LVDS1_1+ / eDP1_TX1+ / DSI1_D1+Out-LVDSi.MX 8MPLVDS1_D1_P-VDD_LVDS_1P8
S115LVDS1_1- / eDP1_TX1- / DSI1_D1-Out-LVDSi.MX 8MPLVDS1_D1_N-VDD_LVDS_1P8
S116LCD1_VDD_ENOutGPIO / 1.8Vi.MX 8MPGPIO1_IO05ALT0NVCC_GPIO1
S117LVDS1_2+ / eDP1_TX2+ / DSI1_D2+Out-LVDSi.MX 8MPLVDS1_D2_P-VDD_LVDS_1P8
S118LVDS1_2- / eDP1_TX2- / DSI1_D2-Out-LVDSi.MX 8MPLVDS1_D2_N-VDD_LVDS_1P8
S119GND-------
S120LVDS1_3+ / eDP1_TX3+ / DSI1_D3+Out-LVDSi.MX 8MPLVDS1_D3_P-VDD_LVDS_1P8
S121LVDS1_3- / eDP1_TX3- / DSI1_D3-Out-LVDSi.MX 8MPLVDS1_D3_N-VDD_LVDS_1P8
S122LCD1_BKLT_PWMOutGPIO / 1.8Vi.MX 8MPGPIO1_IO01ALT0NVCC_GPIO1
S123GPIO13In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O9-VDD_1V8
S124GND-------
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S125LVDS0_0+ / eDP0_TX0+ / DS10_D0+Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D0_P/ LVDS0_D0_P-VDD_MIPI_1P8/ VDD_LVDS_1P8
S126LVDS0_0- / eDP0_TX0- / DS10_D0-Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D0_N/ LVDS0_D0_N-VDD_MIPI_1P8/ VDD_LVDS_1P8
S127LCD0_BKLT_ENOutPD-10KGPIO / 1.8Vi.MX 8MPGPIO1_IO10ALT0NVCC_GPIO1
S128LVDS0_1+ / eDP0_TX1+ / DS10_D1+Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D1_P/ LVDS0_D1_P-VDD_MIPI_1P8/ VDD_LVDS_1P8
S129LVDS0_1- / eDP0_TX1- / DS10_D1-Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D1_N/ LVDS0_D1_N-VDD_MIPI_1P8/ VDD_LVDS_1P8
S130GND------
S131LVDS0_2+ / eDP0_TX2+ / DS10_D2+Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D2_P/ LVDS0_D2_P-VDD_MIPI_1P8/ VDD_LVDS_1P8
S132LVDS0_2- / eDP0_TX2- / DS10_D2-Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D2_N/ LVDS0_D2_N-VDD_MIPI_1P8/ VDD_LVDS_1P8
S133LCD0_VDD_ENOut-GPIO / 1.8Vi.MX 8MPGPIO1_IO13NVCC_GPIO1
S134LVDS0_CK+ / eDP0_AUX+ / DS10_CLK+Out-DSI/LVDSi.MX 8MPMIPI_DSI1_CLK_P/ LVDS0_CLK_P-VDD_MIPI_1P8/ VDD_LVDS_1P8
S135LVDS0_CK- / eDP0_AUX- / DS10_CLK-Out-DSI/LVDSi.MX 8MPMIPI_DSI1_CLK_N/ LVDS0_CLK_N-VDD_MIPI_1P8/ VDD_LVDS_1P8
S136GND------
S137LVDS0_3+ / eDP0_TX3+ / DS10_D3+Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D3_P/ LVDS0_D3_P-VDD_MIPI_1P8/ VDD_LVDS_1P8
SMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
S138LVDS0_3-/eDP0_TX3-/DSI0_D3-Out-DSI/LVDSi.MX 8MPMIPI_DSI1_D3_N/LVDS0_D3_N-VDD_MIPI_1P8/VDD_LVDS_1P8
S139I2C_LCD_CKOutPU-2.2KI2C / 1.8i.MX 8MPI2C3_SCLALT5NVCC_I2C_UART
S140I2C_LCD_DATBi-DirPU-2.2KI2C / 1.8i.MX 8MPI2C3_SDAALT5NVCC_I2C_UART
S141LCD0_BKLT_PWMOut-GPIO / 1.8Vi.MX 8MPGPIO1_IO11ALT0NVCC_GPIO1
S142GPIO12In/OutPU-470KGPIO / 1.8VGPIO Expander (U2605)I/O8-VDD_1V8
S143GND-------
S144eDP0_HPD /DSI0_TEInPD-1MSAI / 1.8Vi.MX 8MPSAI3_RXCALT5NVCC_SAI2_SAI3_SPDIF
S145WDT_TIME_OUT#Out-GPIO / 1.8VBMCPC7-P_+1V8SMC
S146PCIE_WAKE#In/ODPU-10KGPIO / 1.8Vi.MX 8MPI2C4_SDAALT5NVCC_I2C_UART
S147VDD_RTCPWR-PWR----
S148LID#In/ODPU-10KSAI / 1.8Vi.MX 8MPSPDIF_EXT_CLKALT5NVCC_SAI2_SAI3_SPDIF
S149SLEEP#In/ODPU-10KGPIO / 1.8VGPIO Expander (U2606)I/O0-VDD_1V8
S150VIN_PWR_BAD#In/ODPU-10KPWRBuck IC (TPS74801DRCR_TI)ENVIN_SHUNT
S151CHARGING#In/ODPU-10KGPIO / 1.8VGPIO Expander (U2606)I/O1-VDD_1V8
S152CHARGER_PRSNT#In/ODPU-10KGPIO / 1.8VGPIO Expander (U2606)I/O2-VDD_1V8
S153CARRIER_STBY#Out-GPIO / 1.8VBMCPB1-P_+1V8SMC
S154CARRIER_PWR_ONOut-GPIO / 1.8VBMCPB6-P_+1V8SMC
S155FORCE_RECOV#InPU-10KGPIO / 1.8VBMCPA8-P_+1V8SMC
S156BATLOW#InPU-10KGPIO / 1.8VGPIO Expander (U2606)I/O3-VDD_1V8
S157TEST#InPU-vendor specific valueGPIO / 1.8VGPIO Expander (U2606)I/O13-VDD_1V8
S158GND-------
# 5. Software Support # 5.1 Uboot / Yocto Yocto source code and compiling instructions available at https://github.com/adlink # 5.2 Ubuntu Build instructions and source code available at https://github.com/adlink # 5.3 Android Android source code and compiling instructions available at https://github.com/adlink # 6. Mechanical ![Module Primary (Top) Side\n4X Ø6\n4X Ø2.70\nTHROUGH\n78\n82\n12\n7.70\n6.20\n3.30\n3.10\n0\n1.25 PIN P1\n74 PINS\nP1 - P74\nA\n774\n775\n82 PINS\nP75 - P156\n39](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/0d04e77770ccd27e181e52455ac1de92410befce6f56aaeb0430db6b85796ac8.jpg) ![1.00 PIN S1\n75 PINS\nS1 - S75\n83 PINS\nS76 - S158\nS4\nModule Primary (Bottom) Side](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/0e9563bc69a7ffa69dbdf59aec6fb77a559fbe53d46399cbb7bd542ff2f61d60.jpg) ![FULLRAD\n73X0.50\n81X0.50\n(3.30)\n156X0.35\nP74\nP75\n3.10 TYP\n1.00\n1.25\n1.25\nDETAILA\nTOP SIDE](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/3b8351be2fb480d63e5254cbec2ebb7ee0996224efab32052dddba1ec1b60b33.jpg) ![1.70\n2X R0.50\n(6.20)\n(1.50)\nDETAILD\nNOTCH, 2 PLACES](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/b20582496a6e49af380285f5d2d863d76e042b6971f893a7e27bdc7461b9f237.jpg) ![P74\nP75\nTOP SIDE\n0.25\nS76\nS75\nBOTTOM SIDE\nPIN ALIGNMENT DETAIL](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/0be9882b5aa30a3a4df8242dc84890e71a596f5afebcb01ee1ddf419cd428ee5.jpg) ![74X0.50\n3.10 TYP\nS75\nS76\n1\n1\n82X0.50\n158X0.35\nDETAILB\nBOTTOM SIDE](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/138b1796952fd29899bca05efda3c7e6ca039d7d9a67e76d7cf47077979ba3ee.jpg) ![The image displays a technical line drawing of a slot cross-section labeled **CHAMFEREDGE DETAL** at the bottom. It features three dimensions: a top width of **1.20 +/- 0.1**, a vertical depth of **0.18** on the left, and a slanted angle of **45°** on the right.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/7b4507280e8d04e15e7bc63cc15a8c55eaaf580b25398475d1b80b8da245c2fb.jpg) ![3.00 MAX\nCOMPONENT HEIGHT\n(TOP SIDB)\n1.30 MAX\nCOMPONENT HEIGHT\n(BOTTOM SIDB)](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/db88e935d2efe6280189837763c808cfe017a95a2a362967d35707fa972ff56d.jpg) Figure 3 – Mechanical dimensions # 7. Thermal Solutions For optimal performance, LEC-IMX8M Plus has to be cooled by a passive heatsink / heat-spreader (optionally available for ordering) ![The image displays a technical engineering drawing of a rectangular electronic component, likely a heat sink module, presented in four orthographic views with dimensional annotations.\n\n**1. Front View (Left):**\n* Depicts a rectangular block with vertical fins running across the face.\n* **Left Edge Dimensions (Vertical):** From top to bottom, the numbers are 42, 38±0.1, 34. Below the lower hole, the numbers are 8, 4±0.1, 0, 8.\n* **Right Edge Dimensions (Horizontal):** The numbers 74, 78±0.1, and 82±0.3 are listed vertically along the right edge.\n* Circular mounting holes are visible in the corners.\n\n**2. Side Profile View (Top Center):**\n* Shows the side profile of the component.\n* **Vertical Dimension:** A dimension circled with the number **2** indicates a height of **42±0.2**.\n* **Thickness Dimension:** A smaller dimension indicates **0.65**.\n* **Text:** The text **4-ø2.7** is visible at the top.\n\n**3. Top View (Right):**\n* Shows the top surface of the component.\n* **Horizontal Dimension:** A dimension circled with the number **1** indicates a width of **82±0.3**.\n* **Vertical Dimension:** Matches the side view height of **42±0.2** (circled **2**).\n* **Text:** The text **NC1431** is printed on the surface.\n* Features include a square cutout, a rectangular cutout below it, and four corner mounting holes.\n\n**4. Bottom View (Bottom):**\n* Shows the underside of the component with fins and adhesive strips.\n* **Vertical Dimension (Left):** A dimension circled with the number **3** indicates **12±0.3**.\n* **Vertical Dimension (Right):** A dimension circled with the number **6** indicates **1.65±0.1**.\n* **Label:** An arrow points to strips with the text **Thermally Conductive Adhesive**.](.smarc-lec-imx8m-plus-manual-50m-72512-1080-18/0c784d749322196996afb3051a3ef6a71a31a0b50ea29e9ddec931734e6b4d07.jpg)
HTS-sIMX8MPHeatspreader for LEC-iMX8MP
THS-sIMX8MPLow profile heatsink for LEC-iMX8MP
Figure 4 – Thermal solutions