# LEC-IMX8MM User's Guide 03/04/2022 ![The image displays the logo for NXP. The letters 'NXP' are arranged horizontally in a stylized, sans-serif font against a white background.\n\n* The letter **N** is on the left, composed of a yellow vertical bar and a brownish-grey diagonal bar.\n* The letter **X** is in the center, colored blue.\n* The letter **P** is on the right, featuring a light green vertical bar and a dark green loop.](.smarc-lec-imx8mm-user-s-guide-rev06/9b564d77c529ddc848aec38dc908ea3cedc37dce321367cc651bc0f0cb618810.jpg) ![Close-up of a blue printed circuit board with various electronic components and gold contacts (no readable text or symbols)](.smarc-lec-imx8mm-user-s-guide-rev06/0d26d4e503200df5e632f1e53d5e5b2f8f79000cfa293d70aa6c45e5558cea80.jpg) ![The image features a lime green cross shape with rounded corners and a white square cutout in the center, set against a white background.](.smarc-lec-imx8mm-user-s-guide-rev06/0f5690ae75029f76bb31b685d551a0a7c42ec13a4bf571e1686dfa5fa0a693bf.jpg) SMARC module # Preface # Disclaimer Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice. # Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # © Copyright 2017 ADLINK Technology, Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Safety Instructions For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this manual for future reference. • Read the specifications section of this manual for detailed information on the operating environment of this equipment. • Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment. • To avoid electrical shock and/or damage to equipment: Keep equipment away from water or liquid sources; Keep equipment away from high heat or high humidity; • Keep equipment properly ventilated (do not block or cover ventilation openings); • Make sure to use recommended voltage and power source settings; • Always install and operate equipment near an easily accessible electrical socket outlet; • Secure the power cord (do not place any object on/over the power cord); • Only install/attach and operate equipment on stable surfaces and/or recommended mountings; • If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment. # Conventions The following conventions may be used throughout this manual, denoting special levels of information ![A white icon featuring a red outline of a document with a folded top-right corner. Inside the outline are three horizontal red lines.](.smarc-lec-imx8mm-user-s-guide-rev06/38d74802bc45ba385ddcad846af8facb608a0c0d0141fa4016e8a49dfd5f9905.jpg) Note: This information adds clarity or specifics to text and illustrations. ![This image shows a low-resolution, yellow triangular warning sign with a white exclamation point centered inside. A faint, thin horizontal line runs across the upper portion of the triangle. The graphic is set against a white background.](.smarc-lec-imx8mm-user-s-guide-rev06/b60048093cf40f8f40cefae5e4fedf4ba1ffe2365d9a7ae8ee600cce69694827.jpg) Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. ![The image shows a red triangular warning symbol containing a white exclamation mark centered inside it, set against a white background.](.smarc-lec-imx8mm-user-s-guide-rev06/ef4e68f735d3ba12024d07a62d86709bf419a61fe1a21f9a4ad81dd3a5bf5849.jpg) Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. # Revision History
RevisionDescriptionDate (dd/mm/yyyy)Author
0.6Preliminary engineering version updated05/04/2022HP
# Table of Contents # Introduction .. . 8 1.1 The SMARC Formfactor .. ..8 # 2. Specifications.. C 2.1 Core System... ..9 2.2 Video.... ... 10 2.3 Audio ... ... 10 2.4 Dual Ethernet... ... 11 2.5 1216 M.2 LGA WIFI (optional) .. ... 11 2.6 Extension busses.. ... 11 2.7 System Storage .. ... 13 2.8 Boot Modes .. ... 13 2.9 Power... ... 14 2.10 Mechanical and Environmental . ... 14 # 3. Block Diagram .. .15 # 4. Pinout and Signal Descriptions ... .16 4.1 Pin Summary .. .. 16 4.2 Signal Terminology Descriptions.. ... 20 4.3 Signal Description by function... .. 21 4.3.1 The First Display Interface . . 21 4.3.2 MIPI Camera support (CSI1-4Lane) ... . 25 4.3.3 I2S (audio) ... ... 26 4.3.4 USB ports... . 27 4.3.5 PCIe Ports .. . 29 4.3.6 LAN ports .. ... 30 4.3.7 SDIO.... . 32 4.3.8 SPI & ESPI... ... 33 4.3.9 SPI0 ... ... 33 4.3.10 ESPI .. . 34 # 4.4 General Purpose I2C.. . 35 4.4.1 GPIO.. . 36 4.4.2 UART... . 37 4.4.3 CAN bus ... ... 38 4.4.4 Miscellaneous .. ... 38 4.4.5 Power and System Management . . 39 4.4.6 Boot Select.. . 41 4.4.7 Power . . 42 4.5 SMARC pin to controller mapping.... . 43 5. Software Support .... .54 5.1.1 Uboot / Yocto... . 54 5.1.2 Ubuntu (TBD)... . 54 6. Mechanical.... .55 7. Thermal Solutions... .56 # List of Figures Figure 1 – Module function diagram... .15 Figure 2 – Module top/botom side pin numbering .. .17 # Introduction # 1.1 The SMARC Formfactor The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor computer on Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented X86 devices and other RISC CPUs may be used as well. The Module power envelope is typically under 6W. Two Module sizes are defined: 82 mm x 50 mm and 82 mm x 80 mm. The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321 pin connector, but 7 pins are lost to the key). The Modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the Module. The Modules are used with application specific Carrier Boards that implement other features such as audio CODECs, touch controllers, wireless devices, etc. The modular approach allows scalability, fast time to market and upgradability while still maintaining low costs, low power and small physical size. ![The image displays a logo featuring the text 'SGeT'. The letters 'S', 'G', and 'T' are large and yellow, while a lowercase 'e' in magenta is superimposed over the 'G' and the left side of the 'T'.](.smarc-lec-imx8mm-user-s-guide-rev06/152c6ab92f56ceefcb26030b9d9c43e1d1995da7906d9beb295d6da544c8e84d.jpg) STANDARDIZATION GROUPFOR EMBEDDED TECHNOLOGIES SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html # 2. Specifications # 2.1 Core System # SoC NXP iMX 8M Series • i.MX8M-Mini Quad 4 x Cortex-A53 at 1.6 - 1.8GHz, 1 x Cortex-M4F, GPU, VPU Decode/Encode • i.MX8M-Mini QuadLite: 4 x Cortex-A53 at 1.6 - 1.8GHz, 1 x Cortex-M4F available either as industrial (-40°C to +85°C) or commercial (0°C to +70°C) type" # L2 Cache 32 KB I-cache 32 KB D-cache (A53) 512 KB L2 Cache (ECC) # Memory 1 / 2 / 4GB LPDDR4 memory down # security TPM 2.0 Device, ST Microelectronics ST33HTPH2X32AHD5 (optional) compliant with Trusted Computing Group (TCG) Trusted Platform Module (TPM) Library specifications 2.0, Level 0, Revision 138 and TCG PC Client Specific TPM Platform Specifications 1.03 • Fault-tolerant firmware loader that keeps the TPM fully functional when the loading process is interrupted (self-recovery) SP800-193 compliant for protection, detection and recovery requirements # 2.2 Video LEC-iMX8M mini standard display support is consisting of single/dual channel 24-bit LVDS and a 4-lane DSI. # GPU Core: Vivante GCNanoUltra # GPU/VPU Feature Support 1080p60 VP9 Profile 0, 2 (10-bit) 1080p60 HEVC/H.265 Decoder 1080p60 AVC/H.264 Baseline, Main, High decoder 1080p60 VP8 • 1080p60 AVC/H.264 Encoder 1080p60 VP8 • TrustZone support # LVDS SN65DSI84ZXHR (optional) LVDS single/dual channel 24-bit at max. 1920 ×1080 at 60 Hz over DSI to LVDS bridge # MIPI DSI DSI 4 lanes at max. 1080p@60fps display output (multiplexed with LVDS signal) # Camera support - Compatible with the MIPI Alliance Interface specification v2.1 - One MIPI-CSI2 camera input 4-lane # 2.3 Audio Supports I2S audio codec interface, audio ADC and DAC (located on carrier) # 2.4 Dual Ethernet # Primary LAN Gigabit Ethernet controller with Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588 Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex " # Secondary LAN RTL9119i-CG (optional) PCIe Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), and IEEE 1588 Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex # 2.5 1216 M.2 LGA WIFI (optional) LEC-IMX8MM can be equipped with an optional WIFI LGA module. In case of non-populated part, the footprint is still there and visible Only the Azurewave AW-CM276NF has been validated during DVT but other M.2 LGA modules could be compatible as well if they use the same standard interfaces, following are the used interface SDIO0 (main WIFI interface) UART1 (main Bluetooth interface) PCM ( Bluetooth audio transfer interface ) AW-CM276F has been pre-certified by Azurewave for several countries and regions, Adlink can assist in final device certification if applicable FCC ID: UAY-W8997-M1216 # 2.6 Extension busses # PCIe One PCI Express GEN2 x1 interfaces # USB 2x USB 2.0, (USB0, USB1) Optional a 4 port USB hub is available which brings out a total of 5 USB busses # UART Four UART interface SER0, SER2 (Tx/Rx/CTS/RTS) and SER1, SER3(optional) (Tx/Rx) 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) Programmable baud rates up to 4 Mbps. # CAN bus (optional) Supporting single CAN2.0B only or mixed CAN2.0B and CAN FB mode, data bit rate up to 8 Mbps via SPI to CAN adapter # SPI 2x SPI # I2S 1x I2S interface< CODEC located on the carrier # I2C 2x I2C interfaces \- Support for 7-bit and 10-bit address mode \- Software programmable clock frequency of 100 kbit/s in Standard-mode, 400 kbit/s in the Fast-mode or 1 Mbit/s in Fast-mode Plus # GPIO 13x GPIO with interrupt # 2.7 System Storage # SDIO 1x SDIO (4-bit) compatible up to version 3.0. # eMMC Soldered on module 16 \~ 128GB (build option) either standard or -40+85C temp range Compatible with eMMC specification 4.41, 4.51 and 5.0 # 2.8 Boot Modes eMMC and SD-Card boot modes are supported # 2.9 Power # Supply Voltage 4.75 V – 5.25 V # 2.10 Mechanical and Environmental # Form Factor SGET SMARC Specifications v2.1 # Dimension SMARC small size module, 82mm x 50mm # Operating Temperature Standard: 0°C to +60°C Rugged: -40°C to +85°C (optional) # Humidity 5-90% RH operating, non-condensing 5-95% RH storage (and operating with conformal coating) # Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27, MIL-STD-202 F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D # 3. Block Diagram ![The diagram depicts the connectivity of the **NXP i.MX 8M Mini** system-on-chip (SoC), shown as a large central red block.\n\n**Central Block (SoC Interfaces):**\nThe red block contains the following labeled internal interfaces:\n* **DSI 4 lanes**\n* **MIPI CSI 4-lanes**\n* **USB 2.0 OTG**\n* **USB 2.0 Host**\n* **RGMII**\n* **1x PCIe x1**\n* **ESPI CS1**\n* **ESPI CS0**\n* **UART x4**\n* **I2S**\n* **SDMMC**\n* **GPIO x13**\n\n**Left-Side Connections (Board Pins to SoC/Chips):**\n* **DSI0** connects to **DSI 4 lanes**.\n* **DSI 4 lanes** connects to a block labeled **DSI to LVDS**, which outputs to **LVDS0** and **LVDS1**.\n* **CSI1** connects to **MIPI CSI 4-lanes**.\n* **USB0** connects to **USB 2.0 OTG**.\n* **USB 2.0 Host** connects to a block labeled **USB hub**.\n* **USB1**, **USB2**, **USB3**, and **USB4** connect to the **USB hub**.\n* **RGMII** connects to a blue block labeled **DM9119INX**, which connects to **GbE0**.\n* **1x PCIe x1** connects to a white block labeled **RTL8119i-CG**, which connects to **GbE1**.\n* **PCIe0** connects directly to **1x PCIe x1**.\n* **CAN0** connects to a block labeled **CAN + FD**.\n* **SPI1** and **SPI0** connect to **ESPI CS1** and **ESPI CS0**.\n* **UART0**, **UART1**, **UART2**, and **UART3** connect to **UART x4**.\n* **I2S** connects to **I2S**.\n* **SDIO** connects to **SDMMC**.\n* **GPIO** connects to **GPIO x13**.\n* **I2C_GP** and **I2C_PM** connect to a block labeled **TPM**.\n\n**Right-Side and Bottom Connections:**\n* **LPDDR4 x32 1 / 2/ 4 GB** connects to the central block.\n* **eMCC Up to 128GB** connects to the central block.\n* **WIFI/BT** connects to the central block via an orange line.\n* **Watchdog / Boot Select, Power Control** connects to a block labeled **PMIC**, which connects to the bottom of the central block.\n* **RTC backup power** connects to a block labeled **RTC Crystal + PWR**, which connects to the bottom of the central block.](.smarc-lec-imx8mm-user-s-guide-rev06/a58db618e9e31d6532139d120b7f4a30f71544cb3570b14e3abd1720b2a370e3.jpg) Figure 1 – Module function diagram # 4. Pinout and Signal Descriptions # 4.1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1. ![TOP Side\nP1 P74 P75 P156\nKey](.smarc-lec-imx8mm-user-s-guide-rev06/239b5bc596636d0516cbb7b33e7871d1769d174e6d455f324c0297162fe98dbc.jpg) ![BOTTOM Side\nS156 S76 S75 S1\nKey](.smarc-lec-imx8mm-user-s-guide-rev06/9ef183ce94fd8a8f25b8ba1cb1549f520a06ba0627222a4535715097aa7f3a70.jpg) Figure 2 – Module top/botom side pin numbering <table>P-PinPrimary (Top) SideP1SMB_ALERT_1V8#P2GNDP3CSI1_CK+P4CSI1_CK-P5GBE1_SDPP6GBE0_SDPP7CSI1_RX0+P8CSI1_RX0-P9GNDP10CSI1_RX1+P11CSI1_RX1-P12GNDP13CSI1_RX2+P14CSI1_RX2-P15GNDP16CSI1_RX3+P17CSI1_RX3-P18GNDP19GBE0_MDI3-P20GBE0_MDI3+P21GBE0_LINK100#P22GBE0_LINK1000#P23GBE0_MDI2-P24GBE0_MDI2+P25GBE0_LINK_ACT#P26GBE0_MDI1-P27GBE0_MDI1+P28GBE0_CTREF
S-PinSecondary (Bottom) Side
S1CSI1_TX+ / I2C_CAM1_CK
S2CSI1_TX- / I2C_CAM1_DAT
S3GND
S4RSVD
S5CSI0_TX- / I2C_CAM0_CK
S6CAM_MCK
S7CSI0_TX+ / I2C_CAM0_DAT
S8CSI0_CK+
S9CSI0_CK-
S10GND
S11CSI0_RX0+
S12CSI0_RX0-
S13GND
S14CSI0_RX1+
S15CSI0_RX1-
S16GND
S17GBE1_MDI0+
S18GBE1_MDI0-
S19GBE1_LINK100#
S20GBE1_MDI1+
S21GBE1_MDI1-
S22GBE1_LINK1000#
S23GBE1_MDI2+
S24GBE1_MDI2-
S25GND
S26GBE1_MDI3+
S27GBE1_MDI3-
S28GBE1_CTREF
S29PCIE_D_TX+ / SERDES 1_TX+
P-PinPrimary (Top) Side
P29GBE0_MDIO-
P30GBE0_MDIO+
P31SPI0_CS1
P32GND
P33SDIO_WP
P34SDIO_CMD
P35SDIO_CD#
P36SDIO_CK
P37SDIO_PWR_EN
P38GND
P39SDIO_D0
P40SDIO_D1
P41SDIO_D2
P42SDIO_D3
P43SPI0_CS0#
P44SPI0_CK
P45SPI0_DIN
P46SPI0_DO
P47GND
P48SATA_TX+
P49SATA_TX-
P50GND
P51SATA_RX+
P52SATA_RX-
P53GND
P54ESPI_CS0# / SPI1_CS0#
P55ESPI_CS1# / SPI1_CS1#
P56ESPI_CK / SPI1_CK
P57ESPI_IO_1 / SPI1_DIN
S-PinSecondary (Bottom) Side
S30PCIE_D_TX- / SERDES 1 TX-
S31GBE1_LINK_ACT#
S32PCIE_D_RX+ / SERDES 1 RX+
S33PCIE_D_RX- / SERDES 1 RX-
S34GND
S35USB4+
S36USB4-
S37USB3_VBUS_DET
S38AUDIO_MCK
S39I2S0_LRCK
S40I2S0_SDOUT
S41I2S0_SDIN
S42I2S0_CK
S43ESPI_ALERT0#
S44ESPI_ALERT1#
S45MDIO_CLK
S46MDIO_DAT
S47GND
S48I2C_GP_CK
S49I2C_GP_DAT
S50HDA_SYNC / I2S2_LRCK
S51HDA_SDO / I2S2_SDOUT
S52HDA_SDI / I2S2_SDIN
S53HDA_CK / I2S2_CK
S54SATA_ACT#
S55USB5_EN_OC
S56ESPI_IO_2
S57ESPI_IO_3
S58ESPI_RESET#
P-PinPrimary (Top) Side
P58ESPI_IO_0 / SPI1_DO
P59GND
P60USB0+
P61USB0-
P62USB0_EN_OC#
P63USB0_VBUS_DET
P64USB0_OTG_ID
P65USB1+
P66USB1-
P67USB1_EN_OC#
P68GND
P69USB2+
P70USB2-
P71USB2_EN_OC#
P72RSVD
P73RSVD
P74USB3_EN_OC#
Key
P75PCIE_A_RST#
P76USB4_EN_OC#
P77PCIE_B_CKREQ#
P78PCIE_A_CKREQ#
P79GND
P80PCIE_C_REFCK+
P81PCIE_C_REFCK-
P82GND
P83PCIE_A_REFCK+
P84PCIE_A_REFCK-
P85GND
P86PCIE_A_RX+
P87PCIE_A_RX-
P88GND
P89PCIE_A_TX+
S-PinSecondary (Bottom) Side
S59USB5+
S60USB5-
S61GND
S62USB3_SSTX+
S63USB3_SSTX-
S64GND
S65USB3_SSRX+
S66USB3_SSRX-
S67GND
S68USB3+
S69USB3-
S70GND
S71USB2_SSTX+
S72USB2_SSTX-
S73GND
S74USB2_SSRX+
S75USB2_SSRX-
Key
S76PCIE_B_RST#
S77PCIE_C_RST#
S78PCIE_C_RX+ / SERDES 2 RX+
S79PCIE_C_RX- / SERDES 2 RX-
S80GND
S81PCIE_C_TX+ / SERDES 2 TX+
S82PCIE_C_TX- / SERDES 2 TX-
S83GND
S84PCIE_B_REFCK+
S85PCIE_B_REFCK-
S86GND
S87PCIE_B_RX+
S88PCIE_B_RX-
S89GND
S90PCIE_B_TX+
P-PinPrimary (Top) Side
P90PCIE_A_TX-
P91GND
P92HDMI_D2+ / DP1_LANE0+
P93HDMI_D2- / DP1_LANE0-
P94GND
P95HDMI_D1+ / DP1_LANE1+
P96HDMI_D1- / DP1_LANE1-
P97GND
P98HDMI_D0+ / DP1_LANE2+
P99HDMI_D0- / DP1_LANE2-
P100GND
P101HDMI_CK+ / DP1_LANE3+
P102HDMI_CK- / DP1_LANE3-
P103GND
P104HDMI_HPD / DP1_HPD
P105HDMI_CTRL_CK / DP1_AUX+
P106HDMI_CTRL_DAT / DP1_AUX-
P107DP1_AUX_SEL
P108GPIO0 / CAM0_PWR#
P109GPIO1 / CAM1_PWR#
P110GPIO2 / CAM0_RST#
P111GPIO3 / CAM1_RST#
P112GPIO4 / HDA_RST#
P113GPIO5 / PWM_OUT
P114GPIO6 / TACHIN
P115GPIO7
P116GPIO8
P117GPIO9
P118GPIO10
P119GPIO11
P120GND
P121I2C_PM_CK
P122I2C_PM_DAT
P123BOOT_SEL0#
P124BOOT_SEL1#
S-PinSecondary (Bottom) Side
S91PCIE_B_TX-
S92GND
S93DP0_LANE0+
S94DP0_LANE0-
S95DP0_AUX_SEL
S96DP0_LANE1+
S97DP0_LANE1-
S98DP0_HPD
S99DP0_LANE2+
S100DP0_LANE2-
S101GND
S102DP0_LANE3+
S103DP0_LANE3-
S104USB3_OTG_ID
S105DP0_AUX+
S106DP0_AUX-
S107LCD1_BKLT_EN
S108LVDS1_CK+/eDP1_AUX+/ DSI1_CLK+
S109LVDS1_CK- / eDP1_AUX- / DSI1_CLK-
S110GND
S111LVDS1_0+ / eDP1_TX0+ / DSI1_D0+
S112LVDS1_0- / eDP1_TX0- / DSI1_D0-
S113eDP1_HPD / DSI1_TE
S114LVDS1_1+ / eDP1_TX1+ / DSI1_D1+
S115LVDS1_1- / eDP1_TX1- / DSI1_D1-
S116LCD1_VDD_EN
S117LVDS1_2+ / eDP1_TX2+ / DSI1_D2+
S118LVDS1_2- / eDP1_TX2- / DSI1_D2-
S119GND
S120LVDS1_3+ / eDP1_TX3+ / DSI1_D3+
S121LVDS1_3- / eDP1_TX3- / DSI1_D3-
S122LCD1_BKLT_PWM
S123GPIO13
S124GND
S125LVDS0_0+ / eDP0_TX0+ / DSI0_D0+
P-PinPrimary (Top) Side
P125BOOT_SEL2#
P126RESET_OUT#
P127RESET_IN#
P128POWER_BTN#
P129SERO_TX
P130SERO_RX
P131SERO_RTS#
P132SERO_CTS#
P133GND
P134SER1_TX
P135SER1_RX
P136SER2_TX
P137SER2_RX
P138SER2_RTS#
P139SER2_CTS#
P140SER3_TX
P141SER3_RX
S-PinSecondary (Bottom) Side
S126LVDS0_0- / eDP0_TX0- / DSI0_D0-
S127LCD0_BKLT_EN
S128LVDS0_1+ / eDP0_TX1+ / DSI0_D1+
S129LVDS0_1- / eDP0_TX1- / DSI0_D1-
S130GND
S131LVDS0_2+/eDP0_TX2+/ DSI0_D2+
S132LVDS0_2- / eDP0_TX2- / DSI0_D2-
S133LCD0_VDD_EN
S134LVDS0_CK+/eDP0_AUX/ DSI0_CLK+
S135LVDS0_CK-/eDP0_AUX- / DSI0_CLK-
S136GND
S137LVDS0_3+ / eDP0_TX3+ / DSI0_D3+
S138LVDS0_3- / eDP0_TX3- / DSI0_D3-
S139I2C_LCD_CK
S140I2C_LCD_DAT
S141LCD0_BKLT_PWM
S142GPIO12
P-PinPrimary (Top) Side
P142GND
P143CAN0_TX
P144CAN0_RX
P145CAN1_TX
P146CAN1_RX
P147VDD_IN
P148VDD_IN
P149VDD_IN
P150VDD_IN
P151VDD_IN
P152VDD_IN
P153VDD_IN
P154VDD_IN
P155VDD_IN
P156VDD_IN
S-PinSecondary (Bottom) Side
S143GND
S144eDP0_HPD / DSI0_TE
S145WDT_TIME_OUT#
S146PCIE_WAKE#
S147VDD_RTC
S148LID#
S149SLEEP#
S150VIN_PWR_BAD#
S151CHARGING#
S152CHARGER_PRSNT#
S153CARRIER_STBY#
S154CARRIER_PWR_ON
S155FORCE_RECOV#
S156BATLOW#
S157TEST#
S158GND
![The image displays a red icon resembling a document or piece of paper with a folded bottom-right corner. Inside the outline, there are two horizontal red lines, with the top line being shorter than the bottom one.](.smarc-lec-imx8mm-user-s-guide-rev06/620736698d2794505c7b6d0bc55550b675396377377370984f9f18d9418d4ad3.jpg) Note : DSI0 is pinshared with LVDS0 # 4.2 Signal Terminology Descriptions Meaning of the terms used for signal description tables
TermDescription
IInput to the module
OOutput from the module
O ODOpen drain output from the module
I ODOpen drain input to the module, with mandatory PU (pull up) on module
ODOpen drain
I/OBi-directional Input/Output
PUPU (pull-up) resistor on module
PDPD (pull-down) resistor on module
VDD_INMain power source from carrier to module
CMOSLogic input or output
GBE MDIDifferential analog signaling for Gigabit Media Dependent Interface
LVDS DPLow Voltage Differential Signal for DisplayPort interface
LVDS D-PHYLow Voltage Differential Signal for MIPI CSI-2 cameras and DSI displays
LVDS M-PHYLow Voltage Differential Signal for MIPI CSI-3 cameras
LVDS LCDLow Voltage Differential Signal for LCD displays
LVDS PCIELow Voltage Differential Signal for PCIe
LVDS SATALow Voltage Differential Signal for SATA
TMDS HDMITransition Minimized Differential Signal for HDMI displays
USBDC coupled differential signaling for traditional (non-Superspeed) USB signals
USB SSDifferential signal for SuperSpeed USB signals
USB VBUS 5V5V tolerant input for USB VBUS detection
3.3V3.3V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
1.8V1.8V Power Domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)
3.3Vsb3.3V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
1.8Vsb1.8V Power Domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)
# 4.3 Signal Description by function # 4.3.1 The First Display Interface The first display interface is a group of 30-pins that is split into a channel 0 and channel 1. The SMARC specification allows to support either dual channel LVDS ports, 2 separate single channel LVDS ports, 2 MIPI DSI ports of 4 lanes each or 2 eDP ports 4 lanes each. A mix of different display type such as DSI and eDP is also permitted. Below tables show which display ports are supported on this particular module Signals not supported are strikethrough
Pin #LVDS NameMIPI DSI NameeDP Name
S125LVDS0_0+DSI0_D0+eDP0_TX0+
S126LVDS0_0-DSI0_D0-eDP0_TX0-
S128LVDS0_1+DSI0_D1+eDP0_TX1+
S129LVDS0_1 -DSI0_D1-eDP0_TX1-
S131LVDS0_2+DSI0_D2+eDP0_TX2+
S132LVDS0_2-DSI0_D2-eDP0_TX2-
S137LVDS0_3+DSI0_D3+eDP0_TX3+
S138LVDS0_3-DSI0_D3-eDP0_TX3-
S134LVDS0_CK+DSI0_CLK+eDP0_AUX+
S135LVDS0_CK-DSI0_CLK-eDP0_AUX-
S133LCD0_VDD_ENLCD0_VDD_ENLCD0_VDD_EN
S127LCD0_BKLT_ENLCD0_BKLT_ENLCD0_BKLT_EN
S141LCD0_BKLT_PWMLCD0_BKLT_PWMLCD0_BKLT_PWM
S144DSI0_TEeDP0_HPD
S139I2C_LCD_CKI2C_LCD_CKI2C_LCD_CK
S140I2C_LCD_DATI2C_LCD_DATI2C_LCD_DAT
Pin #LVDS NameMIPI DSI NameeDP Name
S111LVDS1_0+DSI1_D0+eDP1_TX0+
S112LVDS1_0-DSI1_D0-eDP1_TX0-
S114LVDS1_1+DSI1_D1+eDP1_TX1+
S115LVDS1_1 -DSI1_D1-eDP1_TX1-
S117LVDS1_2+DSI1_D2+eDP1_TX2+
S118LVDS1_2-DSI1_D2-eDP1_TX2-
S120LVDS1_3+DSI1_D3+eDP1_TX3+
S121LVDS1_3-DSI1_D3-eDP1_TX3-
S108LVDS1_CK+DSI1_CLK+eDP1_AUX+
S109LVDS1_CK-DSI1_CLK-eDP1_AUX-
S116LCD1_VDD_ENLCD1_VDD_ENLCD1_VDD_EN
S107LCD1_BKLT_ENLCD1_BKLT_ENLCD1_BKLT_EN
S122LCD1_BKLT_PWMLCD1_BKLT_PWMLCD1_BKLT_PWM
S113DSI1_TEeDP1_HPD
Note : LVDS0/LVDS1 are optional supported on the module by means of a DSI to LVDS bridge Note : DSI0 can be used, this will disable the LVDS0 port, DSI1 is not supported 4.3.1.1 LVDS0/LVDS1 mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
LVDS0_0+S125Primary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS0_0-S126
LVDS0_1+S128
LVDS0_1 -S129
LVDS0_2+S131
LVDS0_2-S132
LVDS0_3+S137
LVDS0_3-S138
LVDS0_CK+S134Primary LVDS channel differential pair clock linesO LVDS LCDRuntime
LVDS0_CK-S135
LCD0_VDD_ENS133Primary LVDS channel power enable, active highO CMOS1.8VRuntime
LCD0_BKLT_ENS127Primary LVDS channel backlight enable, active highO CMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary LVDS channel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
LVDS1_0+S111Secondary LVDS channel differential pair data linesO LVDS LCDRuntime
LVDS1_0-S112
LVDS1_1+S114
LVDS1_1 -S115
LVDS1_2+S117
LVDS1_2-S118
LVDS1_3+S120
LVDS1_3-S121
LVDS1_CK+S108Secondary LVDS channel differential pair clock lines.O LVDS LCDRuntime
LVDS1_CK-LCD1_VDD_ENS109S116
Secondary panel power enable, active highO CMOS1.8VRuntime
LCD1_BKLT_ENS107Secondary panel backlight enable, active highO CMOS1.8VRuntime
LCD1_BKLT_PWMS122Secondary panel brightness control through pulse width modulation (PWM)O CMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
4.3.1.2 DSI mode
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
DSI0_D0+S125Primary DSI panel differential pair data linesO LVDSD-PHYRuntimeBuild option
DSI0_D0-S126
DSI0_D1+S128
DSI0_D1-S129
DSI0_D2+S131
DSI0_D2-S132
DSI0_D3+S137
DSI0_D3-S138
DSI0_CLK+S134Primary DSI panel differential pair clock lines.O LVDSD-PHYRuntimeBuild option
DSI0_CLK-S135
LCD0_VDD_ENS133Primary panel power enable, active highOCMOS1.8VRuntime
LCD0_BKLT_ENS127Primary panel backlight enable, active highOCMOS1.8VRuntime
LCD0_BKLT_PWMS141Primary panel brightness control through pulse width modulation (PWM)OCMOS1.8VRuntime
DSI0_TES144Primary DSI panel tearing effect signalICMOS1.8VRuntime
I2C_LCD_DATS140DDC data line used for flat panel detection and controlI/O OD CMOS1.8VRuntimePU 2k2
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlO OD CMOS1.8VRuntimePU 2k2
![This image displays a red icon of a document or note with a folded bottom-right corner. Inside the shape, centered on a white background, are two horizontal lines.](.smarc-lec-imx8mm-user-s-guide-rev06/094532d9522de11d48128abd605f8228fa31e69208d54f28d5072b1509bbbf2b.jpg) Note: Default output is DSI 4.3.2 MIPI Camera support (CSI1-4Lane)
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CSI1_RX0+P7CSI1 differential input (point to point)I LVDS D-PHY / I LVDS M-PHYRuntime
CSI1_RX0-P8
CSI1_RX1+P10
CSI1_RX1-P11
CSI1_RX2+P13
CSI1_RX2-P14
CSI1_RX3+P16
CSI1_RX3-P17
CSI1_CK+P3CSI1 differential clock input (point to point)I LVDS D-PHYRuntime
CSI1_CK-P4
I2C_CAM1_DAT / CSI1_TX-S2I2C data for serial camera data support link or differential data laneI/O OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_DAT MIPI-CSI 3.0 mode uses CSI1_TX-
I2C_CAM1_CK / CSI1_TX+S1I2C clock for serial camera data support link or differential data laneO OD CMOS / O LVDS M-PHY1.8VRuntimePU 2.2KMIPI-CSI 2.0 mode uses I2C_CAM1_CK MIPI-CSI 3.0 mode uses CSI1_TX+
CAM1_PWR# / GPIO1P109Camera 0 Power Enable, active low output.O CMOS1.8VRuntimeCAM1_PWR# is default, GPIO1 can be enabled through DVT
CAM1_RST# / GPIO3P111Camera 0 reset, active low outputO CMOS1.8VRuntimeCAM1_PWR# is default, GPIO3 can be enabled through DVT
CAM_MCKS6Master clock outputO CMOS1.8VRuntimeThis signal is used by both CSI0 and CSI1
4.3.3 I2S (audio)
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2S0_LRCKS39I2S0 Left & Right synchronization clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S0_SDOUTS40I2S0 Digital audio OutputO CMOS1.8VRuntime
I2S0_SDINS41I2S0 Digital audio InputI CMOS1.8VRuntime
I2S0_CKS42I2S0 Digital audio clockI/O CMOS1.8VRuntimeModule Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_LRCKS50I2S2 Left & Right synchronization clockI/O CMOS1.8VRuntime-Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
I2S2_SDOUTS51I2S2 Digital audio OutputO CMOS1.8VRuntime--
I2S2_SDINS52I2S2 Digital audio InputI CMOS1.8VRuntime--
I2S2_CKS53I2S2 Digital audio clockI/O CMOS1.8VRuntime-Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode
AUDIO_MCKS38Master clock output to I2S codec(s)O CMOS1.8VRuntime--
![The image shows a red icon resembling a document or piece of paper with a curled bottom-right corner. Inside the white area, there are two thick, horizontal red lines stacked vertically, resembling an equals sign.](.smarc-lec-imx8mm-user-s-guide-rev06/52276b7be1bd8775a445b3d278bc28af0368c76a85b83a26529590e5e188539b.jpg) Note: support for I2S1 signalling pins has been removed during update to SMARC 2.0 specification 4.3.4 USB ports
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
USB0+USB0-P60P61USB differential data pairs for port 0I/OUSBUSBRuntimeFrom SOC
USB0_EN_OC#P62USB over-current sense for port 0I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB0_VBUS_DETP63USB port 0 host power detection, when this port is used as a device.I USBVBUS 5VUSB VBUS 5VRuntimeCan be connected to a USB client port VBUS pin
USB0_OTG_IDP64Input pin to announce OTG device insertion on USB 2.0 portICMOS3.3Vsb / 3.3VRuntime
USB1+USB1-P65P66USB differential data pairs for port 1I/OUSBUSBRuntimeFrom USB HUB
USB1_EN_OC#P67USB over-current sense for port 1I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB2+USB2-P69P70USB differential data pairs for port 2I/OUSBUSBRuntimeFrom USB HUB
USB2_SSRX+USB2_SSRX-S74S75Receive signal differential pairs for SuperSpeed on port 2IUSB SSUSB SSRuntime-
USB2_SSTX+USB2_SSTX-S71S72Transmit signal differential pairs for SuperSpeed on port 2OUSB SSUSB SSRuntime-
USB2_EN_OC#P71USB over-current sense for port 2I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB3+USB3-S68S69USB differential data pairs for port 3I/OUSBUSBRuntimeFrom USB HUB
USB3_SSRX+USB3_SSRX-S65S66Receive signal differential pairs for SuperSpeed on port 3↑USB_SSUSB_SSRuntime
USB3_SSTX+USB3_SSTX-S62S63Transmit signal differential pairs for SuperSpeed on port 3QUSB_SSUSB_SSRuntime
USB3_EN_OC#P74USB over-current sense for port 3I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB3_VBUS_DETS37USB port 3 host power detection, when this port is used as a device.↑USB_VBUS5VUSBV_BUS 5VRuntime--
USB3_OTG_IDS104Input pin to announce OTG device insertion on USB 3.0 port↓CMOS3.3Vsb / 3.3VRuntime--
USB4+USB4-S35S36USB differential data pairs for port 4I/OUSBUSBRuntime
USB4_EN_OC#P76USB over-current sense for port 4I/O ODCMOS3.3Vsb / 3.3VRuntimePU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
USB5+USB5-S59S60USB differential data pairs for port 5I/OUSBUSBStandby--
USB5_EN_OC#S55USB over-current sense for port 5I/O ODCMOS3.3Vsb / 3.3VStandbyPU 10kPulled low by Module OD driver to disable USB0 power. Pulled low by Carrier OD driver to indicate over-current situation.
![A red icon depicting a square document with a folded bottom-right corner. Inside the square are two horizontal red lines centered vertically, representing text.](.smarc-lec-imx8mm-user-s-guide-rev06/c837f111df751bde9f011884644959c78e1c77ae63b34e9b33cd1916eeeca10b.jpg) Note: By default only USB0 and 1 are available, optional HUB brings USB2,3,4 to the SMARC connector # 4.3.5 PCIe Ports The module supports one PCIe Gen 2.1 ports (PCIE\_A).
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
PCIE_A_TX+PCIE_A_TX-P89P90Differential PCIe link A transmit data pairO LVDSPCIERuntimeSeries AC coupled on module
PCIE_A_RX+PCIE_A_RX-P86P87Differential PCIe link A receive data pairI LVDSPCIERuntimeSeries AC coupled off module
PCIE_A_REFCK+PCIE_A_REFCK-P83P84Differential PCIe Link A reference clock outputO LVDSPCIERuntime
PCIE_A_RST#P75PCIe Port A reset outputOCMOS3.3VRuntime
PCIE_A_CKREQ#P78PCIe Port A clock requestIODCMOS3.3VRuntime-No need for this signal because module provides onboard PCIe clock
![The image displays a red icon of a document or page with a folded bottom-right corner. Inside the red border, there are three horizontal red lines representing text.](.smarc-lec-imx8mm-user-s-guide-rev06/a5ff603d3ecbc8189860388fdade1365a248c68c93999d23622babe2576fb69f.jpg) Note: Module provides PCIe clock generators for PCIE\_A so no external clock source on the carrier is needed # 4.3.6 LAN ports # 4.3.6.1 First LAN port The first LAN port is derived from the SOCs RGMII interface
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE0_MDI0+P30Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:GBE MDIRuntimeTwisted pair signals for external transformer.
GBE0_MDI0-P29
GBE0_MDI1+P27
GBE0_MDI1-P26
GBE0_MDI2+P24
GBE0_MDI2-P231000 100 10
GBE0_MDI3+P20MDI[0]+/- B1_DA+/- TX+/- TX+/-
GBE0_MDI3-P19MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
GBE0_LINK100#P21Link Speed Indication LED for GBE 0 100MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_LINK1000#P22Link Speed Indication LED for GBE 0 1000MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_LINK_ACT#P25Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on ActivityO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE0_CTREFP28Center-Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)Analog0 to 3.3V maxRuntime--
GBE0_SDPP6IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VRuntime
# 4.3.6.2 Second LAN port The Second LAN port is derived from RTL8119i PCIe ethernet controller
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GBE1_MDI0+S17Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:GBE MDIRuntimeTwisted pair signals for external transformer.
GBE1_MDI0-S18
GBE1_MDI1+S20
GBE1_MDI1-S21
GBE1_MDI2+S23
GBE1_MDI2-S241000 100 10MDI[0]+/- B1_DA+/- TX+/- TX+/-MDI[1]+/- B1_DB+/- RX+/- RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-
GBE1_MDI3+S26
GBE1_MDI3-S27
GBE1_LINK100#S19Link Speed Indication LED for GBE 1 100MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_LINK1000#S22Link Speed Indication LED for GBE 1 1000MbpsO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_LINK_ACT#S31Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on ActivityO OD CMOS3.3VRuntimeShall be able to sink 24mA or more Carrier LED current
GBE1_CTREFS28Center-Tap reference voltage for Carrier board Ethernet magnetic `(if required by the Module GBE PHY)`Analog0 to 3.3V maxRuntime
GBE1_SDPP5IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)IO CMOS3.3VRuntime
![The image displays a red outline icon of a document or page with a folded bottom-right corner. Inside the white area, there are two horizontal red lines centered vertically, resembling text or a list.](.smarc-lec-imx8mm-user-s-guide-rev06/0e299a1ec2cc2001cc7644952cbcdc80275578558f7bb2016a9354153e046ec8.jpg) Note: Adding the optional 2nd LAN will remove PCIe A 4.3.7 SDIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SDIO_D0P39SDIO Data lines. These signals operate in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_D1P40
SDIO_D2P41
SDIO_D3P42
SDIO_WPP33SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CMDP34SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.I/O CMOS1.8V or 3.3VRuntimeSDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly
SDIO_CD#P35SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.I OD CMOS3.3VRuntimePU 10kPulled up on module
SDIO_CKP36SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.O CMOS1.8V or 3.3VRuntime
SDIO_PWR_ENP37SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.O CMOS3.3VRuntimeshould be driven low in STB Mode by the module
# 4.3.8 SPI & ESPI # 4.3.9 SPI0
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SPI0_CS0#P43SPI0 Master Chip Select 0O CMOS1.8VStandbyThis signal can be used to select carrier SPI as boot device
SPI0_CS1#P31SPI0 Master Chip Select 1O CMOS1.8VStandby
SPI0_CKP44SPI0 ClockO CMOS1.8VStandby
SPI0_DINP45SPI0 Master input / Slave outputI CMOS1.8VStandbyalso referred to as MISO
SPI0_DOP46SPI0 Master output / Slave inputO CMOS1.8VStandbyalso referred to as MOSI
SPI1_CS0#P54SPI1 Master Chip Select 0O CMOS1.8VStandby-See ESPI
SPI1_CS1#P55SPI1 Master Chip Select 1O CMOS1.8VStandby-See ESPI
SPI1_CKP56SPI1 ClockO CMOS1.8VStandby-See ESPI
SPI1_DINP57SPI1 Master input / Slave outputI CMOS1.8VStandby-See ESPI
SPI1_DOP58SPI1 Master output / Slave inputO CMOS1.8VStandby-See ESPI
![The image displays a small, pixelated icon resembling a document or note. It features a thick, red outline of a square shape with the bottom-right corner folded upwards. Inside the white area, there are two horizontal lines centered vertically, resembling an equals sign.](.smarc-lec-imx8mm-user-s-guide-rev06/65356ff00f68ce2db1b84f0309a3cc2bd29cc464b911d8be8cd62d33e8dd3a82.jpg) Note: SPI0/1 is free to use on the carrier 4.3.10 ESPI
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
ESPI_CS0#P54ESPI1 Master Chip Select 0O CMOS1.8VStandby-
ESPI_CS1#P55ESPI1 Master Chip Select 1O CMOS1.8VStandby-
ESPI_CKP56ESPI Master Clock outputO CMOS1.8VStandby-
ESPI_RESET#S58ESPI ResetO CMOS1.8VStandby-Reset the eSPI interface for both master and slaves.eSPI Reset# is typically driven from eSPI master to eSPI slaves
ESPI_ALERT0#ESPI_ALERT1#S43S44ESPI ALERTI ODCMOS1.8VStandby-This pin is used by eSPI slave to request service from eSPI.master.Alert# is an open-drain output from the slave.This pin is optional for Single Master-Single Slave configuration where I/O[1] can be used to signal the Alert event.
ESPI_IO_0ESPI_IO_1ESPI_IO_2ESPI_IO_3P58P57S56S57ESPI Master Data Input / Output.-I/O CMOS1.8VStandby-ESPI_IO_0 can also be used as SPI1_DO (MOSI)ESPI_IO_1 can also be used as SPI1_DIN (MISO)In Single I/O mode, ESPI_IO_0 is the eSPI master output / eSPI-slave input (MOSI) whereas ESPI_IO_1 is the SPI master input / eSPI-slave output (MISO).
![The image displays a red icon resembling a square document or note with the bottom right corner folded over (a 'dog-ear'). Inside the shape, there are two horizontal parallel lines centered within the upper portion.](.smarc-lec-imx8mm-user-s-guide-rev06/c00a2f25f26479a7f74ea23ca932e17bd865c3524161391f7998aa873f1698ce.jpg) Note: On NXP i.MX8M mini parts SPI is used # 2 General Purpose I2C The SMARC specification supports a total of 6 different I2C busses on its pinout. Most of these busses are designated for specific functions such as I2C for camera management, I2C for EDID on HDMI, LVDS panels or I2C for PMIC. Just one I2C bus is marked as General purpose
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
I2C_GP_DATS49General purpose I2C data signalI/O OD CMOS1.8VRuntimePU 2k2
I2C_GP_CKS48General purpose I2C clock signalO OD CMOS1.8VRuntimePU 2k2
Most of the other I2C busses are described in their designated function tables rather than in a single big list. Below is an overview of all I2C busses and where to find them.
NamePin #DescriptionWhere to find
I2C_LCD_DATS140DDC data line used for flat panel detection and controlLVDS / DSI / eDP tables
I2C_LCD_CKS139DDC clock line used for flat panel detection and controlLVDS / DSI / eDP tables
HDMI_CTRL_CKP105I2C_CLK line dedicated to HDMIHDMI table
HDMI_CTRL_DATP106I2C_DAT line dedicated to HDMIHDMI table
I2C_CAM0_DATS7I2C data for serial camera data support linkMIPI CSI table
I2C_CAM0_CKS5I2C clock for serial camera data support linkMIPI CSI table
I2C_CAM1_DATS2I2C data for serial camera data support linkMIPI CSI table
I2C_CAM1_CKS1I2C clock for serial camera data support linkMIPI CSI table
I2C_PM_DATP122Power management I2C bus DATA (SMBus for x86)Power and System Management
I2C_PM_CKP121Power management I2C bus CLK (SMBus for x86)Power and System Management
4.4.1 GPIO
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
GPIO0 / CAM0_PWR#P108General purpose I/O pin 0.I/O CMOS1.8VRuntimePU 470K on the Module.Default use is GPIO0, alternative use is Camera 0 Power Enable - active low, through DTS
GPIO1 / CAM1_PWR#P109General purpose I/O pin 1.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is is GPIO1 alternative use is Camera 1 Power Enable - active low, through DTS
GPIO2 / CAM0_RST#P110General purpose I/O pin 2.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO2, alternative use is Camera 0 Reset - active low, through DTS
GPIO3 / CAM1_RST#P111General purpose I/O pin 3.I/O CMOS1.8VRuntimePU 470K on the ModuleDefault use is GPIO3, alternative use is Camera 1 Reset - active low, through DTS
GPIO4 / HDA_RST#P112General purpose I/O pin 4.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO5 / PWM_OUTP113General purpose I/O pin 5.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO6 / TACHINP114General purpose I/O pin 6.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO7P115General purpose I/O pin 7.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO8P116General purpose I/O pin 8.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO9P117General purpose I/O pin 9.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO10P118General purpose I/O pin 10.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO11P119General purpose I/O pin 11.I/O CMOS1.8VRuntimePU 470K on the Module
GPIO12S142General purpose I/O pin 12I/O CMOS1.8VRuntimePU 470K on the Module
GPIO13S123General purpose I/O pin 13I/O CMOS1.8VRuntimePU 470K on the Module
4.4.2 UART
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
SER0_TXP129Asynchronous serial data output port 0O CMOS1.8VRuntime
SER0_RXP130Asynchronous serial data input port 0I CMOS1.8VRuntime
SER0_RTS#P131"Request to Send" handshake line for port 0O CMOS1.8VRuntime
SER0_CTS#P132"Clear to Send" handshake line for port 0I CMOS1.8VRuntime
SER1_TXP134Asynchronous serial data output port 1O CMOS1.8VRuntime
SER1_RXP135Asynchronous serial data input port 1I CMOS1.8VRuntime
SER2_TXP136Asynchronous serial data output port 2O CMOS1.8VRuntime--
SER2_RXP137Asynchronous serial data input port 2I CMOS1.8VRuntime--
SER2_RTS#P138"Request to Send" handshake line for port 2O CMOS1.8VRuntime--
SER2_CTS#P139"Clear to Send" handshake line for port 2I CMOS1.8VRuntime--
SER3_TXP140Asynchronous serial data output port 3O CMOS1.8VRuntime-
SER3_RXP141Asynchronous serial data input port 3I CMOS1.8VRuntime-
4.4.3 CAN bus
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
CAN0_TXP143CAN port 0 Transmit outputO CMOS1.8VRuntime
CAN0_RXP144CAN port 0 Receive inputI CMOS1.8VRuntime
4.4.4 Miscellaneous
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
TEST#S157Held low by Carrier to invoke Module vendor specific test function(s).ICMOS1.8VRuntimePU on Module. Driven by OD on CarrierModule must implement PU but actual value is depended on particular module design. Carrier Board should leave this pin floating for normal operation
WDT_TIME_OUT#S145Watch-Dog-Timer Output, low active.OCMOS1.8VRuntimeDriven only during runtime
4.4.5 Power and System Management
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BATLOW#S156Battery low indication to Module. Carrier to float the line in inactive state.I OD CMOS1.8VRuntimePU 10KDriven by OD on Carrier. Pulled up on module.
CARRIER_PWR_ONS154Carrier board circuits (apart from power management and power path circuits) should not be powered up until the Module asserts the CARRIER_PWR_ON signal.O CMOS1.8Vsb / 1.8V-1.8Vsb is only used for signaling, not a power source to the module
CARRIER_STBY#S153The Module shall drive this signal low when the system is in a standby power state.O CMOS1.8Vsb / 1.8V-
CHARGER_PRSNT#S152Held low by Carrier if DC input for battery charger is present.I OD CMOS1.8VRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
CHARGING#S151Held low by Carrier during battery charging. Carrier to float the line when charge is complete.I OD CMOS1.8VRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
VIN_PWR_BAD#S150Power bad indication from Carrier board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall not be enabled while this signal is held low by the Carrier.I OD CMOS1.8VRuntimePU 2.2KDriven by OD on Carrier Module must implement PU but actual value is depended on particular module design.
SLEEP#S149Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state.Active low, level sensitive. Should be de-bounced on the Module.I OD CMOS1.8VRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
LID#S148Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.I OD CMOS1.8VRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
POWER_BTN#P128Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.I OD CMOS1.8VRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
RESET_OUT#P126General purpose reset output to Carrier board.O CMOS1.8VRuntime
RESET_IN#P127Reset input from Carrier board. Carrier drives low to force a Module reset, floats the line otherwise.I OD CMOS1.8VRuntimePU 4.7KDriven by OD on Carrier. Pulled up on module.
I2C_PM_DATP122Power management I2C bus DATAI/O OD CMOS1.8VRuntimePU 2k2On x86 systems these serve as SMB DATA. Pulled up on module.
I2C_PM_CKP121Power management I2C bus CLKO OD CMOS1.8VRuntimePU 2k2On x86 systems these serve as SMB CLK. Pulled up on module.
SMB_ALERT_1V8#P1SMBus Alert# (interrupt) signalI OD CMOS1.8VRuntimePU 2k2only used on x86 design
4.4.6 Boot Select
NamePin #DescriptionI/O TypeI/O LevelPower DomainPU / PDComments
BOOT_SEL0#P123Input straps determine the Module bootI OD CMOS1.8VsbStandbyPU 4.7KDriven by OD on Carrier.Pulled up on module.Only booting from EMMc and SDcard is supported
BOOT_SEL1#P124
BOOT_SEL2#P125
FORCE_RECOV#S155I OD CMOS1.8VsbStandbyPU 10KDriven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.
4.4.7 Power
NamePin #DescriptionI/O TypePower Rail / TolerancePU / PDComments
VDD_INP147, P148, P149, P150, P151, P152, P153, P154, P155, P156Module power input voltage 4.75 min to 5.25V maxP Not defined within Signal Terminology Descriptions. Should we define a specific rail?4.75 to 5.25V / 5V
GNDP2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158Module signal and power return, and GND referenceP Not defined within Signal Terminology Descriptions. Should we define a specific rail?Ground
VDD_RTCS147Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.P Not defined within Signal Terminology Descriptions. Should we define a specific rail?[2 to 3.25] / 3.25V
4.5 SMARC pin to controller mapping
PinSMARC Signal NameModule DirectionModule TerminationType/ToleranceControllerController Pin NameI/O Mux defaultPower Rail
P1SMB_ALERT_1V8#In-GPIO / 1.8Vi.MX8M MiniSAI5_RXC-NVCC_SAI1_SAI5
P2GND-------
P3CSI1_CK+In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_CLK_P-CSI_P2_VDDHA
P4CSI1_CK-In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_CLK_N-CSI_P2_VDDHA
P5GBE1_SDPOut-GPIO/3.3VRTL8119iCLK_OUT
P6GBE0_SDPOut-GPIO/3.3VDM9119INXCLK_OUT
P7CSI1_RX0+In-LVDS D-PHYSN65DSI84ZXHRMIPI_CSI2_D0_P-CSI_P2_VDDHA
P8CSI1_RX0-In-LVDS D-PHYSN65DSI84ZXHRMIPI_CSI2_D0_N-CSI_P2_VDDHA
P9GND-----
P10CSI1_RX1+In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_D1_P-CSI_P2_VDDHA
P11CSI1_RX1-In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_D1_N-CSI_P2_VDDHA
P12GND-----
P13CSI1_RX2+In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_D2_P-CSI_P2_VDDHA
P14CSI1_RX2-In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_D2_N-CSI_P2_VDDHA
P15GND-----
P16CSI1_RX3+In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_D3_P-CSI_P2_VDDHA
P17CSI1_RX3-In-LVDS D-PHYi.MX8M MiniMIPI_CSI2_D3_N-CSI_P2_VDDHA
P18GND-------
P19GBE0_MDI3-Bi-Dir-GBE MDIDM9119INXTD_M_D-VDDIO
P20GBE0_MDI3+Bi-Dir-GBE MDIDM9119INXTD_P_D-VDDIO
P21GBE0_LINK100#Out/OD-GPIO / 3.3VDM9119INXLED_1-VDDIO
P22GBE0_LINK1000#Out/OD-GPIO / 3.3VDM9119INXLED_2-VDDIO
P23GBE0_MDI2-Bi-Dir-GBE MDIDM9119INXTD_M_C-VDDIO
P24GBE0_MDI2+Bi-Dir-GBE MDIDM9119INXTD_P_C-VDDIO
P25GBE0_LINK_ACT#Out/OD-GPIO / 3.3VDM9119INXLED_0-VDDIO
P26GBE0_MDI1-Bi-Dir-GBE MDIDM9119INXTD_M_B-VDDIO
P27GBE0_MDI1+Bi-Dir-GBE MDIDM9119INXTD_P_B-VDDIO
P28GBE0_CTREFPWR------
P29GBE0_MDIO-Bi-Dir-GBE MDIDM9119INXTD_M_A-VDDIO
P30GBE0_MDIO+Bi-Dir-GBE MDIDM9119INXTD_P_A-VDDIO
P31SPI0_CS1#---N.C.N.C.--
P32GND-------
P33SDIO_WPIn-SD2 / 3.3Vi.MX8M MiniSD2_WPALTONVCC_SD2
P34SDIO_CMDBi-Dir-SD2 / 3.3Vi.MX8M MiniSD2_CMDALTONVCC_SD2
P35SDIO_CD#In-SD2 / 3.3Vi.MX8M MiniSD2_CDALTONVCC_SD2
P36SDIO_CKOut-SD2 / 3.3Vi.MX8M MiniSD2_CLKALTONVCC_SD2
P37SDIO_PWR_ENOut-GPIO / 3.3Vi.MX8M MiniGPIO1_IO12ALTONVCC_GPIO1
P38GND-----
P39SDIO_D0Bi-Dir-SD2 / 3.3Vi.MX8M MiniSD2_DATA0ALTONVCC_SD2
P40SDIO_D1Bi-Dir-SD2 / 3.3Vi.MX8M MiniSD2_DATA1ALTONVCC_SD2
P41SDIO_D2Bi-Dir-SD2 / 3.3Vi.MX8M MiniSD2_DATA2ALTONVCC_SD2
P42SDIO_D3Bi-Dir-SD2 / 3.3Vi.MX8M MiniSD2_DATA3ALTONVCC_SD2
P43SPI0_CS0#Out-SPI / 1.8Vi.MX8M MiniECSPI2_SS0ALTONVCC_ECSPI
P44SPI0_CKOut-SPI / 1.8Vi.MX8M MiniECSPI2_SCLKALTONVCC_ECSPI
P45SPI0_DINIn-SPI / 1.8Vi.MX8M MiniECSPI2_MISOALTONVCC_ECSPI
P46SPI0_DOOut-SPI / 1.8Vi.MX8M MiniECSPI2_MOSIALTONVCC_ECSPI
P47GND-------
P48SATA_TX+---N.C.N.C.--
P49SATA_TX----N.C.N.C.--
P50GND-------
P51SATA_RX+---N.C.N.C.--
P52SATA_RX----N.C.N.C.--
P53GND-------
P54ESPI_CS0# / SPI1_CS0#Out-SPI / 1.8Vi.MX8M MiniECSPI1_SS0ALTONVCC_ECSPI
P55ESPI_CS1# / SPI1_CS1#---N.C.N.C.--
P56ESPI_CK / SPI1_CKOut-SPI / 1.8Vi.MX8M MiniECSPI1_SCLKALTONVCC_ECSPI
P57ESPI_IO_1 / SPI1_DINIn-SPI / 1.8Vi.MX8M MiniECSPI1_MISOALTONVCC_ECSPI
P58ESPI_IO_0 / SPI1_DOOut-SPI / 1.8Vi.MX8M MiniECSPI1_MOSIALTONVCC_ECSPI
P59GND-----
P60USB0+Bi-Dir-USBi.MX8M MiniUSB1_DPUSB1_VDD33
P61USB0-Bi-Dir-USBi.MX8M MiniUSB1_DNUSB1_VDD33
P62USB0_EN_OC#InPU-10KGPIO / 3.3Vi.MX8M MiniGPIO1_IO13ALT0NVCC_GPIO1
P63USB0_VBUS_DETPWR-USBi.MX8M MiniUSB1_VBUS-USB1_VDD33
P64USB0_OTG_IDIn-USBi.MX8M MiniUSB1_ID-USB1_VDD33
P65USB1+Bi-Dir-USBUSB Hub (USB2514B)DS4_DP-AVDD33
P66USB1-Bi-Dir-USBUSB Hub (USB2514B)DS4_DM-AVDD33
P67USB1_EN_OC#In-GPIO / 3.3VUSB Hub USB2514B)DS4_OVRCURR-AVDD33
P68GND-----
P69USB2+Bi-Dir-PHYUSB Hub (USB2514B)DS0_DP-AVDD33
P70USB2-Bi-Dir-PHYUSB Hub (USB2514B)DS0_DM-AVDD33
P71USB2_EN_OC#In-GPIO / 3.3VUSB Hub (USB2514B)DS0_OVRCURR-AVDD33
P72RSVD---N.C.N.C.
P73RSVD---N.C.N.C.
P74USB3_EN_OC#In-GPIO / 3.3VUSB Hub (USB2514B)DS1_OVRCURR-AVDD33
P75PCIE_A_RST#Out-GPIO / 3.3Vi.MX8M MiniSAI1_TXCALT5NVCC_SAI1
P76USB4_EN_OC#In-GPIO / 3.3VUSB Hub (USB2514B)DS3_OVRCURR-AVDD33
P77PCIE_B_CREQ#---N.C.N.C.--
P78PCIE_A_CREQ#---N.C.N.C.--
P79GND-------
P80PCIE_C_REFCK+Out--N.C.N.C.--
P81PCIE_C_REFCK-Out--N.C.N.C.--
P82GND-------
P83PCIE_A_REFCK+OutSerial-0.1uFPCIe9FGV0241AKILFDIF3-VDDDIG1p8
P84PCIE_A_REFCK-OutSerial-0.1uFPCIe9FGV0241AKILFDIF3\-VDDDIG1p8
P85GND------
P86PCIE_A_RX+InSerial-0.1uFPCIei.MX8M MiniPCIE2_RXN_P-PCIE2_VPH
P87PCIE_A_RX-InSerial-0.1uFPCIei.MX8M MiniPCIE2_RXN_N-PCIE2_VPH
P88GND-------
P89PCIE_A_TX+OutSerial-0.1uFPCIei.MX8M MiniPCIE2_TXN_P-PCIE2_VPH
P90PCIE_A_TX-OutSerial-0.1uFPCIei.MX8M MiniPCIE2_TXN_N-PCIE2_VPH
P91GND-----
P92HDMI_D2+ / DP1_LANE0+Out-HDMINCHDMI_TX_P_LN_2-HDMI_AVDDIO
P93HDMI_D2- / DP1_LANE0-Out-HDMINCHDMI_TX_N_LN_2-HDMI_AVDDIO
P94GND-------
P95HDMI_D1+ / DP1_LANE1+Out-HDMINCHDMI_TX_P_LN_1HDMI_AVDDIO
P96HDMI_D1- / DP1_LANE1-Out-HDMINCHDMI_TX_N_LN_1HDMI_AVDDIO
P97GND-------
P98HDMI_D0+ / DP1_LANE2+Out-HDMINCHDMI_TX_P_LN_0-HDMI_AVDDIO
P99HDMI_D0- / DP1_LANE2-Out-HDMINCHDMI_TX_N_LN_0-HDMI_AVDDIO
P100GND-------
P101HDMI_CK+ / DP1_LANE3+Out-HDMINCHDMI_TX_P_LN_3-HDMI_AVDDIO
P102HDMI_CK- / DP1_LANE3-Out-HDMINCHDMI_TX_N_LN_3`HDMI_AVDDIO
P103GND-------
P104HDMI_HPD / DP1_HPDInHDMINCHDMI_HPD-HDMI_AVDDIO
P105HDMI_CTRL_CK / DP1_AUX+OutPU-2.2K / PD-100KHDMINCHDMI_DDC_SCL(H) HDMI_AUX(P(L))-HDMI_AVDDIO
P106HDMI_CTRL_DAT / DP1_AUX-Bi-DirPU-2.2K / PD-100KHDMINCHDMI_DDC_SDA(H) HDMI_AUX(N(L))-HDMI_AVDDIO
P107DP1_AUX_SELOutPD-1MHDMINC---
P108GPIO0 / CAM0_PWR#OutPU-470KGPIO / 1.8Vi.MX8M MINIGPIO1_IO03ALT0NVCC_GPIO1
P109GPIO1 / CAM1_PWR#OutPU-470KGPIO / 1.8Vi.MX8M MINIGPIO1_IO05ALT0NVCC_GPIO1
P110GPIO2 / CAM0_RST#OutPU-470KGPIO / 1.8Vi.MX8M MINIGPIO1_IO06ALT0NVCC_GPIO1
P111GPIO3 / CAM1_RST#OutPU-470KGPIO / 1.8Vi.MX8M MINIGPIO1_IO06ALT0NVCC_GPIO1
P112GPIO4 / HDA_RST#OutPU-470KGPIO / 1.8Vi.MX8M MINIP0_4-VDD_1V8
P113GPIO5 / PWM_OUTOutPU-470KGPIO / 1.8Vi.MX8M MINIP0_5-VDD_1V8
P114GPIO6 / TACHINInPU-470KGPIO / 1.8Vi.MX8M MINIP0_6-VDD_1V8
P115GPIO7InPU-470KGPIO / 1.8Vi.MX8M MINIP0_7-VDD_1V8
P116GPIO8InPU-470KGPIO / 1.8Vi.MX8M MINIP1_0-VDD_1V8
P117GPIO9InPU-470KGPIO / 1.8Vi.MX8M MINIP1_1-VDD_1V8
P118GPIO10InPU-470KGPIO / 1.8Vi.MX8M MINIP1_2-VDD_1V8
P119GPIO11InPU-470KGPIO / 1.8Vi.MX8M MINIP1_3-VDD_1V8
P120GND-----
P121I2C_PM_CKOutPU-2k2I2C2i.MX8M MiniI2C2_SCLALT0NVCC_I2C
P122I2C_PM_DATBi-DirPU-2k2I2C2i.MX8M MiniI2C2_SDAALT0NVCC_I2C
P123BOOT_SEL0#InPU-4k7GPIO / 1.8Vi.MX8M MiniPB0-+1V8SMC
P124BOOT_SEL1#InPU-4k7GPIO / 1.8Vi.MX8M MiniPB1-+1V8SMC
P125BOOT_SEL2#InPU-4k7GPIO / 1.8Vi.MX8M MiniPB2-+1V8SMC
P126RESET_OUT#Out-GPIO / 1.8Vi.MX8M MiniPB15-+1V8SMC
P127RESET_IN#InPU-4K7GPIO / 1.8Vi.MX8M MiniPB14-+1V8SMC
P128POWER_BTN#InPU-4K7GPIO / 1.8Vi.MX8M MiniPB4-+1V8SMC
P129SER0_TXOut-UART / 1.8Vi.MX8M MiniUART2_TXDALT5NVCC_UART
P130SER0_RXIn-UART / 1.8Vi.MX8M MiniUART2_RXDALT5NVCC_UART
P131SER0_RTS#In-UART / 1.8Vi.MX8M MiniSD1_DATA4ALT1NVCC_SD1
P132SER0_CTS#Out-UART / 1.8Vi.MX8M MiniSD1_DATA5ALT1NVCC_SD1
P133GND-------
P134SER1_TXOut-UART / 1.8Vi.MX8M MiniNAND_CE0_BALT1NVCC_NAND
P135SER1_RXIn-UART / 1.8Vi.MX8M MiniNAND_ALEALT1NVCC_NAND
P136SER2_TXOut-UART / 1.8Vi.MX8M MiniUART4_TXDALT5NVCC_UART
P137SER2_RXIn-UART / 1.8Vi.MX8M MiniUART4_RXDALT5NVCC_UART
P138SER2_RTS#In-UART / 1.8Vi.MX8M MiniNAND_DATA03ALT1NVCC_NAND
P139SER2_CTS#Out-UART / 1.8Vi.MX8M MiniNAND_DATA02ALT4NVCC_NAND
P140SER3_TXOut-UART / 1.8Vi.MX8M MiniUART1_TXDALT5NVCC_UART
P141SER3_RXIn-UART / 1.8Vi.MX8M MiniUART1_RXDALT5NVCC_UART
P142GND-------
P143CAN0_TXOut-CANi.MX8M MiniTXCAN-VDD_3V3
P144CAN0_RXIn-CANi.MX8M MiniRXCAN-VDD_3V3
P145CAN1_TX--CANi.MX8M MiniTXCANVDD_3V3
P146CAN1_RX--CANi.MX8M MiniRXCANVDD_3V3
P147VDD_INPWR--From Carrier board--3 ~ 5.25 V
P148VDD_INPWR--From Carrier board--3 ~ 5.25 V
P149VDD_INPWR--From Carrier board--3 ~ 5.25 V
P150VDD_INPWR--From Carrier board--3 ~ 5.25 V
P151VDD_INPWR--From Carrier board--3 ~ 5.25 V
P152VDD_INPWR--From Carrier board--3 ~ 5.25 V
P153VDD_INPWR--From Carrier board--3 ~ 5.25 V
P154VDD_INPWR--From Carrier board--3 ~ 5.25 V
P155VDD_INPWR--From Carrier board--3 ~ 5.25 V
P156VDD_INPWR--From Carrier board--3 ~ 5.25 V
S1CSI1_TX+ / I2C_CAM1_CKInPU-2k2I2C3i.MX8M MiniI2C3_SCLALTONVCC_I2C
S2CSI1_TX- / I2C_CAM1_DATInPU-2k2I2C3i.MX8M MiniI2C3_SDAALTONVCC_I2C
S3GND-------
S4RSVDIn--N.C.N.C.--
S5CSI0_TX- / I2C_CAM0_CKOutPU-2k2I2C4N.C.I2C4_SCLALTONVCC_I2C
S6CAM_MCKOut-GPIO / 1.8VN.C.GPIO1_IO15ALT5NVCC_GPIO1
S7CSI0_TX+ / I2C_CAM0_DATBi-DirPU-2k2I2C4N.C.I2C4_SDAALTONVCC_I2C
S8CSI0_CK+In-MIPI-CSIN.C.MIPI_CSI1_CLK_P-MIPI_CSI1_VDDHA
S9CSI0_CK-In-MIPI-CSIN.C.MIPI_CSI1_CLK_N-MIPI_CSI1_VDDHA
S10GND-------
S11CSI0_RX0+In-MIPI-CSIN.C.MIPI_CSI1_D0_P-MIPI_CSI1_VDDHA
S12CSI0_RX0-In-MIPI-CSIN.C.MIPI_CSI1_D0_N-MIPI_CSI1_VDDHA
S13GND-------
S14CSI0_RX1+In-MIPI-CSIN.C.MIPI_CSI1_D1_P-MIPI_CSI1_VDDHA
S15CSI0_RX1-In-MIPI-CSIN.C.MIPI_CSI1_D1_N-MIPI_CSI1_VDDHA
S16GND-------
S17GBE1_MDIO+Bi-Dir-GBE MDIRTL8119iTD_M_D--
S18GBE1_MDIO-Bi-Dir-GBE MDIRTL8119iTD_P_D--
S19GBE1_LINK100#Out-GPIO / 3.3VRTL8119iLED_1--
S20GBE1_MDI1+Bi-Dir-GBE MDIRTL8119iLED_2--
S21GBE1_MDI1-Bi-Dir-GBE MDIRTL8119iTD_M_C--
S22GBE1_LINK1000#Out-GPIO / 3.3VRTL8119iTD_P_C--
S23GBE1_MDI2+Bi-Dir-GBE MDIRTL8119iLED_0--
S24GBE1_MDI2-Bi-Dir-GBE MDIRTL8119iTD_M_B--
S25GND-------
S26GBE1_MDI3+Bi-Dir-GBE MDIRTL8119iMDI_PLUS[3]--
S27GBE1_MDI3-Bi-Dir-GBE MDIRTL8119iMDI_MINUS[3]--
S28GBE1_CTREF---N.C.N.C.--
S29PCIE_D_TX+ / SERDES_1_TX+---N.C.N.C.--
S30PCIE_D_TX- / SERDES_1_TX----N.C.N.C.--
S31GBE1_LINK_ACT#Out-GPIO / 3.3VRTL8119iLED1--
S32PCIE_D_RX+ / SERDES_1_RX+---N.C.N.C.--
S33PCIE_D_RX- / SERDES_1_RX----N.C.N.C.--
S34GND-----
S35USB4+Bi-Dir-USBUSB Hub USB2514B)DS3_DP--
S36USB4-Bi-Dir-USBUSB Hub (USB2514B)DS3_DM--
S37USB3_VBUS_DET---N.C.N.C.--
S38AUDIO_MCKOut-SAI / 1.8Vi.MX8M MiniSAI2_MCLKALT0NVCC_SAI2
S39I2S0_LRCKBi-Dir-SAI / 1.8Vi.MX8M MiniSAI2_TXFSALT0NVCC_SAI2
S40I2S0_SDOUTOut-SAI / 1.8Vi.MX8M MiniSAI2_TXD0ALT0NVCC_SAI2
S41I2S0_SDINIn-SAI / 1.8Vi.MX8M MiniSAI2_RXD0ALT0NVCC_SAI2
S42I2S0_CKBi-Dir-SAI / 1.8Vi.MX8M MiniSAI2_TXCALT0NVCC_SAI2
S43ESPI_ALERT0#In-SAI / 1.8Vi.MX8M MiniSAI1_RXFSALT5NVCC_SAI1
S44ESPI_ALERT1#---N.C.N.C.
S45MDIO_CLK---N.C.N.C.
S46MDIO_DAT---N.C.N.C.
S47GND-----
S48I2C_GP_CKOutPU-2.2KI2C3i.MX8M MiniI2C3_SCLALT0NVCC_I2C
S49I2C_GP_DATBi-DirPU-2.2KI2C3i.MX8M MiniI2C3_SDAALT0NVCC_I2C
S50HDA_SYNC / I2S2_LRCK---N.C.N.C.--
S51HDA_SDO / I2S2_SDOUT---N.C.N.C.--
S52HDA_SDI / I2S2_SDIN---N.C.N.C.--
S53HDA_CK / I2S2_CK---N.C.N.C.--
S54SATA_ACT#---N.C.N.C.--
S55USB5_EN_OC#In-GPIO / 3.3VN.C.DS2_OVRCURR-AVDD33
S56ESPI_IO_2---N.C.N.C.--
S57ESPI_IO_3---N.C.N.C.--
S58ESPI_RESET#---N.C.N.C.--
S59USB5+Bi-Dir-USBUSB Hub (USB2514B)DS2_DP--
S60USB5-Bi-Dir-USBUSB Hub (USB2514B)DS2_DM--
S61GND-------
S62USB3_SSTX+OutSerial-0.1uFUSBNCDS1_TXP--
S63USB3_SSTX-OutSerial-0.1uFUSBNCDS1_TXM--
S64GND-------
S65USB3_SSRX+In-USBNCDS1_RXP--
S66USB3_SSRX-In-USBNCDS1_RXM--
S67GND-------
S68USB3+Bi-Dir-USBUSB Hub (FL5500-2F0)DS1_DP--
S69USB3-Bi-Dir-USBUSB Hub (FL5500-2F0)DS1_DM--
S70GND-------
S71USB2_SSTX+OutSerial-0.1uFUSBNCDS0_TXP--
S72USB2_SSTX-OutSerial-0.1uFUSBNCDS0_TXM--
S73GND-------
S74USB2_SSRX+In-USBNCDS0_RXP--
S75USB2_SSRX-In-USBNCDS0_RXM--
S76PCIE_B_RST#Out-GPIO / 3.3VNCNAND_ALEALT5NVCC_NAND
S77PCIE_C_RST#---N.C.N.C.--
S78PCIE_C_RX+ / SERDES_2_RX+---N.C.N.C.--
S79PCIE_C_RX- / SERDES_2_RX----N.C.N.C.--
S80GND-------
S81PCIE_C_TX+ / SERDES_2_TX+---N.C.N.C.--
S82PCIE_C_TX- / SERDES_2_TX----N.C.N.C.--
S83GND-------
S84PCIE_B_REFCK+OutSerial-0.1uFPCIeNCDIF1-VDDDIG1p8
S85PCIE_B_REFCK-OutSerial-0.1uFPCIeNCDIF1\-VDDDIG1p8
S86GND-------
S87PCIE_B_RX+InSerial-0.1uFPCIeNCPCIE1_RXN_P-PCIE1_VPH
S88PCIE_B_RX-InSerial-0.1uFPCIeNCPCIE1_RXN_N-PCIE1_VPH
S89GND-------
S90PCIE_B_TX+OutSerial-0.1uFPCIeNCPCIE1_TXN_P-PCIE1_VPH
S91PCIE_B_TX-OutSerial-0.1uFPCIeNCPCIE1_TXN_N-PCIE1_VPH
S92GND-------
S93DP0_LANE0+---N.C.N.C.--
S94DP0_LANE0----N.C.N.C.--
S95DP0_AUX_SEL---N.C.N.C.--
S96DP0_LANE1+---N.C.N.C.--
S97DP0_LANE1----N.C.N.C.--
S98DP0_HPD---N.C.N.C.--
S99DP0_LANE2+---N.C.N.C.--
S100DP0_LANE2----N.C.N.C.--
S101GND-------
S102DP0_LANE3+---N.C.N.C.--
S103DP0_LANE3----N.C.N.C.--
S104USB3_OTG_ID---N.C.N.C.--
S105DP0_AUX+---N.C.N.C.--
S106DP0_AUX----N.C.N.C.--
S107LCD1_BKLT_ENOut-GPIO / 1.8Vi.MX8M MiniGPIO1_IO00--
S108LVDS1_CK+/ eDP1_AUX+/ DSI1_CLK+OutSerial-0RLVDSSN65DSI84ZXHRB_CLKP--
S109LVDS1_CK-/ eDP1_AUX-/ DSI1_CLK-OutSerial-0RLVDSSN65DSI84ZXHRB_CLKN--
S110GND-----
S111LVDS1_0+/ eDP1_TX0+/ DSI1_D0+OutSerial-0RLVDSSN65DSI84ZXHRB_YOP--
S112LVDS1_0-/ eDP1_TX0-/ DSI1_D0-OutSerial-0RLVDSSN65DSI84ZXHRB_YON--
S113eDP1_HPD/ DSI1_TE---N.C.N.C.--
S114LVDS1_1+/ eDP1_TX1+/ DSI1_D1+OutSerial-0RLVDSSN65DSI84ZXHRB_Y1P--
S115LVDS1_1- / eDP1_TX1- / DSI1_D1-OutSerial-0RLVDSSN65DSI84ZXHRB_Y1N--
S116LCD1_VDD_ENOut-GPIO/1.8Vi.MX8M MiniGPIO1_IO05--
S117LVDS1_2+ / eDP1_TX2+ / DSI1_D2+OutSerial-0RLVDSSN65DSI84ZXHRB_Y2P--
S118LVDS1_2- / eDP1_TX2- / DSI1_D2-OutSerial-0RLVDSSN65DSI84ZXHRB_Y2N--
S119GND-------
S120LVDS1_3+ / eDP1_TX3+ / DSI1_D3+OutSerial-0RLVDSSN65DSI84ZXHRB_Y3P--
S121LVDS1_3- / eDP1_TX3- / DSI1_D3-OutSerial-0RLVDSSN65DSI84ZXHRB_Y3N--
S122LCD1_BKLT_PWMOut-GPIO / 1.8Vi.MX8M MiniGPIO1_IO01ALT1NVCC_GPIO1
S123GPIO13--GPIO / 1.8Vi.MX8M MININ.C.--
S124GND-------
S125LVDS0_0+ / eDP0_TX0+ / DSI0_D0+OutSerial-0RLVDSSN65DSI84ZXHRA_Y0P--
S126LVDS0_0- / eDP0_TX0- / DSI0_D0-OutSerial-0RLVDSSN65DSI84ZXHRA_Y0N--
S127LCD0_BKLT_ENOut-GPIO / 1.8Vi.MX8M MiniGPIO1_IO10--
S128LVDS0_1+ / eDP0_TX1+ / DSI0_D1+OutSerial-0RLVDSSN65DSI84ZXHRA_Y1P--
S129LVDS0_1- / eDP0_TX1- / DSI0_D1-OutSerial-0RLVDSSN65DSI84ZXHRA_Y1N--
S130GND-------
S131LVDS0_2+ / eDP0_TX2+ / DSI0_D2+OutSerial-0RLVDSSN65DSI84ZXHRA_Y2P--
S132LVDS0_2- / eDP0_TX2- / DSI0_D2-OutSerial-0RLVDSSN65DSI84ZXHRA_Y2N--
S133LCD0_VDD_ENOut-GPIO/1.8Vi.MX8M MiniGPIO1_IO13--
S134LVDS0_CK+ / eDP0_AUX+ / DSI0_CLK+OutSerial-0RLVDSSN65DSI84ZXHRA_CLKP--
S135LVDS0_CK- / eDP0_AUX- / DSI0_CLK-OutSerial-0RLVDSSN65DSI84ZXHRA_CLKN--
S136GND-------
S137LVDS0_3+ / eDP0_TX3+ / DSI0_D3+OutSerial-0RLVDSi.MX8M MiniA_Y3P--
S138LVDS0_3- / eDP0_TX3- / DSI0_D3-OutSerial-0RLVDSi.MX8M MiniA_Y3N--
S139I2C_LCD_CKOutPU-2.2KI2C4i.MX8M MiniI2C4_SCLALT0NVCC_I2C
S140I2C_LCD_DATBi-DirPU-2.2KI2C4i.MX8M MiniI2C4_SCLALT0NVCC_I2C
S141LCD0_BKLT_PWMOut-GPIO / 1.8Vi.MX8M MiniGPIO1_IO11ALT1NVCC_GPIO1
S142GPIO12InPU-10KGPIO / 1.8Vi.MX8M MiniPC14--
S143GND-------
S144eDP0_HPD / DSI0_TEInPD-1MGPIO / 1.8Vi.MX8M MiniSAI3_RXCALT0NVCC_SAI3
S145WDT_TIME_OUT#Out-GPIO / 1.8Vi.MX8M MiniPD2-+1V8SMC
S146PCIE_WAKE#In-GPIO / 3.3Vi.MX8M MiniSAI1_TXFSALT5NVCC_SAI1
S147VDD_RTCPWR-PWR----
S148LID#InPU-4.7KGPIO / 1.8Vi.MX8M MiniSAI5_MCLKALT5NVCC_SAI5
S149SLEEP#InPU-4.7KGPIO / 1.8Vi.MX8M MiniSAI5_RXFSALT5NVCC_SAI5
S150VIN_PWR_BAD#InPU-10KGPIO / 1.8Vi.MX8M MiniPB7-+1V8SMC
S151CHARGING#OutPU-68KGPIO / 1.8Vi.MX8M MiniSAI5_RXCALT5NVCC_SAI5
S152CHARGER_PRSNT#OutPU-100KGPIO / 1.8Vi.MX8M MiniSAI5_RXD0ALT5NVCC_SAI5
S153CARRIER_STBY#Out-GPIO / 1.8Vi.MX8M MiniPB5-+1V8SMC
# 5. Software Support # 5.1.1 Uboot / Yocto Goto : https://github.com/adlink Yocto source-code and compiling instructions are available # 5.1.2 Ubuntu (TBD) Build instruction from source, are available on Github ![Search or jump to...\nPull requests Issues Marketplace Explore\nADLINK Technology Inc.\nhttps://www.adlinktech.com/en/index.aspx\nRepositories 5 Packages People 2 Teams Settings\nPinned repositories Customize pinned repositories\nmeta-adlink-x86-64bit\nSingle Yocto layer for all Intel x86 64-bit based\nComputer on Modules (COM Express, SMARC, Q7,\nETX)\nShell ★1 ★2\nmeta-adlink-nxp\nSingle Yocto layer for iMX6 & iMX8M based\nComputer on Modules. (SMARC)\nBitBake ★1\nmeta-adlink-rockchip\nmeta-adlink-sema\nSEMA layer for Yocto\nC ★1\nbios-utility\nProvide the utility of AMI BIOS setup menu\nconfiguration ★2](.smarc-lec-imx8mm-user-s-guide-rev06/2a0f52f032654bf0d4e4a94043ead91fe0b6995d0fd368da855a083fb94a2f9e.jpg) # 6. Mechanical ![Module Primary (Top) Side\n0 4\n50\n46\n12\n7.70\n6.20\n3.30\n3.10\n0\n1.25 PIN P1\n74 PINS\nP1 - P74\n39\n78\n82\n4X Ø6\n4X Ø2.70\nTHROUGH\nP75\nA\n82 PINS\nP75 - P156](.smarc-lec-imx8mm-user-s-guide-rev06/cb581ac7542f74acd824b716e3e26e1b6d4f87b44660e5c1b200ddf11ee0bdb4.jpg) ![1.00 PIN S1\n75 PINS\nS1 - S75\n83 PINS\nS76 - S158\n74/29\n74/29\nModule Primary (Bottom) Side](.smarc-lec-imx8mm-user-s-guide-rev06/7d418f775c8f1441d7c371241f1916688368ba70dc0186dfa131a3928e3a21cc.jpg) ![FULLRAD\n73X0.50\n81X0.50\n156X0.35\n(3.30)\nP74\nP75\n3.10 TYP\n1.00\n1.25\n1.25\nDETAILA\nTOP SIDE](.smarc-lec-imx8mm-user-s-guide-rev06/385046234ea06cea4ce26541b1a3fee89ab1714c42864d36e9a1bd1aa7ab6a3f.jpg) ![1.70\n(6.20)\n(1.50)\n2X R0.50\nDETAILD\nNOTCH. 2 PLACES](.smarc-lec-imx8mm-user-s-guide-rev06/807add38d511fcfb8faf04ce826a6f8e65efd63cbe61245357ae640f9d6b792e.jpg) ![P74\nP75\nTOP SIDE\n0.25\nS76\nBOTTOM SIDE\nPIN ALIGNMENTDETAL](.smarc-lec-imx8mm-user-s-guide-rev06/188d60c307ca2b6f005d8884f58ed9dfc42ff463766f7630953e3213c2202e54.jpg) ![74X0.50\n3.10 TYP\nS75\nS76\n1\n1\n82X0.50\n158X0.35\nDETAILB\nBOTTOM SIDE](.smarc-lec-imx8mm-user-s-guide-rev06/8cf9060c9580cdd4afd2ff08355e6da1fba1bc80b69621df6e8c0ce50e6ea019.jpg) ![The image displays a technical line drawing of a chamfered edge detail. It features specific dimensioning:\n- A horizontal dimension at the top reads **1.20 ±0.1**.\n- A vertical dimension on the left reads **0.18**.\n- An angle dimension to the right reads **45°**.\n- The text at the bottom reads **CHAMFEREDGE DETAIL**.](.smarc-lec-imx8mm-user-s-guide-rev06/360d228d212a58e32acaa3c7d250de486fb864403760374048c4bb423f9b2a6c.jpg) ![3.00 MAX\nCOMPONENT HEIGHT\n(TOP SIDE)\n1.30 MAX\nCOMPONENT HEIGHT\n(BOTTOM SIDE)](.smarc-lec-imx8mm-user-s-guide-rev06/c14568dc11ce103370eddf0b43bf2079b9fda27617d50eafcb318d29994da29e.jpg) # 7. Thermal Solutions For optimum performance LEC-IMX8M Mini optionally can be cooled by a passive Heatsink / Heat-spreader optionally available for ordering ![This image displays a technical engineering drawing of a mechanical part, arranged in four orthographic views.\n\n**Top Row:**\n* **Left:** A side profile view of the component.\n* **Center:** A top view showing a rectangular plate with vertical ribs running across the surface. It features four mounting holes at the corners (indicated by circles with crosshairs) and a rectangular cutout at the bottom left.\n* **Right:** Another side profile view. A leader line points to a protrusion on the side, labeled with a circled number **2**.\n\n**Bottom Row:**\n* **Bottom View:** This shows the underside of the component with red dimension lines and callouts.\n * A horizontal dimension line at the top is labeled with a circled number **1** and the text **82±0.3**.\n * A vertical dimension line on the left is labeled with a circled number **2** and the text **42±0.2**.\n * Vertical text reading **NC1198** is oriented along the left side.\n * A central square hole is marked with a circled number **3**.\n * There are three additional holes near the top edge (one square-shaped, two oblong) and a cutout at the bottom right corner.](.smarc-lec-imx8mm-user-s-guide-rev06/265ee960d990d860646007077564fa2bc2220b4087f773fcab10f69b8d316a19.jpg)
HTS-sIMX8MMHeatspreader for LEC-iMX8MM
THS-sIMX8MMLow profile heatsink for LEC-iMX8MM