# LEC-RB5(N)

User’s Guide

QualcoMw

![Close-up of a blue printed circuit board with various electronic components and gold connectors (no readable text or symbols)](.smarc-lec-rb5-n-manual-50m-72515-1010-11/2288212a9f53fa3262aae876088ece94c3cdfecbb45ded035cefd6ee5fec1ba4.jpg)

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-03-28</td><td>AL</td></tr><tr><td>1.1</td><td>Specifications and pinout and signal descriptions</td><td>2025-11-04</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image displays a standard warning symbol: a yellow triangle with a thick black border containing a single black exclamation point in the center.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/97a399afcc930570d17636fee7c680d4cf91d5e00cd6e9047123d3031b5a1877.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black and white line drawing of a wheeled waste bin with a lid. A large 'X' is superimposed over the bin, crossing it out. Below the bin, there is a solid black rectangular bar.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/fc145221d45b602f184d42288dd5ba2f0a7a222f6f321e78b03403c5c839d771.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully.
Keep this manual for future reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• Turn off power and unplug any power cords/cables when installing/mounting or un-installing/removing equipment.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources;
Keep equipment away from high heat or high humidity;
• Keep equipment properly ventilated (do not block or cover ventilation openings);
• Make sure to use recommended voltage and power source settings;
• Always install and operate equipment near an easily accessible electrical socket outlet;
• Secure the power cord (do not place any object on/over the power cord);
• Only install/attach and operate equipment on stable surfaces and/or recommended mountings;
• If the equipment will not be used for long periods of time, turn off the power source and unplug the equipment.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information

![The image shows a digital icon of a document or memo pad. It consists of a red outline forming a square shape with the bottom-right corner folded inward. Inside the white interior space, there are two horizontal red lines centered horizontally.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/e3edb4833ab4e4f606ca69582405b6920ba920850f784f2365309c955ec8389b.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a standard warning symbol featuring a yellow triangle with a white border pointing upwards. Centered inside the triangle is a white exclamation point. The background is white.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/9ecdd8302d4375a3bd3277c5bb7510950b87f85366f87f1c46acac7d02555a9b.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image shows a red triangle with rounded corners containing a white exclamation point in the center.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/4c6becd1225e8bffc020a31a515a80f9abccd7eee0e8f309d2fcb2bd4ecb54e7.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ............ ... 2

Preface . .3

List of Figures ..

1. Introduction .. .9

1.1 LEC-RB5(N)... ..9

1.2 The SMARC Form Factor ... ..9

2. Specifications ........... ....... 10

2.1 Core System.. ... 10

2.2 Video.... .. 11

2.2.1 DPU / GPU / VPU .. . 11

2.2.2 Display Interfaces... . 11

2.3 Camera.... ... 12

2.4 Audio .... ... 12

2.5 Dual Wired Ethernet... ... 12

2.6 Wi-Fi / Bluetooth .. ... 13

2.7 Extension Busses.. ... 13

2.8 System Storage .. .. 14

2.9 Board Controller... ... 14

2.10 Debug Header DB30 ... ... 15

2.11 Power.... ... 15

3. Functional Block Diagram .............. ..... 17

4. Pinout and Signal Descriptions.............. ....... 18

4.1 Pin Summary ... .. 18

4.2 Signal Terminology Descriptions... .. 22

4.3 Signal Description by function.. ... 23

4.3.1 Primary Display Interface.. ... 23

4.4 Secondary Display Interface.. ... 25

4.4.1 HDMI Mode... . 25

4.4.2 MIPI Camera Support... . 26

4.4.3 CSI Feature Connectors.. . 28
4.5 Audio Interfaces.. . 29
4.5.1 I2S0 ... . 29
4.6 USB Ports .. ... 30
4.7 PCIe Ports... ... 32
4.8 UART.. .. 33
4.9 Dual LAN Ports .. . 35
4.9.1 GBE0 .. ... 35
4.9.2 GBE1 . ... 36
4.10 SDIO Card (4-bit) ... ... 37
4.11 SPI interfaces .. ... 38
4.11.1 SPI0 .... ... 38
4.11.2 SPI1 ... ... 38
4.12 GPIO .... ... 39
4.13 CAN Bus... ... 40
4.14 Miscellaneous... ... 40
4.15 Power and System Management... ... 41
4.15.1 Boot Select... .... 43
4.15.2 Power ... .... 44

# 5. Software Support......... ...... 45

5.1 Yocto..... ... 45

5.2 Ubuntu .. ... 45

# 6. Mechanical..... ....... 46

6.1 Module Dimensions . .. 46

# 7. Thermal Solutions .. 47

7.1 Heatspreader – HTS.. .. 47

7.2 Heatsink – THS... ... 48

# List of Figures

Figure 1 – Module functional block diagram . .17
Figure 2 – Module top/bottom side pin numbering..... .18
Figure 3 – Module dimensions............ ...46
Figure 4 – Heatspreader HTS.. ..47
Figure 5 – Heatsink THS... ...48

# 1. Introduction

# 1.1 LEC-RB5(N)

ADLINK LEC-RB5(N) is a SMARC R2.1-compliant module that features Qualcomm® Kyro™ 585 CPU, with 8x Arm Cortex-A77 cores, and offers exceptional performance per watt. It includes Qualcomm® Hexagon™ Tensor Accelerator (HTA) running up to 15 TOPS and supports 4K HDMI/MIPI DSI display, MIPI CSI cameras, 2x PCIe x2 Gen3, 2x GbE Ethernet, 2x USB 3.1/2.0, 4x USB 2.0, GPIO/SD and UFS.

# 1.2 The SMARC Form Factor

The SMARC (“Smart Mobility ARChitecture”) is a versatile small form factor Computer on Module definition targeting applications that require low power and high performance at low costs. Typically under 6W, the modules often utilize ARM and other alternative low-power option CPUs, and are used in many familiar handheld devices, such as tablet computers and smart phones.

Two module sizes are defined in SMARC: 82 mm x 50 mm and 82 mm x 80 mm.

The module PCBs have 314 edge fingers that mate with a low-profile 314 pin 0.5 mm pitch right angle connector (the connector is sometimes identified as a 321-pin connector, with 7 pins used by the key).

SMARC modules are used as building blocks for portable and stationary embedded systems. The core CPU and support circuits, including DRAM, boot flash, power sequencing, CPU power supplies, GBE and a single channel LVDS display transmitter are concentrated on the module. Modules are used with application-specific carrier boards that implement other features such as audio codecs, touch controllers, wireless devices, etc.

The modular approach allows scalability, faster time to market and upgradability while still maintaining low costs, low power, and small physical size.

![The image displays a logo featuring the text 'SGTe'. The letters 'S', 'G', and 'T' are large, uppercase characters in a bright yellow color. The letter 'e' is a smaller, lowercase character in purple or magenta. The 'e' is positioned such that it overlaps the bottom right portion of the 'G' and the lower stem of the 'T'.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/a796b10f4e42395cf335abf687e2d7e9e8b33694c2f2fbb77463af10dff77621.jpg)

STANDARDIZATION

GROUPFOR

EMBEDDED

TECHNOLOGIES

SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html

# 2. Specifications

# 2.1 Core System

# SoC

QRB5165

Kryo™ 585 Octa-core CPU:

Kryo Gold prime @ 2.84GHZ
3 Kryo Gold @ 2.42GHz
• 4 Kryo Silver @ 1.81GHz

# Memory

• Four-channel PoP high speed memory LPDDR4 SDRAM @ 2133MHz, up to 8GB
• Four-channel PoP high speed memory LPDDR5 SDRAM @ 2750MHz, up to 16GB

# L2 Cache

System L2 cache (ECC)

Gold core 256 KB
Gold Prime core 512 KB
Silver core 128 KB

# Security

Qualcomm Secure Processing Unit

# 2.2 Video

# 2.2.1 DPU / GPU / VPU

DPU Core

Adreno DPU 995, supports up to 3x 4K display, up to 5040 × 2160 at 60Hz

GPU Core

Adreno GPU 650, Fmax at 587MHz – 4K 60 fps UI or 2X 2K 60 fps UI OpenGL ES 3.2, Vulkan 1.1, DX12 FL 12\_1OpenCL 2.0 full profile

VPU Core

Adreno VPU 665 – 5th gen UHD video processing unit Video, decode up to 4K240/8K60 Video, encode up to 4K120/8K30

# 2.2.2 Display Interfaces

MIPI DSI

1x MIPI DSI 4 lane, compliant with MIPI-DSI standard v1.2

Maximum resolution 1K p60 with 24-bit RGB

# HDMI

• HDMI interface is obtained from DSI0/1 over a DSI2HDMI chip (need 8 lanes)
• HDMI 2.0B complaint
• Supports a maximum display resolution of 1K p60

# 2.3 Camera

Supports CSI0 2Lane and CSI1 4-lane MIPI CSI2 camera input.

CSI2/3/4/5 on module feature connector (4 lanes)

![The image shows a red icon on a white background. It depicts a stylized document or page with a folded bottom-right corner. Inside the red outline, there are three horizontal red lines centered vertically, resembling text or a list.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/081126076f74c0803ea256e0078399efd13560f45cf125b59157f4cfb525b88e.jpg)

Note: Only 4x RGB and 2x YUV camera modules supported.

# 2.4 Audio

Supports I2S audio codec on carrier

# 2.5 Dual Wired Ethernet

# Primary LAN

10/100/1000 Ethernet Controller over USB 3.1

Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex

# Secondary LAN

10/100/1000 Ethernet Controller over USB 3.1

Supports 10/100/1000-Mbps data transfer rates, both full-duplex and half-duplex

# 2.6 Wi-Fi / Bluetooth

Optional M.2 1216 industry standard footprint with support for PCIe solder down modules

# 2.7 Extension Busses

# PCIe

2x 2-lane R3.0

# USB

2x USB 3.1 Gen 1, 4x USB 2.0

# UART

3x UART interfaces SER0,1,2

# CANbus

Optional CAN0 Supports CAN2.0B only or mixed CAN2.0B and CAN FD mode, data bit rate up to 8 Mbps (Optional over SPI1)

# SPI

2x SPI

# I2S / Sound Wire

1x I2S with audio resolution from 16-bits to 32-bits and sample rate up to 192KHz (see Audio Codec support)

# I2C

# 3x I2C interfaces

Support for 7-bit mode
• Software programmable clock frequency of 100 kbit/s in Standard-mode, 400 kbit/s in the Fast-mode, or 1 Mbit/s in Fast-mode Plus

# GPIO

14x GPIO with interrupt, one GPIO with PWM

# 2.8 System Storage

# SDIO

1x SDIO (4-bit) compatible with SD3.0, MMC ver. 4.51 to edge connector

# Storage

Up to 512 GB on-module UFS

# 2.9 Board Controller

BMC lite for power sequence

SEMA BMC Error Code

<table><tr><td>Exception Code</td><td>Error Code</td></tr><tr><td>0</td><td>NOERROR</td></tr><tr><td>2</td><td>NO_VIN</td></tr><tr><td>3</td><td>NO_SDM_RESIN_N</td></tr><tr><td>4</td><td>NO_SDM_RESIN_N</td></tr></table>

# 2.10 Debug Header DB30

Multipurpose Connector: ADLINK standard 30-pin FPC with the following pins

• Boot Select strap pins
Serial port
LITE BMC

# 2.11 Power

<table><tr><td>Power Modes:</td><td>ON / OFF / SUSPEND</td></tr><tr><td>Power on / off Behavior</td><td>AT (always boot)</td></tr><tr><td>Voltage Input:</td><td>5.0V +/- 5%</td></tr></table>

# Operating Temperatures

<table><tr><td>Standard Operating Temperature:</td><td>0 to 60°C</td><td>commercial grade BOM (memory, eMMC, USB hub, SoC)</td></tr><tr><td>Rugged Operating Temperature:</td><td>-20 to 70°C</td><td>industrial grade BOM (memory, eMMC, USB hub, SoC)</td></tr></table>

<table><tr><td rowspan="2">Humidity:</td><td>5-90% RH operating, non-condensing</td></tr><tr><td>5-95% RH storage (and operating with conformal coating).</td></tr><tr><td>EMI:</td><td>EN55022 Class B inside an enclosure</td></tr></table>

Shock and Vibration:

HALT testing, with test report that confirms Extended Operating Temp range during and after vibration. Separate Shock test report to MIL-STD-202F, Method 213B, Table 213-I, Condition A.

In addition, when installed on baseboard shall operate under 18 sawtooth mechanical shocks (3 shocks in each direction) with a peak acceleration of 40g for a duration of 18 msec each and 75g for a duration of 6 msec each.

MTBF:

Capable of supporting Random Vibration: MIL-STD-202F, Method 214A, Table 214-I, Condition D. If HALT testing shows equal or better performance, a separate vibration test report is not necessary.

300,000 hrs (at 40°C), 100,000 hrs (at 70°C),

# 3. Functional Block Diagram

![Based on the provided block diagram, here are the labeled blocks and their connections:\n\n**Labeled Blocks**\n*   **Central Processor:** QRB5165 (containing LPDDR4 / LPDDR5(N) 4G/8GB/16GB POP memory).\n*   **Left Interface Ports:** HDMI, DSI0, CSI0, CSI1, PCIe Port 0, PCIe Port 1, PCIe Port 2, PCIe Port 3, Ethernet 0, Ethernet 1, USB2.0- Port1, USB2.0- Port 4,5, USB3.0- Port 2,3, USB0_OTG, SER0, SER1, SER2, SD/SDIO, SPI 0, SPI 1, CAN, GPIO x14, I2S_SND, I2C x3.\n*   **Intermediate Controllers:** DSI2HDMI LT9611UXC, Mipi switch, LAN7800, USB HUB Microchip USB5807T/KD, CAN FD MCP25S18FDT.\n*   **Right Side Signals/Labels:** Vision connect, USB, PCIe, Uart, UFS, I2C.\n*   **Right External Modules:** CSI2_4L, CSI3_4L, CSI4_4L, CSI5_4L, BT/WIFI M2_1216 build option, UFS 64 ~ 512 GB, Debug port/console, TPM, BMC_Lite.\n\n**Connections**\n*   **HDMI** connects to **DSI2HDMI LT9611UXC**, which connects to **DSI1**.\n*   **DSI0** connects to **Mipi switch**, which connects to **DSI0**.\n*   **CSI0** connects to **CSI0 /2L**.\n*   **CSI1** connects to **CSI1 /4L**.\n*   **PCIe Port 0** connects to **PCIe_1 GEN3**.\n*   **PCIe Port 1** connects to **PCIe_1 GEN3**.\n*   **PCIe Port 2** connects to **PCIe_2 GEN3**.\n*   **PCIe Port 3** connects to **PCIe_2 GEN3**.\n*   **Ethernet 0** and **Ethernet 1** connect to **LAN7800**, which connect to the **USB HUB Microchip USB5807T/KD**, leading to **USB1 / 3.1 SS**.\n*   **USB2.0- Port1**, **USB2.0- Port 4,5**, and **USB3.0- Port 2,3** all connect to the **USB HUB Microchip USB5807T/KD**.\n*   **USB0_OTG** connects to **USB0**.\n*   **SER0** connects to **UART3 / 4W**.\n*   **SER1** connects to **UART1 / 2W**.\n*   **SER2** connects to **UART2 / 4W**.\n*   **SD/SDIO** connects to **SDIO_3.0**.\n*   **SPI 0** connects to **SPI_0**.\n*   **SPI 1** connects to **SPI_3**.\n*   **CAN** connects via dashed lines to **CAN FD MCP25S18FDT**, which connects via dashed lines to **SPI_1**.\n*   **GPIO x14** connects to **GPIO**.\n*   **I2S_SND** connects to **i2S / SoundWire**.\n*   **I2C x3** connects to **I2C**.\n*   **Vision connect** links to **CSI2_4L**, **CSI3_4L**, **CSI4_4L**, and **CSI5_4L**.\n*   **USB**, **PCIe**, and **Uart** labels connect to **BT/WIFI M2_1216 build option**.\n*   **UFS** connects to **UFS 64 ~ 512 GB**.\n*   **Debug port/console** is connected via a dashed line.\n*   **I2C** connects to **TPM**.\n*   **I2C** connects to **BMC_Lite**.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/c1d4883f7d9bac81b2df7c66b1c62ba5c9705a062fba0d6ce31931c9ef3f6c68.jpg)

Figure 1 – Module functional block diagram

# 4. Pinout and Signal Descriptions

# 4.1 Pin Summary

The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1.

Not all signals are available in each design, for specific product specs check the detailed tables in this document. Signals described in the specification but not supported on the LEC-RB5(N) are marked with strikethrough.

![Top Side\nP1 P74 P75 P156\nKey](.smarc-lec-rb5-n-manual-50m-72515-1010-11/6fe86e471ef2654fb5c0fa0863f2b3a5e75975449bdb4583071542431acab7ca.jpg)

![Bottom Side\nS156 S76 S75 S1\nKey](.smarc-lec-rb5-n-manual-50m-72515-1010-11/24d230c12594415683c906c7dee560ddd924af4c6eeab7e0b92f29256e9bb67b.jpg)

Figure 2 – Module top/bottom side pin numbering

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td></td><td></td></tr><tr><td>P1</td><td>SMB_ALERT_1V8#</td></tr><tr><td>P2</td><td>GND</td></tr><tr><td>P3</td><td>CSI1_CK+</td></tr><tr><td>P4</td><td>CSI1_CK-</td></tr><tr><td>P5</td><td>GBE1_SDP</td></tr><tr><td>P6</td><td>GBE0_SDP</td></tr><tr><td>P7</td><td>CSI1_RX0+</td></tr><tr><td>P8</td><td>CSI1_RX0-</td></tr><tr><td>P9</td><td>GND</td></tr><tr><td>P10</td><td>CSI1_RX1+</td></tr><tr><td>P11</td><td>CSI1_RX1-</td></tr><tr><td>P12</td><td>GND</td></tr><tr><td>P13</td><td>CSI1_RX2+</td></tr><tr><td>P14</td><td>CSI1_RX2-</td></tr><tr><td>P15</td><td>GND</td></tr><tr><td>P16</td><td>CSI1_RX3+</td></tr><tr><td>P17</td><td>CSI1_RX3-</td></tr><tr><td>P18</td><td>GND</td></tr><tr><td>P19</td><td>GBE0_MDI3-</td></tr><tr><td>P20</td><td>GBE0_MDI3+</td></tr><tr><td>P21</td><td>GBE0_LINK100#</td></tr><tr><td>P22</td><td>GBE0_LINK1000#</td></tr><tr><td>P23</td><td>GBE0_MDI2-</td></tr><tr><td>P24</td><td>GBE0_MDI2+</td></tr><tr><td>P25</td><td>GBE0_LINK_ACT#</td></tr><tr><td>P26</td><td>GBE0_MDI1-</td></tr><tr><td>P27</td><td>GBE0_MDI1+</td></tr><tr><td>P28</td><td>GBE0_CTREF</td></tr><tr><td>P29</td><td>GBE0_MDIO-</td></tr><tr><td>P30</td><td>GBE0_MDIO+</td></tr><tr><td>P31</td><td>SPI0_CS1#</td></tr><tr><td>P32</td><td>GND</td></tr><tr><td>P33</td><td>SDIO_WP</td></tr><tr><td>P34</td><td>SDIO_CMD</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S1</td><td>CSI1_TX+ / I2C_CAM1_CK</td></tr><tr><td>S2</td><td>CSI1_TX- / I2C_CAM1_DAT</td></tr><tr><td>S3</td><td>GND</td></tr><tr><td>S4</td><td>RSVD</td></tr><tr><td>S5</td><td>CSI0_TX- / I2C_CAM0_CK</td></tr><tr><td>S6</td><td>CAM_MCK</td></tr><tr><td>S7</td><td>CSI0_TX+ / I2C_CAM0_DAT</td></tr><tr><td>S8</td><td>CSI0_CK+</td></tr><tr><td>S9</td><td>CSI0_CK-</td></tr><tr><td>S10</td><td>GND</td></tr><tr><td>S11</td><td>CSI0_RX0+</td></tr><tr><td>S12</td><td>CSI0_RX0-</td></tr><tr><td>S13</td><td>GND</td></tr><tr><td>S14</td><td>CSI0_RX1+</td></tr><tr><td>S15</td><td>CSI0_RX1-</td></tr><tr><td>S16</td><td>GND</td></tr><tr><td>S17</td><td>GBE1_MDIO+</td></tr><tr><td>S18</td><td>GBE1_MDIO-</td></tr><tr><td>S19</td><td>GBE1_LINK100#</td></tr><tr><td>S20</td><td>GBE1_MDI1+</td></tr><tr><td>S21</td><td>GBE1_MDI1-</td></tr><tr><td>S22</td><td>GBE1_LINK1000#</td></tr><tr><td>S23</td><td>GBE1_MDI2+</td></tr><tr><td>S24</td><td>GBE1_MDI2-</td></tr><tr><td>S25</td><td>GND</td></tr><tr><td>S26</td><td>GBE1_MDI3+</td></tr><tr><td>S27</td><td>GBE1_MDI3-</td></tr><tr><td>S28</td><td>GBE1_CTREF</td></tr><tr><td>S29</td><td>PCIE_D_TX+ / SERDES_1_TX+</td></tr><tr><td>S30</td><td>PCIE_D_TX- / SERDES_1_TX-</td></tr><tr><td>S31</td><td>GBE1_LINK_ACT# (build option)</td></tr><tr><td>S32</td><td>PCIE_D_RX+ / SERDES_1_RX+</td></tr><tr><td>S33</td><td>PCIE_D_RX- / SERDES_1_RX-</td></tr><tr><td>S34</td><td>GND</td></tr><tr><td>S35</td><td>USB4+</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P35</td><td>SDIO_CD#</td></tr><tr><td>P36</td><td>SDIO_CK</td></tr><tr><td>P37</td><td>SDIO_PWR_EN</td></tr><tr><td>P38</td><td>GND</td></tr><tr><td>P39</td><td>SDIO_D0</td></tr><tr><td>P40</td><td>SDIO_D1</td></tr><tr><td>P41</td><td>SDIO_D2</td></tr><tr><td>P42</td><td>SDIO_D3</td></tr><tr><td>P43</td><td>SPI0_CS0#</td></tr><tr><td>P44</td><td>SPI0_CK</td></tr><tr><td>P45</td><td>SPI0_DIN</td></tr><tr><td>P46</td><td>SPI0_DO</td></tr><tr><td>P47</td><td>GND</td></tr><tr><td>P48</td><td>SATA_TX+</td></tr><tr><td>P49</td><td>SATA_TX-</td></tr><tr><td>P50</td><td>GND</td></tr><tr><td>P51</td><td>SATA_RX+</td></tr><tr><td>P52</td><td>SATA_RX-</td></tr><tr><td>P53</td><td>GND</td></tr><tr><td>P54</td><td>ESPI_CS0# / SPI1_CS0#</td></tr><tr><td>P55</td><td>ESPI_CS1# / SPI1_CS1#</td></tr><tr><td>P56</td><td>ESPI_CK / SPI1_CK</td></tr><tr><td>P57</td><td>ESPI_IO_1 / SPI1_DIN</td></tr><tr><td>P58</td><td>ESPI_IO_0 / SPI1_DO</td></tr><tr><td>P59</td><td>GND</td></tr><tr><td>P60</td><td>USB0+</td></tr><tr><td>P61</td><td>USB0-</td></tr><tr><td>P62</td><td>USB0_EN_OC#</td></tr><tr><td>P63</td><td>USB0_VBUS_DET</td></tr><tr><td>P64</td><td>USB0_OTG_ID</td></tr><tr><td>P65</td><td>USB1+</td></tr><tr><td>P66</td><td>USB1-</td></tr><tr><td>P67</td><td>USB1_EN_OC#</td></tr><tr><td>P68</td><td>GND</td></tr><tr><td>P69</td><td>USB2+</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S36</td><td>USB4-</td></tr><tr><td>S37</td><td>USB3_VBUS_DET</td></tr><tr><td>S38</td><td>AUDIO_MCK</td></tr><tr><td>S39</td><td>I2S0_LRCK</td></tr><tr><td>S40</td><td>I2S0_SDOUT</td></tr><tr><td>S41</td><td>I2S0_SDIN</td></tr><tr><td>S42</td><td>I2S0_CK</td></tr><tr><td>S43</td><td>ESPI_ALERT0#</td></tr><tr><td>S44</td><td>ESPI_ALERT1#</td></tr><tr><td>S45</td><td>MDIO_CLK</td></tr><tr><td>S46</td><td>MDIO_DAT</td></tr><tr><td>S47</td><td>GND</td></tr><tr><td>S48</td><td>I2C_GP_CK</td></tr><tr><td>S49</td><td>I2C_GP_DAT</td></tr><tr><td>S50</td><td>HDA_SYNC / I2S2_LRCK</td></tr><tr><td>S51</td><td>HDA_SDO / I2S2_SDOUT</td></tr><tr><td>S52</td><td>HDA_SDI / I2S2_SDIN</td></tr><tr><td>S53</td><td>HDA_CK / I2S2_CK</td></tr><tr><td>S54</td><td>SATA_ACT#</td></tr><tr><td>S55</td><td>USB5_EN_OC#</td></tr><tr><td>S56</td><td>ESPI_IO_2</td></tr><tr><td>S57</td><td>ESPI_IO_3</td></tr><tr><td>S58</td><td>ESPI_RESET#</td></tr><tr><td>S59</td><td>USB5+</td></tr><tr><td>S60</td><td>USB5-</td></tr><tr><td>S61</td><td>GND</td></tr><tr><td>S62</td><td>USB3_SSTX+</td></tr><tr><td>S63</td><td>USB3_SSTX-</td></tr><tr><td>S64</td><td>GND</td></tr><tr><td>S65</td><td>USB3_SSRX+</td></tr><tr><td>S66</td><td>USB3_SSRX-</td></tr><tr><td>S67</td><td>GND</td></tr><tr><td>S68</td><td>USB3+</td></tr><tr><td>S69</td><td>USB3-</td></tr><tr><td>S70</td><td>GND</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P70</td><td>USB2-</td></tr><tr><td>P71</td><td>USB2_EN_OC#</td></tr><tr><td>P72</td><td>RSVD</td></tr><tr><td>P73</td><td>RSVD</td></tr><tr><td>P74</td><td>USB3_EN_OC#</td></tr><tr><td></td><td></td></tr><tr><td></td><td>Key</td></tr><tr><td></td><td></td></tr><tr><td>P75</td><td>PCIE_A_RST#</td></tr><tr><td>P76</td><td>USB4_EN_OC#</td></tr><tr><td>P77</td><td>PCIE_B_CKREQ#</td></tr><tr><td>P78</td><td>PCIE_A_CKREQ#</td></tr><tr><td>P79</td><td>GND</td></tr><tr><td>P80</td><td>PCIE_C_REFCK+</td></tr><tr><td>P81</td><td>PCIE_C_REFCK-</td></tr><tr><td>P82</td><td>GND</td></tr><tr><td>P83</td><td>PCIE_A_REFCK+</td></tr><tr><td>P84</td><td>PCIE_A_REFCK-</td></tr><tr><td>P85</td><td>GND</td></tr><tr><td>P86</td><td>PCIE_A_RX+</td></tr><tr><td>P87</td><td>PCIE_A_RX-</td></tr><tr><td>P88</td><td>GND</td></tr><tr><td>P89</td><td>PCIE_A_TX+</td></tr><tr><td>P90</td><td>PCIE_A_TX-</td></tr><tr><td>P91</td><td>GND</td></tr><tr><td>P92</td><td>HDMI_D2+/</td></tr><tr><td>P93</td><td>HDMI_D2-/ DP1_LANE0-</td></tr><tr><td>P94</td><td>GND</td></tr><tr><td>P95</td><td>HDMI_D1+/</td></tr><tr><td>P96</td><td>HDMI_D1-/ DP1_LANE1-</td></tr><tr><td>P97</td><td>GND</td></tr><tr><td>P98</td><td>HDMI_D0+/</td></tr><tr><td>P99</td><td>HDMI_D0-/ DP1_LANE2-</td></tr><tr><td>P100</td><td>GND</td></tr><tr><td>P101</td><td>HDMI_CK+/</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S71</td><td>USB2_SSTX+</td></tr><tr><td>S72</td><td>USB2_SSTX-</td></tr><tr><td>S73</td><td>GND</td></tr><tr><td>S74</td><td>USB2_SSRX+</td></tr><tr><td>S75</td><td>USB2_SSRX-</td></tr><tr><td></td><td></td></tr><tr><td></td><td>Key</td></tr><tr><td></td><td></td></tr><tr><td>S76</td><td>PCIE_B_RST#</td></tr><tr><td>S77</td><td>PCIE_C_RST#</td></tr><tr><td>S78</td><td>PCIE_C_RX+ / SERDES_2_RX+</td></tr><tr><td>S79</td><td>PCIE_C_RX- / SERDES_2_RX-</td></tr><tr><td>S80</td><td>GND</td></tr><tr><td>S81</td><td>PCIE_C_TX+ / SERDES_2_TX+</td></tr><tr><td>S82</td><td>PCIE_C_TX- / SERDES_2_TX-</td></tr><tr><td>S83</td><td>GND</td></tr><tr><td>S84</td><td>PCIE_B_REFCK+</td></tr><tr><td>S85</td><td>PCIE_B_REFCK-</td></tr><tr><td>S86</td><td>GND</td></tr><tr><td>S87</td><td>PCIE_B_RX+</td></tr><tr><td>S88</td><td>PCIE_B_RX-</td></tr><tr><td>S89</td><td>GND</td></tr><tr><td>S90</td><td>PCIE_B_TX+</td></tr><tr><td>S91</td><td>PCIE_B_TX-</td></tr><tr><td>S92</td><td>GND</td></tr><tr><td>S93</td><td>DP0_LANE0+</td></tr><tr><td>S94</td><td>DP0_LANE0-</td></tr><tr><td>S95</td><td>DP0_AUX_SEL</td></tr><tr><td>S96</td><td>DP0_LANE1+</td></tr><tr><td>S97</td><td>DP0_LANE1-</td></tr><tr><td>S98</td><td>DP0_HPD</td></tr><tr><td>S99</td><td>DP0_LANE2+</td></tr><tr><td>S100</td><td>DP0_LANE2-</td></tr><tr><td>S101</td><td>GND</td></tr><tr><td>S102</td><td>DP0_LANE3+</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P102</td><td>HDMI_CK- / DP1_LANE3-</td></tr><tr><td>P103</td><td>GND</td></tr><tr><td>P104</td><td>HDMI_HPD / DP1_HPD</td></tr><tr><td>P105</td><td>HDMI_CTRL_CK /</td></tr><tr><td>P106</td><td>HDMI_CTRL_DAT /</td></tr><tr><td>P107</td><td>DP1_AUX_SEL</td></tr><tr><td>P108</td><td>GPIO0 / CAM0_PWR#</td></tr><tr><td>P109</td><td>GPIO1 / CAM1_PWR#</td></tr><tr><td>P110</td><td>GPIO2 / CAM0_RST#</td></tr><tr><td>P111</td><td>GPIO3 / CAM1_RST#</td></tr><tr><td>P112</td><td>GPIO4 / HDA_RST#</td></tr><tr><td>P113</td><td>GPIO5 / PWM_OUT</td></tr><tr><td>P114</td><td>GPIO6 / TACHIN</td></tr><tr><td>P115</td><td>GPIO7</td></tr><tr><td>P116</td><td>GPIO8</td></tr><tr><td>P117</td><td>GPIO9</td></tr><tr><td>P118</td><td>GPIO10</td></tr><tr><td>P119</td><td>GPIO11</td></tr><tr><td>P120</td><td>GND</td></tr><tr><td>P121</td><td>I2C_PM_CK</td></tr><tr><td>P122</td><td>I2C_PM_DAT</td></tr><tr><td>P123</td><td>BOOT_SEL0#</td></tr><tr><td>P124</td><td>BOOT_SEL1#</td></tr><tr><td>P125</td><td>BOOT_SEL2#</td></tr><tr><td>P126</td><td>RESET_OUT#</td></tr><tr><td>P127</td><td>RESET_IN#</td></tr><tr><td>P128</td><td>POWER_BTN#</td></tr><tr><td>P129</td><td>SER0_TX</td></tr><tr><td>P130</td><td>SER0_RX</td></tr><tr><td>P131</td><td>SER0_RTS#</td></tr><tr><td>P132</td><td>SER0_CTS#</td></tr><tr><td>P133</td><td>GND</td></tr><tr><td>P134</td><td>SER1_TX</td></tr><tr><td>P135</td><td>SER1_RX</td></tr><tr><td>P136</td><td>SER2_TX</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S103</td><td>DP0_LANE3-</td></tr><tr><td>S104</td><td>USB3_OTG_ID</td></tr><tr><td>S105</td><td>DP0_AUX+</td></tr><tr><td>S106</td><td>DP0_AUX-</td></tr><tr><td>S107</td><td>LCD1_BKLT_EN</td></tr><tr><td>S108</td><td>LVDS1_CK+/DSI1_CLK+</td></tr><tr><td>S109</td><td>LVDS1_CK-/DSI1_CLK-</td></tr><tr><td>S110</td><td>GND</td></tr><tr><td>S111</td><td>LVDS1_0+/eDP1_TX0+/DSI1_D0+</td></tr><tr><td>S112</td><td>LVDS1_0-/eDP1_TX0-/DSI1_D0-</td></tr><tr><td>S113</td><td>eDP1_HPD/DSI1_TE</td></tr><tr><td>S114</td><td>LVDS1_1+/eDP1_TX1+/DSI1_D1+</td></tr><tr><td>S115</td><td>LVDS1_1-/eDP1_TX1-/DSI1_D1-</td></tr><tr><td>S116</td><td>LCD1_VDD_EN</td></tr><tr><td>S117</td><td>LVDS1_2+/eDP1_TX2+/DSI1_D2+</td></tr><tr><td>S118</td><td>LVDS1_2-/eDP1_TX2-/DSI1_D2-</td></tr><tr><td>S119</td><td>GND</td></tr><tr><td>S120</td><td>LVDS1_3+/eDP1_TX3+/DSI1_D3+</td></tr><tr><td>S121</td><td>LVDS1_3-/eDP1_TX3-/DSI1_D3-</td></tr><tr><td>S122</td><td>LCD1_BKLT_PWM</td></tr><tr><td>S123</td><td>GPIO13</td></tr><tr><td>S124</td><td>GND</td></tr><tr><td>S125</td><td>LVDS0_0+/eDP0_TX0+/DSI0_D0+</td></tr><tr><td>S126</td><td>LVDS0_0-/eDP0_TX0-/DSI0_D0-</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td></tr><tr><td>S128</td><td>LVDS0_1+/eDP0_TX1+/DSI0_D1+</td></tr><tr><td>S129</td><td>LVDS0_1-/eDP0_TX1-/DSI0_D1-</td></tr><tr><td>S130</td><td>GND</td></tr><tr><td>S131</td><td>LVDS0_2+/eDP0_TX2+/DSI0_D2+</td></tr><tr><td>S132</td><td>LVDS0_2-/eDP0_TX2-/DSI0_D2-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td></tr><tr><td>S134</td><td>LVDS0_CK+/eDP0_AUX/DSI0_CLK+</td></tr><tr><td>S135</td><td>LVDS0_CK-/eDP0_AUX-/DSI0_CLK-</td></tr><tr><td>S136</td><td>GND</td></tr><tr><td>S137</td><td>LVDS0_3+/eDP0_TX3+/DSI0_D3+</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P137</td><td>SER2_RX</td></tr><tr><td>P138</td><td>SER2_RTS#</td></tr><tr><td>P139</td><td>SER2_CTS#</td></tr><tr><td>P140</td><td>SER3_TX</td></tr><tr><td>P141</td><td>SER3_RX</td></tr><tr><td>P142</td><td>GND</td></tr><tr><td>P143</td><td>CAN0_TX</td></tr><tr><td>P144</td><td>CAN0_RX</td></tr><tr><td>P145</td><td>CAN1_TX</td></tr><tr><td>P146</td><td>CAN1_RX</td></tr><tr><td>P147</td><td>VDD_IN</td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S138</td><td>LVDS0_3- / eDP0_TX3- / DSI0_D3-</td></tr><tr><td>S139</td><td>I2C_LCD_CK</td></tr><tr><td>S140</td><td>I2C_LCD_DAT</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td></tr><tr><td>S142</td><td>GPIO12</td></tr><tr><td>S143</td><td>GND</td></tr><tr><td>S144</td><td>eDP0_HPD / DSI0_TE</td></tr><tr><td>S145</td><td>WDT_TIME_OUT#</td></tr><tr><td>S146</td><td>PCIE_WAKE#</td></tr><tr><td>S147</td><td>VDD_RTC</td></tr><tr><td>S148</td><td>LID#</td></tr></table>

<table><tr><td>P-Pin</td><td>Primary (Top) Side</td></tr><tr><td>P148</td><td>VDD_IN</td></tr><tr><td>P149</td><td>VDD_IN</td></tr><tr><td>P150</td><td>VDD_IN</td></tr><tr><td>P151</td><td>VDD_IN</td></tr><tr><td>P152</td><td>VDD_IN</td></tr><tr><td>P153</td><td>VDD_IN</td></tr><tr><td>P154</td><td>VDD_IN</td></tr><tr><td>P155</td><td>VDD_IN</td></tr><tr><td>P156</td><td>VDD_IN</td></tr><tr><td></td><td></td></tr><tr><td></td><td></td></tr></table>

<table><tr><td>S-Pin</td><td>Secondary (Bottom) Side</td></tr><tr><td>S149</td><td>SLEEP#</td></tr><tr><td>S150</td><td>VIN_PWR_BAD#</td></tr><tr><td>S151</td><td>CHARGING#</td></tr><tr><td>S152</td><td>CHARGER_PRSNT#</td></tr><tr><td>S153</td><td>CARRIER_STBY#</td></tr><tr><td>S154</td><td>CARRIER_PWR_ON</td></tr><tr><td>S155</td><td>FORCE_RECOV#</td></tr><tr><td>S156</td><td>BATLOW#</td></tr><tr><td>S157</td><td>TEST#</td></tr><tr><td>S158</td><td>GND</td></tr><tr><td></td><td></td></tr></table>

![This image displays a red icon resembling a document or piece of paper with a folded bottom-right corner. Inside the shape, there are two horizontal red lines.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/b159d54cd4a8c754a9fd64a78c13f6661cf792316a9ce73e661866f994bdc14a.jpg)

Note: Above is the complete SMARC function set, not all signals are available

# 4.2 Signal Terminology Descriptions

Definitions of terms used for signal description tables.

<table><tr><td>Term</td><td>Description</td></tr><tr><td>I</td><td>Input to the Module</td></tr><tr><td>O</td><td>Output from the Module</td></tr><tr><td>I/O</td><td>Bi-directional input/output</td></tr><tr><td>OD</td><td>Open drain</td></tr><tr><td>PU</td><td>PU (pull-up) resistor</td></tr><tr><td>PD</td><td>PD (pull-down) resistor</td></tr><tr><td>CMOS</td><td>Logic input or output</td></tr><tr><td>GBE MDI</td><td>Differential analogue signalling for gigabit media dependent interface</td></tr><tr><td>DP</td><td>Low voltage differential signal for DisplayPort interface</td></tr><tr><td>D-PHY</td><td>Low voltage differential signal for MIPI CSI-2 cameras and DSI displays</td></tr><tr><td>M-PHY</td><td>Low voltage differential signal for MIPI CSI-3 cameras</td></tr><tr><td>LVDS</td><td>Low voltage differential signal for LCD displays</td></tr><tr><td>PCIE</td><td>Low voltage differential signal for PCIe</td></tr><tr><td>SATA</td><td>Low voltage differential signal for SATA</td></tr><tr><td>TMDS HDMI</td><td>Transition minimized differential signal for HDMI displays</td></tr><tr><td>USB</td><td>DC coupled differential signalling for traditional (non-Superspeed) USB signals</td></tr><tr><td>USB SS</td><td>Differential signal for SuperSpeed USB signals</td></tr><tr><td>USB VBUS 5V</td><td>5V tolerant input for USB VBUS detection</td></tr><tr><td>VDD_IN</td><td>Main power source from Carrier to Module</td></tr><tr><td>3.3V</td><td>3.3V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>1.8V</td><td>1.8V power domain: Active while CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>3.3Vsb</td><td>3.3V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>1.8Vsb</td><td>1.8V standby power domain: Active while CARRIER_PWRON is high (regardless of CARRIER_SBY#)</td></tr><tr><td>Sleep</td><td>Module is in its lowest power state</td></tr><tr><td>Runtime</td><td>Module is full on. CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high)</td></tr><tr><td>Standby</td><td>Module is in standby state or higher</td></tr></table>

# 4.3 Signal Description by function

# 4.3.1 Primary Display Interface

HDMI and DSI are supported on this module, eDP is NOT supported. DSI0 is 4 lanes

DSI 0/1 are used over a DSI to HDMI bridge to provide HDMI output

Channel 1

<table><tr><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td><td></td><td>Pin #</td><td>LVDS Name</td><td>MIPI DSI Name</td><td>eDP Name</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>S125</td><td>LVDS0_0+</td><td>DSIO_D0+</td><td>eDP0_TX0+</td><td></td><td>S111</td><td>LVDS1_0+</td><td>DSI1_D0+</td><td>eDP1_TX0+</td></tr><tr><td>S126</td><td>LVDS0_0-</td><td>DSIO_D0-</td><td>eDP0_TX0-</td><td></td><td>S112</td><td>LVDS1_0-</td><td>DSI1_D0-</td><td>eDP1_TX0-</td></tr><tr><td>S128</td><td>LVDS0_1+</td><td>DSIO_D1+</td><td>eDP0_TX1+</td><td></td><td>S114</td><td>LVDS1_1+</td><td>DSI1_D1+</td><td>eDP1_TX1+</td></tr><tr><td>S129</td><td>LVDS0_1-</td><td>DSIO_D1-</td><td>eDP0_TX1-</td><td></td><td>S115</td><td>LVDS1_1-</td><td>DSI1_D1-</td><td>eDP1_TX1-</td></tr><tr><td>S131</td><td>LVDS0_2+</td><td>DSIO_D2+</td><td>eDP0_TX2+</td><td></td><td>S117</td><td>LVDS1_2+</td><td>DSI1_D2+</td><td>eDP1_TX2+</td></tr><tr><td>S132</td><td>LVDS0_2-</td><td>DSIO_D2-</td><td>eDP0_TX2-</td><td></td><td>S118</td><td>LVDS1_2-</td><td>DSI1_D2-</td><td>eDP1_TX2-</td></tr><tr><td>S137</td><td>LVDS0_3+</td><td>DSIO_D3+</td><td>eDP0_TX3+</td><td></td><td>S120</td><td>LVDS1_3+</td><td>DSI1_D3+</td><td>eDP1_TX3+</td></tr><tr><td>S138</td><td>LVDS0_3-</td><td>DSIO_D3-</td><td>eDP0_TX3-</td><td></td><td>S121</td><td>LVDS1_3-</td><td>DSI1_D3-</td><td>eDP1_TX3-</td></tr><tr><td>S134</td><td>LVDS0_CK+</td><td>DSIO_CLK+</td><td>eDP0_AUX+</td><td></td><td>S108</td><td>LVDS1_CK+</td><td>DSI1_CLK+</td><td>eDP1_AUX+</td></tr><tr><td>S135</td><td>LVDS0_CK-</td><td>DSIO_CLK-</td><td>eDP0_AUX-</td><td></td><td>S109</td><td>LVDS1_CK-</td><td>DSI1_CLK-</td><td>eDP1_AUX-</td></tr><tr><td>S133</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td><td>LCD0_VDD_EN</td><td></td><td>S116</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td><td>LCD1_VDD_EN</td></tr><tr><td>S127</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td><td>LCD0_BKLT_EN</td><td></td><td>S107</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td><td>LCD1_BKLT_EN</td></tr><tr><td>S141</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td><td>LCD0_BKLT_PWM</td><td></td><td>S122</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td><td>LCD1_BKLT_PWM</td></tr><tr><td>S144</td><td></td><td>DSIO_TE</td><td>eDP0_HPD</td><td></td><td>S113</td><td>-</td><td>DSI1_TE</td><td>eDP1_HPD</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td></td><td></td><td></td><td></td><td></td><td>S139</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td><td>I2C_LCD_CK</td></tr><tr><td></td><td></td><td></td><td></td><td></td><td>S140</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td><td>I2C_LCD_DAT</td></tr></table>

4.3.1.1 DSI0 Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>DSI0_D0+</td><td>S125</td><td rowspan="8">Primary DSI panel differential pair data lines</td><td rowspan="8">O D-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8">No blocking capacitors or termination required. Layout for 90 Ohms differential impedance.</td></tr><tr><td>DSI0_D0-</td><td>S126</td></tr><tr><td>DSI0_D1+</td><td>S128</td></tr><tr><td>DSI0_D1-</td><td>S129</td></tr><tr><td>DSI0_D2+</td><td>S131</td></tr><tr><td>DSI0_D2-</td><td>S132</td></tr><tr><td>DSI0_D3+</td><td>S137</td></tr><tr><td>DSI0_D3-</td><td>S138</td></tr><tr><td>DSI0_CLK+</td><td>S134</td><td rowspan="2">Primary DSI panel differential pair clock lines.</td><td rowspan="2">O D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>DSI0_CLK-</td><td>S135</td></tr><tr><td>LCD0_VDD_EN</td><td>S133</td><td>Primary panel power enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_EN</td><td>S127</td><td>Primary panel backlight enable</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Active high</td></tr><tr><td>LCD0_BKLT_PWM</td><td>S141</td><td>Primary panel brightness control through pulse width modulation (PWM)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Through pulse width modulation (PWM)</td></tr><tr><td>DSI0_TE</td><td>S144</td><td>Primary DSI panel tearing effect signal</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>1M PD</td><td></td></tr><tr><td>I2C_LCD_DAT</td><td>S140</td><td>DDC data line used for flat panel detection and control</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr><tr><td>I2C_LCD_CK</td><td>S139</td><td>DDC clock line used for flat panel detection and control</td><td>O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 2k2</td><td></td></tr></table>

# 4.4 Secondary Display Interface

# 4.4.1 HDMI Mode

HDMI is bridged from DSI0/1 with a Lontium LT9611UXC DSI2HDMI 4K chip

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>HDMI_D2+</td><td>P92</td><td rowspan="6">HDMI port, differential pair data lines</td><td rowspan="6">O TMDS HDMI</td><td rowspan="6"></td><td rowspan="6">Runtime</td><td rowspan="6"></td><td rowspan="6">AC coupled off module</td></tr><tr><td>HDMI_D2-</td><td>P93</td></tr><tr><td>HDMI_D1+</td><td>P95</td></tr><tr><td>HDMI_D1-</td><td>P96</td></tr><tr><td>HDMI_D0+</td><td>P98</td></tr><tr><td>HDMI_D0-</td><td>P99</td></tr><tr><td>HDMI_CK+</td><td>P101</td><td rowspan="2">HDMI port, differential pair clock lines</td><td rowspan="2">O TMDS HDMI</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2">AC coupled off module</td></tr><tr><td>HDMI_CK-</td><td>P102</td></tr><tr><td>HDMI_CTRL_CK</td><td>P105</td><td>I2C_CLK line dedicated to HDMI</td><td>O OD COMS</td><td>1.8V</td><td>Runtime</td><td>PU 100K</td><td>Level shifter FET and 5V PU resistor shall be placed between the Module and the HDMI connector.Stronger pull-up is demanded to the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete Carrier pull-ups are used, the value depends on the individual carrier board implementation.</td></tr><tr><td>HDMI_CTRL_DAT</td><td>P106</td><td>I2C_DAT line dedicated to HDMI</td><td>I/O OD CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 100K</td><td>Level shifter FET and 5V PU resistor shall be placed between the Module and the HDMI connector.Stronger pull-up is demanded to the carrier board.The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016.If discrete Carrier pull-ups are used, the value depends on the individual carrier board implementation.</td></tr></table>

# 4.4.2 MIPI Camera Support

# 4.4.2.1 CSI0 (2 lanes)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>CSI0_RX0+</td><td>S11</td><td rowspan="4">CSI0 differential input (point to point)</td><td rowspan="4">I D-PHY / I M-PHY</td><td rowspan="4"></td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4"></td></tr><tr><td>CSI0_RX0-</td><td>S12</td></tr><tr><td>CSI0_RX1+</td><td>S14</td></tr><tr><td>CSI0_RX1-</td><td>S15</td></tr><tr><td>CSI0_CK+</td><td>S8</td><td rowspan="2">CSI0 differential clock input (point to point)</td><td rowspan="2">I D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI0_CK-</td><td>S9</td></tr><tr><td>I2C_CAM0_DAT /CSI0_TX-</td><td>S7</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2k</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU MIPI-CSI 3.0 uses CSIO_TX-, no PU required</td></tr><tr><td>I2C_CAM0_CK / CSI0_TX+</td><td>S5</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2k</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU MIPI-CSI 3.0 uses CSIO_TX+, no PU required</td></tr><tr><td>CAM0_PWR# / GPIO0</td><td>P108</td><td>Camera 0 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k</td><td>Shared with GPIO0</td></tr><tr><td>CAM0_RST# / GPIO2</td><td>P110</td><td>Camera 0 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k</td><td>Shared with GPIO2</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

4.4.2.2 CSI1 (4 lanes)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>CSI1_RX0+</td><td>P7</td><td rowspan="8">CSI1 differential input</td><td rowspan="8">I LVDS D-PHY / I LVDS M-PHY</td><td rowspan="8"></td><td rowspan="8">Runtime</td><td rowspan="8"></td><td rowspan="8"></td></tr><tr><td>CSI1_RX0-</td><td>P8</td></tr><tr><td>CSI1_RX1+</td><td>P10</td></tr><tr><td>CSI1_RX1-</td><td>P11</td></tr><tr><td>CSI1_RX2+</td><td>P13</td></tr><tr><td>CSI1_RX2-</td><td>P14</td></tr><tr><td>CSI1_RX3+</td><td>P16</td></tr><tr><td>CSI1_RX3-</td><td>P17</td></tr><tr><td>CSI1_CK+</td><td>P3</td><td rowspan="2">CSI1 differential clock input (point to point)</td><td rowspan="2">I LVDS D-PHY</td><td rowspan="2"></td><td rowspan="2">Runtime</td><td rowspan="2"></td><td rowspan="2"></td></tr><tr><td>CSI1_CK-</td><td>P4</td></tr><tr><td>I2C_CAM1_DAT / CSI1_TX-</td><td>S2</td><td>I2C data for serial camera data support link or differential data lane</td><td>I/O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_DAT which requires PU MIPI-CSI 3.0 uses CSIO_TX-, no PU required</td></tr><tr><td>I2C_CAM1_CK / CSI1_TX+</td><td>S1</td><td>I2C clock for serial camera data support link or differential data lane</td><td>O OD CMOS / O LVDS M-PHY</td><td>1.8V</td><td>Runtime</td><td>PU 2.2K</td><td>MIPI-CSI 2.0 uses I2C_CAM0_CK which requires PU MIPI-CSI 3.0 uses CSIO_TX+, no PU required</td></tr><tr><td>CAM1_PWR# / GPIO1</td><td>P109</td><td>Camera 1 Power Enable, active low output.</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k</td><td>Shared with GPIO1</td></tr><tr><td>CAM1_RST# / GPIO3</td><td>P111</td><td>Camera 1 reset, active low output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k</td><td>Shared with GPIO 3</td></tr><tr><td colspan="8"></td></tr><tr><td>CAM_MCK</td><td>S6</td><td>Master clock output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

![This is an icon of a red memo or document. It features a thick red outline shaped like a square with the top-right corner folded. Inside the outline, there are two horizontal red lines centered horizontally.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/8223e66607b416a10455115e6abd7f42d533d6f6ab13c0b4c08c628c1216050d.jpg)

Note: LEC-RB5 has support for up to 6 cameras. CSI 0,1 go to the carrier while CSI 2,3,4,5 are located on feature connectors of the module.

# 4.4.3 CSI Feature Connectors

All feature connectors use a 22-pin FPC to connect the camera module, the 22-pin connector has a 0.5mm pin pitch.

<table><tr><td>Name</td><td>Pin #</td><td>Description</td></tr><tr><td>GND</td><td>1</td><td>Ground</td></tr><tr><td>CAM_D0_N</td><td>2</td><td>MIPI Data Lane 0 Negative</td></tr><tr><td>CAM_D0_P</td><td>3</td><td>MIPI Data Lane 0 Positive</td></tr><tr><td>GND</td><td>4</td><td>Ground</td></tr><tr><td>CAM_D1_N</td><td>5</td><td>MIPI Data Lane 1 Negative</td></tr><tr><td>CAM_D1_P</td><td>6</td><td>MIPI Data Lane 1 Positive</td></tr><tr><td>GND</td><td>7</td><td>Ground</td></tr><tr><td>CAM_CK_N</td><td>8</td><td>MIPI Clock Lane Negative</td></tr><tr><td>CAM_CK_P</td><td>9</td><td>MIPI Clock Lane Positive</td></tr><tr><td>GND</td><td>10</td><td>Ground</td></tr><tr><td>CAM_D2_N</td><td>11</td><td>MIPI Data Lane 2 Negative</td></tr><tr><td>CAM_D2_P</td><td>12</td><td>MIPI Data Lane 2 Positive</td></tr><tr><td>GND</td><td>13</td><td>Ground</td></tr><tr><td>CAM_D3_N</td><td>14</td><td>MIPI Data Lane 3 Negative</td></tr><tr><td>CAM_D3_P</td><td>15</td><td>MIPI Data Lane 3 Positive</td></tr><tr><td>GND</td><td>16</td><td>Ground</td></tr><tr><td>CAM_IO0</td><td>17</td><td>Power Enable</td></tr><tr><td>CAM_IO1</td><td>18</td><td>LED Indicator</td></tr><tr><td>GND</td><td>19</td><td>Ground</td></tr><tr><td>CAM_SCL</td><td>20</td><td>I2C SCL</td></tr><tr><td>CAM_SDA</td><td>21</td><td>I2C SDA</td></tr><tr><td>CAM_3V3</td><td>22</td><td>3.3V Power Output</td></tr></table>

# 4.5 Audio Interfaces

4.5.1 I2S0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>I2S0_LRCK</td><td>S39</td><td>I2S0 Left &amp; Right synchronization clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td>I2S0_SDOUT</td><td>S40</td><td>I2S0 Digital audio Output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S0_SDIN</td><td>S41</td><td>I2S0 Digital audio Input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>I2S0_CK</td><td>S42</td><td>I2S0 Digital audio clock</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode</td></tr><tr><td colspan="8"></td></tr><tr><td>AUDIO_MCK</td><td>S38</td><td>Master clock output to I2S codec(s)</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td>Shared with I2S2</td></tr></table>

![The image displays a red outline icon resembling a document or page. Inside the outline, there are two horizontal red lines centered vertically. The top right corner of the document shape is folded down.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/9763d14933e685fef184c45d708a923fb8d4381dc389a26f7da9f094cf0c9064.jpg)
Note: I2S1 signalling has been removed during update to SMARC 2.0 specification

4.6 USB Ports

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>USB0+USB0-</td><td>P60P61</td><td>USB differential data pairs for port 0</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td>From SOC</td></tr><tr><td>USB0_EN_OC#</td><td>P62</td><td>USB over-current sense for port 0</td><td>I/O OD CMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB0 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB0_VBUS_DET</td><td>P63</td><td>USB port 0 host power detection, when this port is used as a device.</td><td>I USB VBUS 5V</td><td>USB VBUS 5V</td><td>Standby</td><td></td><td>When this Port is used as a device it can be connected to a USB client port VBUS pin</td></tr><tr><td>USB0_OTG_ID</td><td>P64</td><td>Input pin to announce OTG device insertion on USB 2.0 port</td><td></td><td></td><td>Standby</td><td></td><td>Resistor value to ground according to USB specification</td></tr><tr><td colspan="8"></td></tr><tr><td>USB1+USB1-</td><td>P65P66</td><td>USB differential data pairs for port 1</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td>From SOC</td></tr><tr><td>USB1_EN_OC#</td><td>P67</td><td>USB over-current sense for port 1</td><td>I/O OD CMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB1 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td colspan="8"></td></tr><tr><td>USB2+USB2-</td><td>P69P70</td><td>USB differential data pairs for port 2</td><td>I/O USB</td><td>USB</td><td>Standby</td><td></td><td>From USB 3.0 Hub</td></tr><tr><td>USB2_SSRX+USB2_SSRX-</td><td>S74S75</td><td>Receive signal differential pairs for SuperSpeed on port 2</td><td>I USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB2_SSTX+USB2_SSTX-</td><td>S71S72</td><td>Transmit signal differential pairs for SuperSpeed on port 2</td><td>O USB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB2_EN_OC#</td><td>P71</td><td>USB over-current sense for port 2</td><td>I/O OD CMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB2 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB3+USB3-</td><td>S68S69</td><td>USB differential data pairs for port 3</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td>From USB 3.0 HUB</td></tr><tr><td>USB3_SSRX+USB3_SSRX-</td><td>S65S66</td><td>Receive signal differential pairs for SuperSpeed on port 3</td><td>IUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB3_SSTX+USB3_SSTX-</td><td>S62S63</td><td>Transmit signal differential pairs for SuperSpeed on port 3</td><td>OUSB SS</td><td>USB SS</td><td>Standby</td><td></td><td>DC blocking capacitors 100nF shall be placed on the Carrier</td></tr><tr><td>USB3_EN_OC#</td><td>P74</td><td>USB over-current sense for port 3</td><td>I/O ODCMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB3 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td>USB3_VBUS_DET</td><td>S37</td><td>USB port 3 host power detection, when this port is used as a device.</td><td>IUSB-VBUS5V</td><td>USB-VBUS5V</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td>USB3_OTG_ID</td><td>S104</td><td>Input pin to announce OTG device insertion on USB 3.0 port</td><td>I-CMOS</td><td>3.3V</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td colspan="8"></td></tr><tr><td>USB4+USB4-</td><td>S35S36</td><td>USB differential data pairs for port 4</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td></td><td>From SOC</td></tr><tr><td>USB4_EN_OC#</td><td>P76</td><td>USB over-current sense for port 4</td><td>I/O ODCMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB4 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr><tr><td colspan="8"></td></tr><tr><td>USB5+USB5-</td><td>S59S60</td><td>USB differential data pairs for port 5</td><td>I/OUSB</td><td>USB</td><td>Standby</td><td>-</td><td></td></tr><tr><td>USB5_EN_OC#</td><td>S55</td><td>USB over-current sense for port 5</td><td>I/O ODCMOS</td><td>3.3V note 1</td><td>Standby</td><td>PU 10k</td><td>Pulled low by Module OD driver to disable USB5 power.Pulled low by Carrier OD driver to indicate over-current situation.</td></tr></table>

![The image shows a red icon of a document with a folded bottom-right corner. Inside the white document shape, two horizontal red lines are stacked vertically.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/cafd7271f230494e37fef068e33a44dba07f5b2bc6078560a5704519e3d8c27f.jpg)

# Note:

1. 3.3V or switched 3.3V: if a USB channel is not used, then USB[0:5]\_EN\_OC# pull-up rails may be held at GND to prevent current leakage.
2. USB0 is directly connected to the SoC and offers OTG, while others use a shared bandwidth through a USB 2.0/3.1HUB.

# 4.7 PCIe Ports

PORT A – Dual lane PCIe Gen 3.0

PORT B – Second lane

PORT C – Dual lane PCIe Gen 3.0

PORT D – second lane

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>PCIE_A_TX+PCIE_A_TX-</td><td>P89P90</td><td>Differential PCIe link A transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_A_RX+PCIE_A_RX-</td><td>P86P87</td><td>Differential PCIe link A receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_A_REFCK+PCIE_A_REFCK-</td><td>P83P84</td><td>Differential PCIe Link A reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_RST#</td><td>P75</td><td>PCIe Port A reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_A_CKREQ#</td><td>P78</td><td>PCIe Port A clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on Module</td></tr><tr><td colspan="8"></td></tr><tr><td>PCIE_B_TX+PCIE_B_TX-</td><td>S90S91</td><td>Differential PCIe link B transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_B_RX+PCIE_B_RX-</td><td>S87S88</td><td>Differential PCIe link B receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_B_REFCK+PCIE_B_REFCK-</td><td>S84S85</td><td>Differential PCIe Link B reference clock output</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_RST#</td><td>S76</td><td>PCIe Port B reset output</td><td>OCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_B_CKREQ#</td><td>P77</td><td>PCIe Port B clock request</td><td>IODCMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>Can be used for power saving mode on PCIe - Pulled up or terminated on Module</td></tr><tr><td>PCIE_C_TX+PCIE_C_TX-</td><td>S81S82</td><td>Differential PCIe link C transmit data pair</td><td>O LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled on module</td></tr><tr><td>PCIE_C_RX+PCIE_C_RX-</td><td>S78S79</td><td>Differential PCIe link C receive data pair</td><td>I LVDSPCIE</td><td></td><td>Runtime</td><td></td><td>Series AC coupled off module</td></tr><tr><td>PCIE_C_REFCK+PCIE_C_REFCK-</td><td>P80P81</td><td>Differential PCIe Link C reference clock output</td><td>-O LVDSPCIE</td><td>-</td><td>Runtime</td><td></td><td></td></tr><tr><td>PCIE_C_RST#</td><td>S77</td><td>PCIe Port C reset output</td><td>-O-CMOS</td><td>-3.3V</td><td>Runtime</td><td></td><td></td></tr></table>

4.8 UART

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SER0_TX</td><td>P129</td><td>Asynchronous serial data output port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RX</td><td>P130</td><td>Asynchronous serial data input port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_RTS#</td><td>P131</td><td>"Request to Send" handshake line for port 0</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER0_CTS#</td><td>P132</td><td>"Clear to Send" handshake line for port 0</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td colspan="8"></td></tr><tr><td>SER1_TX</td><td>P134</td><td>Asynchronous serial data output port 1</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER1_RX</td><td>P135</td><td>Asynchronous serial data input port 1</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SER2_TX</td><td>P136</td><td>Asynchronous serial data output port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>SER2_RX</td><td>P137</td><td>Asynchronous serial data input port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>SER2_RTS#</td><td>P138</td><td>"Request to Send" handshake line for port 2</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr><tr><td>SER2_CTS#</td><td>P139</td><td>"Clear to Send" handshake line for port 2</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td>-</td><td>-</td></tr></table>

# 4.9 Dual LAN Ports

4.9.1 GBE0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>GBE0_MDI0+</td><td>P30</td><td>Differential Pair Signals for External Transformer</td><td rowspan="8">I/IO GBE MDI</td><td rowspan="8"></td><td rowspan="8">Standby</td><td rowspan="8"></td><td rowspan="8">Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:1000 100 10_ MDI[0]+/- B1_DA+/- TX+/- TX+/- MDI[1]+/- B1_DB+/- RX+/- RX+/- MDI[2]+/- B1_DC+/- MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE0_MDI0-</td><td>P29</td><td rowspan="2">Carrier Series Termination: Magnetics Module appropriate for 10/100/1000 GBE transceivers</td></tr><tr><td>GBE0_MDI1+</td><td>P27</td></tr><tr><td>GBE0_MDI1-</td><td>P26</td><td>Carrier Parallel Termination:</td></tr><tr><td>GBE0_MDI2+</td><td>P24</td><td rowspan="4">Secondary side center tap terminations appropriate for Gigabit Ethernet implementations</td></tr><tr><td>GBE0_MDI2-</td><td>P23</td></tr><tr><td>GBE0_MDI3+</td><td>P20</td></tr><tr><td>GBE0_MDI3-</td><td>P19</td></tr><tr><td>GBE0_LINK100#</td><td>P21</td><td>Link Speed Indication LED for GBE 0 100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE0_LINK1000#</td><td>P22</td><td>Link Speed Indication LED for GBE 0 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE0_LINK_ACT#</td><td>P25</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE0_CTREF</td><td>P28</td><td>Center Tap reference voltage for Carrier board Ethernet magnetic (if required by the Module GBE PHY)</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td>GBE0_SDP</td><td>P6</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td>-</td><td>-</td></tr></table>

![The image displays a red icon on a white background. The icon is shaped like a document or note with rounded corners and a folded bottom-right corner. Inside the red shape, two horizontal red lines are centered, resembling lines of text.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/9bdee14de6d45cca6f55d0b01078d266c42bfdc3db5fd381718ff2ba475f62b5.jpg)

Note: LAN ports are derived from USB. There are no native LAN port in the QRB5165 SoC

4.9.2 GBE1

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GBE1_MDI0+</td><td>S17</td><td>Differential Pair Signals for External Transformer</td><td rowspan="8">I/IO GBE MDI</td><td rowspan="8"></td><td rowspan="8">Standby</td><td rowspan="8"></td><td rowspan="8">Gigabit Ethernet Controller 1: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:1000 100 10MDI[0]+/- B1_DA+/- TX+/-TX+/-MDI[1]+/- B1_DB+/- RX+/-RX+/-MDI[2]+/- B1_DC+/-MDI[3]+/- B1_DD+/-</td></tr><tr><td>GBE1_MDI0-</td><td>S18</td><td>Carrier Series Termination:</td></tr><tr><td>GBE1_MDI1+</td><td>S20</td><td>Magnetics Module appropriate for 10/100/1000 GBE transceivers</td></tr><tr><td>GBE1_MDI1-</td><td>S21</td><td>Carrier Parallel Termination:</td></tr><tr><td>GBE1_MDI2+</td><td>S23</td><td rowspan="4">Secondary side center tap terminations appropriate for Gigabit Ethernet implementations</td></tr><tr><td>GBE1_MDI2-</td><td>S24</td></tr><tr><td>GBE1_MDI3+</td><td>S26</td></tr><tr><td>GBE1_MDI3-</td><td>S27</td></tr><tr><td>GBE1_LINK100#</td><td>S19</td><td>Link Speed Indication LED for GBE 1 100Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE1_LINK1000#</td><td>S22</td><td>Link Speed Indication LED for GBE 1 1000Mbps</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE1_LINK_ACT#</td><td>S31</td><td>Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity</td><td>O OD CMOS</td><td>3.3V</td><td>Standby</td><td></td><td>Shall be able to sink 24mA or more Carrier LED current</td></tr><tr><td>GBE1_CTREF</td><td>S28</td><td>Center-Tap reference voltage for Carrier board Ethernet magnetic`(if required by the Module GBE PHY)`</td><td>Analog</td><td>0 to 3.3V max</td><td>Standby</td><td>-</td><td>-</td></tr><tr><td>GBE1_SDP</td><td>P5</td><td>IEEE 1588 Trigger Signal. For hardware implementation of PTP (precision time protocol)</td><td>IO CMOS</td><td>3.3V</td><td>Standby</td><td>-</td><td>-</td></tr></table>

![The image displays a simple icon of a document or memo. It features a red outline of a white rectangular shape with a folded bottom-right corner. Inside the shape, there are two horizontal red lines stacked vertically in the center, resembling text or a list.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/c1ad045468f747017ac5433376295939c67eb71e5a7d69af5ceb3e861662b4f4.jpg)

Note: LAN ports are derived from USB. There are no native LAN port in the QRB5165 SoC

4.10 SDIO Card (4-bit)

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SDIO_D0</td><td>P39</td><td rowspan="4">SDIO Data lines. These signals operate in push-pull mode.</td><td rowspan="4">I/O CMOS</td><td rowspan="4">1.8V or 3.3V</td><td rowspan="4">Runtime</td><td rowspan="4"></td><td rowspan="4">SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_D1</td><td>P40</td></tr><tr><td>SDIO_D2</td><td>P41</td></tr><tr><td>SDIO_D3</td><td>P42</td></tr><tr><td>SDIO_WP</td><td>P33</td><td>SDIO Write Protect. This signal denotes the state of the write-protect tab on SD cards.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CMD</td><td>P34</td><td>SDIO Command/Response. This signal is used for card initialization and for command transfers. During initialization mode this signal is open drain. During command transfer this signal is in push-pull mode.</td><td>I/O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td>SDIO controller will detect SD Cards voltage level (1.8V for UHS-I and 3.3V for standard) and adjust its I/O voltage level accordingly</td></tr><tr><td>SDIO_CD#</td><td>P35</td><td>SDIO Card Detect. This signal indicates when a SDIO/MMC card is present.</td><td>I OD CMOS</td><td>3.3V</td><td>Runtime</td><td>PU 10k</td><td>Pulled up on module</td></tr><tr><td>SDIO_CK</td><td>P36</td><td>SDIO Clock. With each cycle of this signal a one-bit transfer on the command and each data line occurs.</td><td>O CMOS</td><td>1.8V or 3.3V</td><td>Runtime</td><td></td><td></td></tr><tr><td>SDIO_PWR_EN</td><td>P37</td><td>SDIO Power Enable. This signal is used to enable the power being supplied to a SD/MMC card device.</td><td>O CMOS</td><td>3.3V</td><td>Runtime</td><td></td><td>should be driven low in STB Mode by the module</td></tr></table>

# 4.11 SPI interfaces

4.11.1 SPI0

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>SPI0_CS0#</td><td>P43</td><td>SPI0 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_CS1#</td><td>P31</td><td>SPI0 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_CK</td><td>P44</td><td>SPI0 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI0_DIN</td><td>P45</td><td>SPI0 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MISO</td></tr><tr><td>SPI0_DO</td><td>P46</td><td>SPI0 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MOSI</td></tr></table>

# 4.11.2 SPI1

SPI Mode

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>SPI1_CS0#</td><td>P54</td><td>SPI1 Master Chip Select 0</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>SPI1_CS1#</td><td>P55</td><td>SPI1 Master Chip Select 1</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td>-</td><td>can also be used as ESPI_CS1#</td></tr><tr><td>SPI1_CK</td><td>P56</td><td>SPI1 Clock</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>can also be used as ESPI_CK</td></tr><tr><td>SPI1_DIN</td><td>P57</td><td>SPI1 Master input / Slave output</td><td>I CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MISO can also be used as ESPI_IO_1</td></tr><tr><td>SPI1_DO</td><td>P58</td><td>SPI1 Master output / Slave input</td><td>O CMOS</td><td>1.8V</td><td>Standby</td><td></td><td>also referred to as MOSI can also be used as ESPI_IO_0</td></tr></table>

4.12 GPIO

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td>GPIO0 / CAM0_PWR#</td><td>P108</td><td>General purpose I/O pin 0.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>alternate use is Camera 0 Power Enable, active low output</td></tr><tr><td>GPIO1 / CAM1_PWR#</td><td>P109</td><td>General purpose I/O pin 1.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>alternate use is Camera 1 Power Enable, active low output</td></tr><tr><td>GPIO2 / CAM0_RST#</td><td>P110</td><td>General purpose I/O pin 2.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>alternate use is Camera 0 Reset, active low output</td></tr><tr><td>GPIO3 / CAM1_RST#</td><td>P111</td><td>General purpose I/O pin 3.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>alternate use is Camera 1 Reset, active low output</td></tr><tr><td>GPIO4 / HDA_RST#</td><td>P112</td><td>General purpose I/O pin 4.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>alternative use is HD Audio Reset, active low output</td></tr><tr><td>GPIO5 / PWM_OUT</td><td>P113</td><td>General purpose I/O pin 5.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>alternate use is PWM output</td></tr><tr><td>GPIO6 / TACHIN</td><td>P114</td><td>General purpose I/O pin 6.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>FAN Tachometer input (used with GPIO5 PWM_OUT)</td></tr><tr><td>GPIO7</td><td>P115</td><td>General purpose I/O pin 7.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td></td></tr><tr><td>GPIO8</td><td>P116</td><td>General purpose I/O pin 8.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td></td></tr><tr><td>GPIO9</td><td>P117</td><td>General purpose I/O pin 9.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td></td></tr><tr><td>GPIO10</td><td>P118</td><td>General purpose I/O pin 10.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td></td></tr><tr><td>GPIO11</td><td>P119</td><td>General purpose I/O pin 11.</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td></td></tr><tr><td>GPIO12</td><td>S142</td><td>General purpose I/O pin 12</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td>advised as INT signal to any expander on carrier.</td></tr><tr><td>GPIO13</td><td>S123</td><td>General purpose I/O pin 13</td><td>I/O CMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k $^{1}$ </td><td></td></tr></table>

![The image displays a red icon on a white background. It depicts a rectangular outline resembling a document or page, featuring a folded bottom-right corner. Inside the outline, there are two horizontal red lines centered in the upper portion.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/b3c2305120635f23efb88b539ccddb931479219ad1bfcbd6a0742eff9b90134a.jpg)

Note: In-SoC Pull-Ups allowed. These can be ≤ 10k. Max 2.2k PD should be implemented on Carrier if a low level needs to be ensured.

# 4.13 CAN Bus

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr></table>

<table><tr><td>CAN0_TX</td><td>P143</td><td>CAN port 0 Transmit output</td><td>O CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>CAN0_RX</td><td>P144</td><td>CAN port 0 Receive input</td><td>I CMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr></table>

![The image displays a red icon on a white background. The icon is shaped like a document page with the bottom-right corner folded up. Inside the page outline is a solid red square, which contains two horizontal white lines.](.smarc-lec-rb5-n-manual-50m-72515-1010-11/d98c51d3dcff8f421347728c8dac9fd24c31eaed60a379866cdbdeebe49dcc5b.jpg)

Note: CAN bus is derived from SPI to CAN adapter (BOM option).

# 4.14 Miscellaneous

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr></table>

<table><tr><td>TEST#</td><td>S157</td><td>Held Low by Carrier to Invoke Module Vendor Specific Test Functions</td><td>I ODCMOS</td><td>1.8 to 5 V</td><td>Runtime</td><td>PU</td><td>Module must implement PU but actual value is depended on particular Module design. Carrier Board should leave this pin floating for normal operation. Driven by OD on Carrier</td></tr><tr><td>WDT_TIME_OUT#</td><td>S145</td><td>Watch-Dog-Timer Output, low active.</td><td>OCMOS</td><td>1.8V</td><td>Runtime</td><td></td><td></td></tr><tr><td>PWM_OUT / GPIO5</td><td>P113</td><td>Pulse Width Modulation (PWM) output</td><td>I/OCMOS</td><td>1.8V</td><td>Runtime</td><td>PU 470k</td><td>PWM is the default pin configuration</td></tr></table>

4.15 Power and System Management

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>BATLOW#</td><td>S156</td><td>Battery low indication to Module. Carrier to float the line in inactive state.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/ Sleep</td><td>PU 10k</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CARRIER_PWR_ON</td><td>S154</td><td>Carrier Board circuits (apart from power management and power path circuits)should notbe powered up until the Module asserts the CARRIER_PWR_ON signal.</td><td>OCMOS</td><td>1.8V</td><td>Standby</td><td></td><td>On x86 designs this pin should utilize a standby related power signal i.e. RSM_RST# or SLP_A# signal.</td></tr><tr><td>CARRIER_STBY#</td><td>S153</td><td>The Moduleshalldrive this signal low when the system is in a standby power state.</td><td>OCMOS</td><td>1.8V</td><td>Standby</td><td></td><td>On x86 designs this pin should utilize the SUS_S3# signal.</td></tr><tr><td>CHARGER_PRSNT#</td><td>S152</td><td>Held low by Carrier if DC input for battery charger is present.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/ Sleep</td><td>PU 10k</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>CHARGING#</td><td>S151</td><td>Held low by Carrier during battery charging. Carrier to float the line when charge is complete.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/ Sleep</td><td>PU 10k</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>VIN_PWR_BAD#</td><td>S150</td><td>Power bad indication from Carrier Board. Module and Carrier power supplies (other than Module and Carrier power supervisory circuits) shall notbe enabled while this signal is held low by the Carrier.</td><td>IOD CMOS</td><td>VDD_IN</td><td></td><td>PU 10k</td><td>Driven by OD on Carrier Module must implement PU but actual value is depended on particular module design.</td></tr><tr><td>SLEEP#</td><td>S149</td><td>Sleep indicator from Carrier Board.May be sourced from user Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive.Shouldbe de-bounced on the Module.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10k</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>LID#</td><td>S148</td><td>Lid open/close indication to Module. Low indicates lid closure (which system may use to initiate a sleep state). Carrier to float the line in in-active state. Active low, level sensitive.Shouldbe de-bounced on the Module.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10k</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>POWER_BTN#</td><td>P128</td><td>Power-button input from Carrier Board. Carrier to float the line in in-active state. Active low, level sensitive. Should be debounced on the Module.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10k</td><td>Driven by OD on Carrier. Pulled up on module.</td></tr><tr><td>POWER_BTN#</td><td>P128</td><td>Power-button input from Carrier Board. Carrier to float the line in in-active state. Active low, level sensitive.Should be debounced on the Module.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10k</td><td>Driven by OD on Carrier.Pulled up on module.</td></tr><tr><td>RESET_OUT#</td><td>P126</td><td>General purpose reset output to Carrier board.</td><td>OCMOS</td><td>1.8V</td><td>Standby</td><td></td><td></td></tr><tr><td>RESET_IN#</td><td>P127</td><td>Reset input from Carrier Board. Carrier drives low to force a Module reset, floats the line otherwise.This signal Shall be level triggered during bootup to allow to stop booting of the module.After bootup it May act as an edge triggered signal.</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby</td><td>PU 10k</td><td>Driven by OD on Carrier.Pulled up on module.</td></tr><tr><td>I2C_PM_DAT</td><td>P122</td><td>Power management I2C bus DATA</td><td>I/O ODCMOS</td><td>1.8V</td><td>Standby/Sleep</td><td>PU 2k2</td><td>On x86 systems these serve as SMB DATA.Pulled up on module.</td></tr><tr><td>I2C_PM_CK</td><td>P121</td><td>Power management I2C bus CLK</td><td>OD CMOS</td><td>1.8V</td><td>Standby/Sleep</td><td>PU 2k2</td><td>On x86 systems these serve as SMB CLK.Pulled up on module.</td></tr><tr><td>SMB_ALERT_1V8#</td><td>P1</td><td>SMBus Alert# (interrupt) signal</td><td>IOD CMOS</td><td>1.8V to 5V</td><td>Standby/Sleep</td><td>PU 2k2</td><td>only used on x86 design</td></tr></table>

4.15.1 Boot Select

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>I/O Level</td><td>Power Domain</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="8"></td></tr><tr><td>BOOT_SEL0#</td><td>P123</td><td rowspan="3">Input straps determine the Module boot</td><td rowspan="3">I OD CMOS</td><td rowspan="3">1.8V</td><td rowspan="3">Standby</td><td rowspan="3">PU 10k</td><td rowspan="3">Driven by OD on Carrier.Pulled up on module.booting from UFS only</td></tr><tr><td>BOOT_SEL1#</td><td>P124</td></tr><tr><td>BOOT_SEL2#</td><td>P125</td></tr><tr><td>FORCE_RECOV#</td><td>S155</td><td></td><td>I OD CMOS</td><td>1.8V</td><td>Standby</td><td>PU 10k</td><td>Driven by OD on Carrier.Pulled up on module.Low on this pin allows non-protected segments of Module boot device to be rewritten / restored from an external USB Host on Module USB0. The Module USB0 operates in Client Mode when in the Force Recovery function is invoked. Pulled high on the Module. For SOCs that do not implement a USB based Force Recovery functions, then a low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier.</td></tr></table>

4.15.2 Power

<table><tr><td>Name</td><td>Pin #</td><td>Description</td><td>I/O Type</td><td>Power Rail / Tolerance</td><td>PU / PD</td><td>Comments</td></tr><tr><td colspan="7"></td></tr><tr><td>VDD_IN</td><td>P147, P148, P149, P150, P151, P152, P153, P154, P155, P156</td><td>Module power input voltage 4.75 min to 5.25V max</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>5V +/- 5%</td><td></td><td></td></tr><tr><td>GND</td><td>P2, P9, P12, P15, P18, P32, P38, P47, P50, P53, P59, P68, P79, P82, P85, P88, P91, P94, P97, P100, P103, P120, P133, P142, S3, S10, S16, S25, S34, S47, S61, S64, S67, S70, S73, S80, S83, S86, S89, S92, S101, S110, S119, S124, S130, S136, S143, S158</td><td>Module signal and power return, and GND reference</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>Ground</td><td></td><td></td></tr><tr><td>VDD_RTC</td><td>S147</td><td>Low current RTC circuit backup power - 3.0V nominal. May be sourced from a Carrier based Lithium cell or Super Cap.</td><td>P Not defined within Signal Terminology Descriptions. Should we define a specific rail?</td><td>[2 to 3.25] / 3.25V</td><td></td><td></td></tr></table>

# 5. Software Support

# 5.1 Yocto

Go to www.github.com/ADLINK/meta-adlink-qualcomm for Yocto support.

# 5.2 Ubuntu

Standard OS

# 6. Mechanical

# 6.1 Module Dimensions

SMARC Short Size: 82x 50mm

![Preferred Area for\nRF Connectors\n(Top Side)\nKeep Out Area\n(Top and Bottom Side)\n5.10 mm](.smarc-lec-rb5-n-manual-50m-72515-1010-11/bf339eb91da95b31e9475c3bb6da3c1655b80f1cd15e9ef4b9a540584ca1a5c5.jpg)

Figure 3 – Module dimensions

# 7. Thermal Solutions

# 7.1 Heatspreader – HTS

Sustainable temperature range with high performance LAB copper heatsink

with high airflow = -40\~85°C ambient

![' No need to check the character size & position.'\n① 82±0.20\n② 42±0.20\nNC1613\n③ NC1613\n⑥ 1.85±0.1\n⑤ 1.15±0.1\n③6±0.2\nhairpin direction\nQC check level D-level\nAppearance of the surface to allow metal traces after processing\nThermally Conductive Adhesive\nQC check level C-level\nAppearance of the surface to allow metal traces after processing\nFigure 4 – Heatspreader HTS](.smarc-lec-rb5-n-manual-50m-72515-1010-11/f81c0b7961617ee4627ff3a16f01bfd52c59c409870acc49698b0c647cb9d58a.jpg)

# 7.2 Heatsink – THS

Sustainable temperature range with moderate airflow $= 0 { \sim } 6 0 ^ { \circ } C$ ambient

![NC1614\n①\n②\n③\n④\n⑤\n⑥\n⑦\n⑧\n⑨\n⑩\n⑪\n⑫\n⑬\n⑭\n⑮\n⑯\n⑰\n⑱\n⑲\n⑳\n⑴\n⑵\n⑶\n⑷\n⑸\n⑹\n⑺ No need to check the character size & position.'\nNC1614\n①82±0.3\n②42±0.2\n③12±0.3\n④ 1.15±0.1\n⑤ 1.85±0.1\nQC check level: C-level\nAppearance of the surface to allow metal traces after processing\nQC check level: D-level\nAppearance of the surface to allow metal traces after processing.\nThermally Conductive Adhesive](.smarc-lec-rb5-n-manual-50m-72515-1010-11/11f3e90a630301377d6844a5249869dc8598f25d971f5f759463f7c399a6c5a5.jpg)

Figure 5 – Heatsink THS
[🔗 Link to the original document](.smarc-lec-rb5-n-manual-50m-72515-1010-11/smarc-lec-rb5-n-manual-50m-72515-1010-11.pdf)