# Titan2 Series

IP69K Stainless Steel Panel PC

User’s Manual

![Exterior view of a modern tablet device with black frame and silver casing (no visible text or symbols)](.sp-titan2-50m-p5300-1010-11-240912/1df165091f31ad76c65c8e00d71256d8c2eee22b5788942bb782bbcb63147c80.jpg)

Manual Rev.: 1.1

Revision Date: Sept 12, 2024

Part No: 50M-P5300-1010

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2024-02-27</td><td>Initial Release</td></tr><tr><td>1.1</td><td>2024-09-12</td><td>DC input pin definition corrected</td></tr></table>

# Preface

# Copyright © 2024 ADLINK Technology Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.sp-titan2-50m-p5300-1010-11-240912/19e8ebd31b6548f65c40177f9b95cad060dc042b27a6429c893a18f508384ed1.jpg)

Battery Labels (for products with battery)

![Simple line drawing of a trash bin with two crossed lines (no text or symbols)](.sp-titan2-50m-p5300-1010-11-240912/8b0db813bd0236838bead81f5aa4fd061dbcac02c621915b487fb1c51f1b448f.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.sp-titan2-50m-p5300-1010-11-240912/d9f9d18e640e557fe3513d33b75d1b1597c2c90cb5304284a78ca2d3f02d0650.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n1-800.822.8837](.sp-titan2-50m-p5300-1010-11-240912/01bd346febf2292f7d1f75d9603c61ca13b7265a1e83d2e63b1aa74669dd529b.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.sp-titan2-50m-p5300-1010-11-240912/85ec1322ce457b739ea182a01f1f7a598a83c1e554f2f8b22b77c17c7cdfb98f.jpg)

ᘄ㟁ụㄳᅇᨲ

# California Proposition 65 Warning

![The image displays the upper portion of a yellow triangular warning sign with a thick black border. Inside the triangle is a large, black exclamation point. The sign is set against a white background.](.sp-titan2-50m-p5300-1010-11-240912/235837a1cd1253d76d145cbbd47f4d793e01ac0ba674741d18671974173fef6b.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl) phosphate (TDCPP), 1,4- Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a graphic icon of a white sheet of paper featuring faint horizontal gray lines that simulate text. A large, bold red checkmark is superimposed diagonally across the center of the document. The top-left corner of the paper is folded down.](.sp-titan2-50m-p5300-1010-11-240912/eaaef85f55954a147800b5d05c6b2520394b37c89c3d815bf8f52a2eec167097.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a cropped view of a yellow triangular warning sign with a black border. Inside the yellow triangle is a large black exclamation point. Below the sign, a white background is visible.](.sp-titan2-50m-p5300-1010-11-240912/421aa67f9dd6013e786c42923b877a83a432d5519c797f0c7035e5f55779389b.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

ATTENTION: Informations destinées à prévenir les blessures corporelles mineures, les dommages aux composants, la perte de données et/ou la corruption de programme lors de l'exécution d'une tâche.

![A red triangle with a white exclamation point in the center.](.sp-titan2-50m-p5300-1010-11-240912/eda08a7ff48ca5a185de6bed215c4afb4bcb450e51aa355bfd6eefa3b15fe8cd.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

AVERTISSEMENT: Informations destinées à prévenir les blessures corporelles graves, les dommages aux composants, la perte de données et/ou la corruption de programme lors de l'exécution d'une tâche spécifique.

# Table of Contents

# Preface ............ iii

# List of Tables......... ... vii

# List of Figures ........ ix

# 1 Introduction .......

1.1 Overview...... 1
1.2 Features.... 1
1.3 Packing List .. 2
1.4 Optional Accessories . 2

# 2 Specifications ........ 3

2.1 Titan2 Series Specifications ..... 3
2.2 Titan2 Series Block Diagram ..... 5
2.3 Power... 6
2.4 Mechanical Dimensions... 7
2.5 Thermal Options . 10

# 3 System Layout....... . 13

3.1 External I/O Connectors . . 13
3.2 Internal I/O Connectors.... . 18

# 4 BIOS Setup.......... 49

4.1 BIOS Setup Menu.. 49
4.2 Menu Structure ... . 51
4.3 Main Menu... 53
4.4 Advanced Menu.. 55
4.5 Chipset.. 77
4.6 Security ..... 86
4.7 Boot .... 87

4.8 Save & Exit ... 88

# 5 Driver & Application Installation ....... .. 89

5.1 Driver Installation Order .... 89

# Important Safety Instructions......... .... 91

# Consignes de Sécurité Importante ......... .. 93

# EMC Compliance ........ .... 96

# Getting Service ........ .... 97

# List of Tables

Table 2-1: Titan2 Series Specifications . 3

Table 2-2: Power Consumption . 6

Table 2-3: Heat Sink Components.. .. 11

Table 3-1: External I/O Legend.. . 13

Table 3-2: DC Input Pin Definition ... .. 14

Table 3-3: Serial Port Pin Definition.. . 15

Table 3-4: USB 2.0 Connector Pin Definition... .. 16

Table 3-5: Ethernet Pin Definition ... .. 17

Table 3-6: Mainboard Connector Legend . . 19

Table 3-7: Power Connector Pin Definition.. .. 20

Table 3-8: SATA Data Connector Pin Definition... .. 21

Table 3-9: SATA Power Connector Pin Definition ..... .. 21

Table 3-10: Touchscreen Connector Pin Definition .... .. 22

Table 3-11: M.2 3042 Connector Pin Definition.. .. 24

Table 3-12: M.2 2230 Connector Pin Definition. .. 26

Table 3-13: Mini DisplayPort Pin Definition.. . 27

Table 3-14: USB 3.1 Power (S5/S0) Jumper (JP7) . .. 28

Table 3-15: Power & Reset Connector Pin Definition.... .. 28

Table 3-16: Buzzer Connector Pin Definition... .. 29

Table 3-17: Mic-in & Line-out Connector Pin Definition ........ .. 29

Table 3-18: Speaker Connector Pin Definition... .. 30

Table 3-19: USB 2.0 Connector Pin Definition... .. 30

Table 3-20: Volume & Backlight Control Connector Pin Definition ... 31

Table 3-21: Key Connector Pin Definition.. .. 33

Table 3-22: Fan Connector Pin Definition.. .. 34

Table 3-23: Clear CMOS Jumper (JP1501).. .. 34

Table 3-24: PCIe Gen4 x4 Connector Pin Definition ... .. 36

Table 3-25: COM2 Connector Pin Definition.. . 37

Table 3-26: LED Connector Pin Definition... .. 38

Table 3-27: LED Connector Pin Functions .... .. 39

Table 3-28: I2C Connector 1 & 2 Pin Definition.. .. 39

Table 3-29: RTC Battery Wafer Pin Definition .. .. 40

Table 3-30: DB40 Connector Pin Definition.. .. 42

Table 3-31: GPIO Connector Pin Definition.. .. 44

Table 3-32: GPIO Connector Pin Voltage.. ... 45

Table 3-33: Nano SIM Connector Pin Definition.. .. 46

Table 3-34: Backup Battery Connector Pin Definition..... ... 47

Table 3-35: M.2 2280 Connector Pin Definition. .. 48

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# List of Figures

Figure 2-1: Titan2 Series Block Diagram . 5

Figure 2-2: Titan2-15WP-TGL Dimensions... 7

Figure 2-3: Titan2-21WP-TGL Dimensions.. 8

Figure 2-4: Titan2-24WP-TGL Dimensions.. 9

Figure 2-5: Heat Sink Specifications... .. 10

Figure 2-6: Cable Routing Considerations for Heat Sinks ........... ... 12

Figure 3-1: Titan2 Series External I/O.. . 13

Figure 3-2: DC Input Pin Definition .. . 14

Figure 3-3: Serial Port Pin Definition.. .. 15

Figure 3-4: USB 2.0 Connector Pin Definition.... .. 16

Figure 3-5: Ethernet Connector Pin Definition . . 17

Figure 3-6: Mainboard Connectors (Top).. . 18

Figure 3-7: Mainboard Connectors (Bottom)... . 19

Figure 3-8: Power Connector Pin Definition.. .. 20

Figure 3-9: SATA Data Connector Pin Definition... .. 21

Figure 3-10: SATA Power Connector Pin Definition ... .. 21

Figure 3-11: Touchscreen Connector Pin Definition ... . 22

Figure 3-12: M.2 3042 Connector Pin Definition.. .. 23

Figure 3-13: M.2 2230 Connector Pin Definition.. .. 25

Figure 3-14: Mini DisplayPort Pin Definition.. .. 27

Figure 3-15: USB 3.1 Power (S5/S0) Jumper (JP7) Pin Definition .... 28

Figure 3-16: Power & Reset Connector Pin Definition.. . 28

Figure 3-17: Buzzer Connector Pin Definition... . 29

Figure 3-18: Mic-in & Line-out Connector Pin Definition... .. 29

Figure 3-19: Speaker Connector Pin Definition.. .. 30

Figure 3-20: USB 2.0 Connector Pin Definition.. .. 30

Figure 3-21: Volume & Backlight Control Connector Pin Definition ... 31

Figure 3-22: Key Connector Pin Definition... . 32

Figure 3-23: Fan Connector Pin Definition... .. 34

Figure 3-24: Clear CMOS Jumper (JP1501) Pin Definition...... .. 34

Figure 3-25: PCIe Gen4 x4 Connector Pin Definition .. .. 35

Figure 3-26: COM2 Connector Pin Definition.. .. 37

Figure 3-27: LED Connector Pin Definition... .. 38

Figure 3-28: I2C Connector 1 & 2 Pin Definition.. . 39

Figure 3-29: RTC Battery Wafer Pin Definition .. ... 40

Figure 3-30: DB40 Connector Pin Definition.. ... 40

Figure 3-31: GPIO Connector Pin Definition. .. 43

Figure 3-32: Nano SIM Connector Pin Definition... .. 46

Figure 3-33: Backup Battery Connector Pin Definition.... . 47

Figure 3-34: M.2 2280 Connector Pin Definition .... .. 47

# 1 Introduction

# 1.1 Overview

The Titan2 Series IP69K Stainless Steel Panel PC features a powerful, energy-efficient 11th generation Intel® processor, optional Microsoft® Windows® or Ubuntu Linux operating system in a duable IP69K fanless package. The Titan2 Series is ideal for highquality display experiences in advertising, digital menu board, and digital billboard applications.

# 1.2 Features

 11th Generation Intel® Core™ i5/i3 (Tiger Lake-U SoC) processors
 15.6”/21.5”/23.8" New Generation Stainless Steel Panel PC
 Full IP69K rating for dust and water ingress
Corrosion-resistant 304 Stainless Steel Enclosure (316 as Option)
 All M12 type connectors suite for harsh environments
 Optional for optical bonding and high brightness (1000 nits)
 Standard VESA mounting, Optional Yoke/Pipe mount

# 1.3 Packing List

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any product to ADLINK. Ensure that the following items are included in the package.

 1x Titan2 Series IP69K Stainless Steel Panel PC

# 1.4 Optional Accessories

 M12 Connector to DB-9 Cable, 2m
 M12 Connector to 2xUSB2.0 Cable, 2m
 M12 Connector to 2.5GbE LAN Cable, 2m
 M12 Connector to 1xUSB3. 2 Gen.1 Cable, 2m
Wireless Modules : Wi-Fi kit (w/ antenna), LTE/5G kit (w/ Antenna)
 AC/DC Adapter: Adapter 24V 160W, M12 Connector

# 2 Specifications

2.1 Titan2 Series Specifications

<table><tr><td>Model</td><td>Titan2-15WP-TGL</td><td>Titan2-21WP-TGL</td><td>Titan2-24WP-TGL</td></tr><tr><td>Processor</td><td colspan="3">Intel® CoreTM i5-1145G7E, 2.6(4.1)GHz, 8MB, 15-28W (4C) Intel® CoreTM i3-1115G4E, 3.0(3.9)GHz, 6MB, 15-28W (2C)</td></tr><tr><td>Memory</td><td colspan="3">2x SODIMM non-ECC 2400/3200 MHz DDR4 memory up to 64GB</td></tr><tr><td>Storage</td><td colspan="3">1x M.2 SATA 6 Gbps port, M key 2280 1x 2.5&quot; SSD/HDD SATA 6 Gbps port (optional)</td></tr><tr><td colspan="4">Display and Touch</td></tr><tr><td>Size</td><td>15.6&quot;</td><td>21.5&quot;</td><td>23.8&quot;</td></tr><tr><td>Resolution</td><td colspan="3">1920 x 1080</td></tr><tr><td>Contrast Ratio</td><td>1000:1</td><td>1000:1</td><td>3000:1</td></tr><tr><td>Luminance (cd/m2)</td><td>500 cd/m2 (typ) 1000 cd/m2 (optional)</td><td>400 cd/m2 (typ) 1000 cd/m2 (optional)</td><td>250 cd/m2 (typ) 1000 cd/m2 (optional)</td></tr><tr><td>Backlight Life (Hrs)</td><td colspan="3">50,000</td></tr><tr><td>Viewing Angle (U/D/R/L)</td><td colspan="3">89/89/89/89</td></tr><tr><td>Touch Points</td><td colspan="3">10 points</td></tr><tr><td>Touch Structure</td><td colspan="3">Glass/Glass</td></tr><tr><td>Surface Hardness</td><td colspan="3">7H</td></tr><tr><td>Surface Treatment</td><td colspan="3">AS coating</td></tr><tr><td colspan="4">External I/O</td></tr><tr><td>IP69K I/O Ports (M12 stainless connectors waterproof covers)</td><td colspan="3">2x USB 2.0 (A-coded) 1x M12 for RS-232/422/485 (default RS-232, A-coded) 1x M12 for 2.5GbE LAN (X-coded) Optional: 1x USB 3.2 Gen.1 1x 2.5GbE LAN</td></tr><tr><td colspan="4">Power</td></tr><tr><td>Power Input</td><td colspan="3">AT/ATX (default: AT mode) 24V DC, OVP/UVP protection</td></tr><tr><td>Power Connector</td><td colspan="3">1x 4-pin power connector</td></tr><tr><td>Power/Fail Reset</td><td colspan="3">1x wafer supports system reset, power button and power LED</td></tr></table>

Table 2-1: Titan2 Series Specifications

<table><tr><td>Model</td><td>Titan2-15WP-TGL</td><td>Titan2-21WP-TGL</td><td>Titan2-24WP-TGL</td></tr><tr><td colspan="4">Environmental</td></tr><tr><td>Operating Temperature</td><td>-10°C to 50°C</td><td>0°C to 50°C</td><td>0°C to 40°C</td></tr><tr><td>Storage Temperature</td><td colspan="3">-20°C to 60°C</td></tr><tr><td>Humidity</td><td colspan="3">Up to 95% @ 40°C</td></tr><tr><td>Vibration</td><td colspan="3">10 ~ 500 Hz, 1.87G for X, Y, Z (IEC 60068-2-64)</td></tr><tr><td>Shock</td><td colspan="3">Titan2-15WP-TGL/21WP-TGL: 30 G, half sine 11ms duration (w/ SSD)Titan2-24WP-TGL: 20 G, half sine 11ms duration (w/ SSD)</td></tr><tr><td>Drop</td><td colspan="3">Refer to ISTA 1A</td></tr><tr><td>IP Rating</td><td colspan="3">Total IP69K</td></tr><tr><td>ESD</td><td colspan="3">Air: ±8kV, Contact: ±4kV</td></tr><tr><td>EMC/Safety Compliance</td><td colspan="3">EMI: IEC/EN 61000-3-2, IEC/EN 61000-3-3, EN 61000-6-4, EN 55032EMS: EN 55035, EN 61000-6-2EMC: CE, FCC Class B, IEC 60601-1-2, UNECE R10, EN 50121-3-2Safety: Compliant with IEC 62368-1:2014Note: Titan2-TGL has passed pre-compliance testing of EMI, EMS, EMC and Safety.</td></tr><tr><td colspan="4">Software</td></tr><tr><td>Watch Dog Timer</td><td colspan="3">Supported</td></tr><tr><td>Operating Systems</td><td colspan="3">Windows® 10 IoT Enterprise x64 bitWindows 11Linux Ubuntu 22.04 LTS</td></tr><tr><td colspan="4">Mechanical</td></tr><tr><td>Size</td><td>15.6&quot;</td><td>21.5&quot;</td><td>23.8&quot;</td></tr><tr><td>Construction</td><td colspan="3">Corrosion-resistant 304 Stainless Steel Enclosure (316 as Option)</td></tr><tr><td>Dimensions (HxWxD mm)</td><td>261.49x402.06x55.2</td><td>337.1x537.14x55.2</td><td>364.36x584.94x55.2</td></tr><tr><td>Weight</td><td>7kg</td><td>10kg</td><td>13kg</td></tr><tr><td>Mounting (Optional)</td><td colspan="3">VESA 100x100 (Titan2-15WP-TGL/21WP-TGL)/200 x 100(Titan2-24WP-TGL) mm Mounting, Yoke/Pipe mount options</td></tr></table>

Table 2-1: Titan2 Series Specifications

2.2 Titan2 Series Block Diagram
![**Central Block:**\n*   Intel® Tiger Lake-U Processor\n    *   i5 - 1145G7E\n    *   i3 - 1115G4E\n\n**Left Side Connections (Inputs/Interfaces):**\n*   **LVDS CN** connects to **eDP (optional)**, which connects to **eDP to LVDS PTN3460**, leading to **DDI A**.\n*   **DP CN** connects via **TCP 0**.\n*   **BIOS** and **TPM SLM9670** connect via **SPI1**.\n*   **M.2 B+M Key** and **2.5' HDD** connect via **SATA**.\n*   Two instances of **RJ45** connect to **I225**, then to **0 ohm Option**, leading to **PCIe**.\n*   **wafer** connects via **RTC**.\n*   **Wafer** connects via **4DO** and **4DI**.\n*   **Key Pad** connects via **GPIO#37** to **EC IT8528**.\n*   **LVDS BL CN Volume up/down** connects via **PWM** to **EC IT8528**.\n*   **EC IT8528** connects via **LPC**.\n\n**Right Side Connections (Outputs/Peripherals):**\n*   **DDR4 CH1** and **DDR4 CH2** connect to **DDR4 SO-DIMM**.\n*   **PCIe** connects to **M.2 A/E Key**.\n*   **USB2** connects to **M.2 B Key**, which connects to **Nano USIM**. **USB3** also connects to this line.\n*   **HDA** connects to **92HD91**, which splits to **SPK** (to **Wafer**) and **MIC IN** (to **Wafer**).\n*   Two instances of **USB3,USB2** connect to **0 ohm Option**, then to **Re-driver NB7NPQ022**, leading to **Dual USB3.2 typeA**.\n*   **USB3,USB2** connects directly to **USB3.1+USB2.0 typeA**.\n*   **USB2** connects to **0 ohm Option**, then to **PM6000**, then via **5-wire** to **RES touch panel**.\n*   **USB2** connects via **0 ohm Option** to **CAP touch panel**.\n*   **USB2** connects directly to **Wafer for camera module**.\n*   **I2C** connects to **Wafer for DIO board**.\n*   **SMBUS** connects to **Lite BMC STM32L071RBH**, which connects via **PWM** to **FAN CONN**, **HW monitor**, and **Thermal sensor *2**.\n*   **SMBUS** connects to **LED Driver**, which connects via **PWM** to **Wafer**.\n*   **LPC** connects to **LPC to UART NCT5104D**, which connects via **SP339E** to **Switch TMUX6112**, leading to **Full COM DB-9** and **Full COM Wafer**.](.sp-titan2-50m-p5300-1010-11-240912/7e638663217b50aef307b21441aa5c1a2be318530029816008dfbeb026623a23.jpg)

Figure 2-1: Titan2 Series Block Diagram

# 2.3 Power

Power supply options:

 160W (24V DC/6.67A)

# 2.3.1 Power Consumption

Power consumption is based on lab data in which 24V DC is applied and current is measured by the DC power supply. The power consumption (W) is calculated as the product of applied voltage (V) and current (A). Platforms tested for this data have available external I/O interfaces, and are attached to supported devices such as keyboard/ mouse, USB dummy load, COM loopback, LAN port, and with an internal SSD drive installed. Information is presented for reference only. Actual power consumption will vary with different attached devices and operating systems.

<table><tr><td>Configuration</td><td>Idle</td><td>Full Load</td></tr><tr><td>Titan2-15WP-i5, 24V</td><td>34.2W</td><td>54.7W</td></tr><tr><td>Titan2-21WP-i5, 24V</td><td>45.3W</td><td>72.4W</td></tr><tr><td>Titan2-24WP-i5, 24V</td><td>52.7W</td><td>99.6W</td></tr></table>

Table 2-2: Power Consumption

# 2.4 Mechanical Dimensions

![The image displays a standard white document icon with a folded upper-left corner and faint horizontal lines representing text. Superimposed over the center of the document is a large, bold red checkmark.](.sp-titan2-50m-p5300-1010-11-240912/7bfda021cc21db5f6f90d451131c5c13feb13648f792503c400659e4d288787c.jpg)
NOTE:

All dimensions are in millimeters, unless noted.

# 2.4.1 Titan2-15WP-TGL Dimensions

![This image is a technical line drawing showing the dimensional specifications and port layout of an electronic device, likely a display panel.\n\n**Front View (Center):**\n*   Overall Width: **402.06 ± 2 (W)**\n*   Inner Width (Active Area): **345.23 (VA)**\n*   Overall Height: **261.49 ± 2 (H)**\n*   Inner Height (Active Area): **194.54 (VA)**\n*   A Wi-Fi symbol is visible at the bottom right corner.\n\n**Left Side View:**\n*   Overall Height: **107.65**\n*   Depth of a cutout: **27.6**\n\n**Right Side View:**\n*   Overall Depth: **55.2 ± 2 (D)**\n*   Bottom protrusion depth: **17.2 ± 2**\n*   Mounting note: **2-M4 max depth 6mm**\n\n**Rear View (Bottom):**\n*   Mounting note: **4-M4 max depth 6mm**\n*   Horizontal mounting hole spacing: **100**\n*   Vertical mounting hole spacing: **100**\n*   Port labels (from left to right): **V610T**, **DO-IN**, **COM**, **USB2.0**, **LAN**, **USB2.0**, **LAN**\n*   Warning text under a screw icon: **DO NOT REMOVE**](.sp-titan2-50m-p5300-1010-11-240912/b038277c18b83b1605533f062412a43dd5611a350192f598cd25937b92e92e95.jpg)
Figure 2-2: Titan2-15WP-TGL Dimensions

2.4.2 Titan2-21WP-TGL Dimensions
![This image is a technical engineering drawing of a rectangular electronic device, likely a display, showing front, side, and rear views with dimensional specifications.\n\n**Front View (Center):**\n*   Outer Width: 537.14 ± 2 (W)\n*   Inner Width (VA): 477.64 ± 0.3 (VA)\n*   Outer Height: 337.1 ± 2 (H)\n*   Inner Height (VA): 269.11 ± 0.3 (VA)\n*   Corner Radius: R20.25\n\n**Left Side View:**\n*   Dimension: 100\n*   Dimension: 27.6\n\n**Right Side View:**\n*   Depth: 55.2 ± 2 (D)\n*   Dimension: 17.2 ± 2\n*   Text: 2-M4 max depth 6mm\n\n**Rear View (Bottom):**\n*   Mounting hole spacing: 100, 100\n*   Text: 4-M4 max depth 6mm\n*   Port labels (from left to right):\n    *   VRF (above a circle with a minus sign)\n    *   DO NOT REMOVE (below the first symbol)\n    *   DO-NI (above a black circle)\n    *   DO (above a white circle)\n    *   USB3.0 (above a white circle)\n    *   LAN (above a white circle)\n    *   USB3.0 (above a white circle)\n    *   LAN (above a hexagon)](.sp-titan2-50m-p5300-1010-11-240912/ecf51fa8ebe116e730248a3eb007805804c50407c2657740df5cf74e2596a5a1.jpg)
Figure 2-3: Titan2-21WP-TGL Dimensions

2.4.3 Titan2-24WP-TGL Dimensions
![The image is a technical engineering drawing of a flat panel display, showing four views with dimensional annotations.\n\n**Front View (Center):**\n*   Top dimension: **584.94 ± 2 (W)**\n*   Inner screen width: **528.44 (VA)**\n*   Top bezel thickness: **6.5**\n*   Left screen height: **297.86 (VA)**\n*   Right total height: **364.36 ± 2 (H)**\n*   Bottom bezel thickness: **3**\n*   Bottom right mounting: **2-M4 max depth 6mm**\n\n**Left Side View:**\n*   Total height: **150**\n*   Depth/Thickness: **27.6**\n\n**Right Side View:**\n*   Total depth: **55.2 ± 2 (D)**\n*   Mounting hole position: **17.2 ± 2**\n\n**Rear View (Bottom):**\n*   VESA mounting width: **200**\n*   VESA mounting height: **100**\n*   Screw specification: **4-M4 max depth 6mm**\n*   Text under port icons: **DO NOT REMOVE**](.sp-titan2-50m-p5300-1010-11-240912/97a89c3644315549c92da623c0f0eb9e88ca2bf1d83bfa46d17cdc4794d42cc4.jpg)
Figure 2-4: Titan2-24WP-TGL Dimensions

# 2.5 Thermal Options

# 2.5.1 Heat Sink Specifications

![Technical line drawing of a rectangular frame with internal components and bolt holes (no text or symbols)](.sp-titan2-50m-p5300-1010-11-240912/a6f53ad793485900e173d2c3fb9c00c0f08a9cb56c96d3ac0e576071d80519d6.jpg)

![2 ± 0.3\nCoat the external rivets\nwith waterproof silicone.*4PCS\nLock with M3 Nut*7pcs\n8\n8\nB\nB\nB\nB\nB](.sp-titan2-50m-p5300-1010-11-240912/b45b26f6789d9253a574289b77066e0748bfda5c020181c0811e12ffe7586c46.jpg)

Figure 2-5: Heat Sink Specifications

<table><tr><td>No.</td><td>Description</td><td>Part Number</td><td>Material</td><td>Dimensions</td></tr><tr><td>1</td><td>TITAN2-238_CR_BACK</td><td>34-35275-0000-B0</td><td rowspan="3">SUS304, T=2.0mm/AL,T=5.0mm,Production: NCTFINISH:Hair-line SurfaceTreatment</td><td>350*164*5mm</td></tr><tr><td>2</td><td>TITAN2-215_CR_BACK</td><td>34-35480-0000-A0</td><td>350*164*5mm</td></tr><tr><td>3</td><td>TITAN2-156_CR_BACK</td><td>34-35492-0000-A0</td><td>350*164*5mm</td></tr></table>

Table 2-3: Heat Sink Components

![The image displays a white document icon featuring a folded top-left corner and faint horizontal grey lines. A large, bold red checkmark is superimposed over the left side of the document.](.sp-titan2-50m-p5300-1010-11-240912/6cc140d9fb964cf538c07d307dd9084caa86d0955d289d040e9471854e368e8d.jpg)
NOTE:

All dimensions are in millimeters, unless noted.

![A yellow triangular warning sign with a black border featuring a large black exclamation mark in the center, set against a white background.](.sp-titan2-50m-p5300-1010-11-240912/c83e6e4a4ff56027407d7426238b651d571ad8df6f2832d73b780087541f41f0.jpg)
CAUTION:

Due to radiant heat from the passive heat sink, make sure the heat sink is positioned at least 10cm from the nearest wall.

# 2.5.2 Cable Routing Considerations for Heat Sinks

Cable routing should avoid high temperature areas as shown.

![This page intentionally left blank.](.sp-titan2-50m-p5300-1010-11-240912/13ed4ed46b1aedb87d91b693aca4a065107a9f17d511208de44c5522f335f028.jpg)

Figure 2-6: Cable Routing Considerations for Heat Sinks

![The image displays an icon of a white document or piece of paper with a folded upper-left corner. Faint gray horizontal lines run across the document, resembling text or a list. A large, bold red checkmark is superimposed diagonally over the center of the paper.](.sp-titan2-50m-p5300-1010-11-240912/b5734eb2b7e57b1f64826eb7c7c8026c5f5c5173d8da6584afa90944e0695a7a.jpg)
NOTE:

Heat sink design optimized for open-frame installations, such as a kiosk.

For panel PCs, a different design may be required. Consult your ADLINK sales representative for guidance.

# 3 System Layout

# 3.1 External I/O Connectors

The Titan2 Series provides the following external I/O connectors.

![DC-IN\nA](.sp-titan2-50m-p5300-1010-11-240912/f5546c5bc3e29e0e72afd12322cbaa517462874cadf84886443a43434f422d76.jpg)

![COM\nB](.sp-titan2-50m-p5300-1010-11-240912/ddeaa397a3d6af58f98c367f806af7d189fb90b1ef485a4a6dcd7858bb45ddb6.jpg)

![USB2.0\nC](.sp-titan2-50m-p5300-1010-11-240912/42cbe9124e84f6b7fe7e752b87073d2d48b469fa642653b8874ae102f4bf8678.jpg)

![LAN\nD](.sp-titan2-50m-p5300-1010-11-240912/9634ff7860ed5d52dc763168595f7c39db46cb1d3b0b0e317146b86811ab4b0e.jpg)

![Chemical structure of USB3.0 with a cyclohexene ring and substituent E](.sp-titan2-50m-p5300-1010-11-240912/30c85010b0a0a6d35b9dff5231fedb2f5a7120959660bef52342b119b6af6314.jpg)

![Chemical structure of a fluorinated cyclohexane ring with label 'LAN' above and 'F' below](.sp-titan2-50m-p5300-1010-11-240912/0948bc4126e443312b7388c3e39667327385c654e68556bd0e503642f1073d4d.jpg)

Figure 3-1: Titan2 Series External I/O

<table><tr><td>A</td><td>1x M12 for DC power</td><td>T-coded</td></tr><tr><td>B</td><td>1x M12 for RS-232/422/485 (default RS-232)</td><td>A-coded</td></tr><tr><td>C</td><td>1x M12 for 2x USB 2.0</td><td>A-coded</td></tr><tr><td>D</td><td>1x M12 for 2.5GbE LAN</td><td>X-coded</td></tr><tr><td>E</td><td>1x M12 for USB3.2 Gen.1 (Optional)</td><td>X-coded</td></tr><tr><td>F</td><td>1x M12 for 2.5GbE LAN (Optional)</td><td>X-coded</td></tr></table>

Table 3-1: External I/O Legend

# 3.1.1 DC Input

The M12 DC (24V) input is a male connector with 4 pins in $\mathsf { a } \ ^ { \ast } \mathsf { T } .$ - coded” configuration.

![②\n①\n③\n④](.sp-titan2-50m-p5300-1010-11-240912/539cc66bacbd953da75bc727b97e50ab8c324314c3fe1cae7826722fb4810e86.jpg)

Figure 3-2: DC Input Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>24VDC</td></tr><tr><td>4</td><td>24VDC</td></tr></table>

Table 3-2: DC Input Pin Definition

# 3.1.2 Serial Port Connector

Through a M12 male A-coded connector, COM1 supports RS-232 (default) and RS-422/RS-485 modes, by BIOS setting.

![②\n①\n③\n⑧\n⑦\n④\n⑤\n⑥](.sp-titan2-50m-p5300-1010-11-240912/adbe806c08b07b1902245c7a47c491589ff560ca538eadfc16fa9cf7f45d039c.jpg)

Figure 3-3: Serial Port Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CD</td></tr><tr><td>2</td><td>RXD</td></tr><tr><td>3</td><td>TXD</td></tr><tr><td>4</td><td>DTR</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>DSR</td></tr><tr><td>7</td><td>RTS</td></tr><tr><td>8</td><td>CTS</td></tr></table>

Table 3-3: Serial Port Pin Definition

# 3.1.3 USB 2.0 Connector

USB 2.0 M12 male A-coded connector, up to 480 Mbps with 500 mA power current and OCP protection.

![1\n2\n7\n8\n3\n6\n4\n5](.sp-titan2-50m-p5300-1010-11-240912/2da1b2811e9fe4922199527776d96d3b4c1916b9b797dbc0a474b8b5497f0886.jpg)

Figure 3-4: USB 2.0 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>D2-</td></tr><tr><td>2</td><td>D1-</td></tr><tr><td>3</td><td>D1+</td></tr><tr><td>4</td><td>USB1 5V</td></tr><tr><td>5</td><td>GND2</td></tr><tr><td>6</td><td>USB2 5V</td></tr><tr><td>7</td><td>D2+</td></tr><tr><td>8</td><td>GND1</td></tr></table>

Table 3-4: USB 2.0 Connector Pin Definition

# 3.1.4 2.5 Gigabit Ethernet Connector

One 2.5 Gigabit Intel® Ethernet Controller i225 Series with M12 9- pin X-code male connector.

![①\n②\n③\n④\n⑤\n⑥\n⑦\n⑧](.sp-titan2-50m-p5300-1010-11-240912/768acc4f68e320b2e0a76a56e29d51d34fb5dda1d3570e4b47047436df07f3f8.jpg)

Figure 3-5: Ethernet Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>White/Orange</td></tr><tr><td>2</td><td>Orange</td></tr><tr><td>3</td><td>White/Green</td></tr><tr><td>4</td><td>Green</td></tr><tr><td>5</td><td>White/Blue</td></tr><tr><td>6</td><td>Blue</td></tr><tr><td>7</td><td>White/Brown</td></tr><tr><td>8</td><td>Brown</td></tr><tr><td>S</td><td>Braid</td></tr></table>

Table 3-5: Ethernet Pin Definition

# 3.2 Internal I/O Connectors

![The image displays a standard safety warning sign. It features a red equilateral triangle pointing upwards, containing a large white exclamation point in the center. Below the triangle is the word 'WARNING' printed in bold, black, capital letters.](.sp-titan2-50m-p5300-1010-11-240912/0be5d81749c82e602f06f3f830ac6620c5b5b14de50c8819b4f2794ea2c92be0.jpg)

Installation of add-on devices must be carried out by ADLINK service personnel only. Users must not disassemble the device themselves.

L'installation de périphériques complémentaires doit être effectuée uniquement par le personnel de service ADLINK. Les utilisateurs ne doivent pas démonter l'appareil eux-mêmes.

# 3.2.1 Mainboard Connector Locations

![C D E F G H\nB C B A I J K L M N\nA C B O P Q](.sp-titan2-50m-p5300-1010-11-240912/4680b08e4553df0a4c354e7d7b75b69d65a3cd7ccf632a77302011d4cb957f4d.jpg)

Figure 3-6: Mainboard Connectors (Top)

![V\nW\nX\nY\nU\nT\nS\nZ\nAA\nR](.sp-titan2-50m-p5300-1010-11-240912/f9dd5f145c3568f7c87bb3e7f8a22ba2af8c7457324d6522c3fcfbc25992e16d.jpg)

Figure 3-7: Mainboard Connectors (Bottom)

<table><tr><td>A</td><td>Power connector</td><td>N</td><td>Key connector (optional)</td></tr><tr><td>B</td><td>2.5” SATA data &amp; power</td><td>O</td><td>Fan connector</td></tr><tr><td>C</td><td>Touchscreen</td><td>P</td><td>Clear CMOS Jumper (JP1501)</td></tr><tr><td>D</td><td>M.2 3042, B Key for 4G/5G</td><td>Q</td><td>PCIe Gen4 x4 slot</td></tr><tr><td>E</td><td>M.2 2230, A/E Key for WiFi/BT</td><td>R</td><td>COM2 wafer</td></tr><tr><td>F</td><td>Mini DP connector</td><td>S</td><td>LED wafer</td></tr><tr><td>G</td><td>USB 3.1 Power (S5/S0) Jumper (JP7)</td><td>T</td><td>I2C connector 1</td></tr><tr><td>H</td><td>PWR &amp; RST wafer</td><td>U</td><td>I2C connector 2</td></tr><tr><td>I</td><td>Buzzer</td><td>V</td><td>RTC Battery wafer</td></tr><tr><td>J</td><td>Line-out &amp; Mic-in</td><td>W</td><td>DB40 connector</td></tr><tr><td>K</td><td>Speaker</td><td>X</td><td>GPIO wafer</td></tr><tr><td>L</td><td>USB 2.0</td><td>Y</td><td>Nano SIM Card Socket</td></tr><tr><td>M</td><td>Volume &amp; Backlight wafer (optional)</td><td>Z</td><td>Backup battery connector (optional)</td></tr><tr><td colspan="2"></td><td>AA</td><td>M.2 2280 SATA SSD connector</td></tr></table>

Table 3-6: Mainboard Connector Legend

# 3.2.2 Power Connector

The 6-pin power connector connects an AC/DC power supply adapter, DC to DC power module and battery, with AT and ATX power modes (AT mode start is controlled by BIOS).

![The image displays a technical line drawing of a rectangular connector housing. Inside the housing is a grid of six circular contacts arranged in two columns and three rows. The contacts are labeled with numbers: the left column contains 8, 10, and 12 from top to bottom, while the right column contains 9, 11, and 13. To the right of the housing, the number '1' is visible. The housing outline includes rectangular slots at the top and bottom edges and a rectangular protrusion extending from the left side.](.sp-titan2-50m-p5300-1010-11-240912/2421507a7dc216d3b2c0a3be17c3c71aaf0edb37b294ce9291252be130fff6cf.jpg)
Figure 3-8: Power Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>PWR_CONN_IN</td></tr><tr><td>5</td><td>PWR_CONN_IN</td></tr><tr><td>6</td><td>PWR_CONN_IN</td></tr></table>

Table 3-7: Power Connector Pin Definition

# 3.2.3 SATA Data & Power Connectors

The SATA data and power connectors are used to connect an internal $2 . 5 "$ HDD.

![A vertical technical drawing labeled with the number '1' to its left. The image depicts a rectangular mechanical assembly, resembling a door lock mechanism, with a stepped outer edge on the left side. Inside the frame, there is a central vertical slot containing a rectangular block. Above and below this block are circular holes. Further down, a smaller rectangular component is visible, along with a small square near the bottom left corner.](.sp-titan2-50m-p5300-1010-11-240912/bf887a9214ea2528a47e8e9ddc6c6196e623cb98c491b6255e3d66afdca951c2.jpg)
Figure 3-9: SATA Data Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>SATA_TX1_P</td></tr><tr><td>3</td><td>SATA_TX1_N</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>SATA_RX1_N</td></tr><tr><td>6</td><td>SATA_RX1_P</td></tr><tr><td>7</td><td>GND</td></tr></table>

Table 3-8: SATA Data Connector Pin Definition
![The image displays a vertical rectangle containing a column of six symbols. From top to bottom, there are four small circles, followed by a circle containing a plus sign (+), and finally a square containing a minus sign (-). The number 1 is positioned to the right of the bottom square.](.sp-titan2-50m-p5300-1010-11-240912/96cf14711d6531d6b5aa8b007cb4aa7d5578d636a48ed22885a82faff3b0ce85.jpg)
Figure 3-10: SATA Power Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>P_+5V_S0</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>P_+3V3_S0</td></tr></table>

Table 3-9: SATA Power Connector Pin Definition

# 3.2.4 Touchscreen Connector

The USB 2.0 connector supports a PCAP touchscreen.

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/27eea61ce969651bec8c1fb356463ee154e509a0e131dfe416b4d5b8dbac323d.jpg)

Figure 3-11: Touchscreen Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TSC_D+</td></tr><tr><td>3</td><td>TSC_D-</td></tr><tr><td>4</td><td>P5V_U2_TOU</td></tr></table>

Table 3-10: Touchscreen Connector Pin Definition

# 3.2.5 M.2 3042 Connector

The M.2 B key port supports standard USB3.1 and USB2.0 for 4G/ 5G module.

![2\n74\n1\n75](.sp-titan2-50m-p5300-1010-11-240912/0b4daec51612386c82934e1c4bc60babdcac0a20fc520db780b55668a705dd96.jpg)

Figure 3-12: M.2 3042 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>M2B_CONFIG_3</td><td>2</td><td>P_+3V3_NGFF_B</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>P_+3V3_NGFF_B</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>FULL_CARD_POWER_OFF</td></tr><tr><td>7</td><td>U2_USB1_P</td><td>8</td><td>W_DISABLE1</td></tr><tr><td>9</td><td>U2_USB1_N</td><td>10</td><td>NC</td></tr><tr><td>11</td><td>GND</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>M2B_CONFIG_0</td><td>22</td><td>NC</td></tr><tr><td>23</td><td>NC</td><td>24</td><td>NC</td></tr><tr><td>25</td><td>NC</td><td>26</td><td>NC</td></tr><tr><td>27</td><td>NC</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>U3_USB1_RX_N_R</td><td>30</td><td>M2_UIM_RST</td></tr><tr><td>31</td><td>U3_USB1_RX_P_R</td><td>32</td><td>M2_UIM_CLK</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>M2_UIM_DATA</td></tr><tr><td>35</td><td>U3_USB1_TX_N_R</td><td>36</td><td>P_+3V3_UIM_M2</td></tr><tr><td>37</td><td>U3_USB1_TX_P_R</td><td>38</td><td>NC</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>NC</td></tr><tr><td>41</td><td>NC</td><td>42</td><td>NC</td></tr><tr><td>43</td><td>NC</td><td>44</td><td>NC</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td></tr><tr><td>47</td><td>NC</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>NC</td><td>50</td><td>M2B_PLTRST_BUF-L</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>NC</td></tr><tr><td>53</td><td>NC</td><td>54</td><td>NC</td></tr><tr><td>55</td><td>NC</td><td>56</td><td>NC</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>NC</td></tr><tr><td>59</td><td>NC</td><td>60</td><td>NC</td></tr><tr><td>61</td><td>NC</td><td>62</td><td>NC</td></tr><tr><td>63</td><td>NC</td><td>64</td><td>NC</td></tr><tr><td>65</td><td>NC</td><td>66</td><td>M2_UIM1_DET</td></tr><tr><td>67</td><td>WWAN_RESET-L</td><td>68</td><td>NC</td></tr><tr><td>69</td><td>M2B_CONFIG_1</td><td>70</td><td>P_+3V3_NGFF_B</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>P_+3V3_NGFF_B</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>P_+3V3_NGFF_B</td></tr><tr><td>75</td><td>M2B_CONFIG_2</td><td></td><td></td></tr></table>

Table 3-11: M.2 3042 Connector Pin Definition

# 3.2.6 M.2 2230 Connector

The M.2 E key port supports standard USB for a WiFi/Bluetooth module.

![74\n75\n2\n1](.sp-titan2-50m-p5300-1010-11-240912/b874e5ee39ebc293df91b13f43574aac4ce31ebe067c8c225c86204eb96fb53b.jpg)

Figure 3-13: M.2 2230 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>M2B_CONFIG_3</td><td>2</td><td>P_+3V3_NGFF_B</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>P_+3V3_NGFF_B</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>FULL_CARD_POWER_OFF</td></tr><tr><td>7</td><td>U2_USB1_P</td><td>8</td><td>W_DISABLE1</td></tr><tr><td>9</td><td>U2_USB1_N</td><td>10</td><td>NC</td></tr><tr><td>11</td><td>GND</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>M2B_CONFIG_0</td><td>22</td><td>NC</td></tr><tr><td>23</td><td>NC</td><td>24</td><td>NC</td></tr><tr><td>25</td><td>NC</td><td>26</td><td>NC</td></tr><tr><td>27</td><td>NC</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>U3_USB1_RX_N_R</td><td>30</td><td>M2_UIM_RST</td></tr><tr><td>31</td><td>U3_USB1_RX_P_R</td><td>32</td><td>M2_UIM_CLK</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>M2_UIM_DATA</td></tr><tr><td>35</td><td>U3_USB1_TX_N_R</td><td>36</td><td>P_+3V3_UIM_M2</td></tr><tr><td>37</td><td>U3_USB1_TX_P_R</td><td>38</td><td>NC</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>NC</td></tr><tr><td>41</td><td>NC</td><td>42</td><td>NC</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>43</td><td>NC</td><td>44</td><td>NC</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td></tr><tr><td>47</td><td>NC</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>NC</td><td>50</td><td>M2B_PLTRST_BUF-L</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>NC</td></tr><tr><td>53</td><td>NC</td><td>54</td><td>NC</td></tr><tr><td>55</td><td>NC</td><td>56</td><td>NC</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>NC</td></tr><tr><td>59</td><td>NC</td><td>60</td><td>NC</td></tr><tr><td>61</td><td>NC</td><td>62</td><td>NC</td></tr><tr><td>63</td><td>NC</td><td>64</td><td>NC</td></tr><tr><td>65</td><td>NC</td><td>66</td><td>M2_UIM1_DET</td></tr><tr><td>67</td><td>WWAN_RESET-L</td><td>68</td><td>NC</td></tr><tr><td>69</td><td>M2B_CONFIG_1</td><td>70</td><td>P_+3V3_NGFF_B</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>P_+3V3_NGFF_B</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>P_+3V3_NGFF_B</td></tr><tr><td>75</td><td>M2B_CONFIG_2</td><td></td><td></td></tr></table>

Table 3-12: M.2 2230 Connector Pin Definition

# 3.2.7 Mini DisplayPort Connector

![19\n1\n20\n2](.sp-titan2-50m-p5300-1010-11-240912/8aaf1314c755551a92f6ba1737389e6bba6fbfab782a84445fe12d9db1b8a3cd.jpg)

Figure 3-14: Mini DisplayPort Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>CON_TCP2_HPD</td></tr><tr><td>3</td><td>CON_TCP2_TX0_P</td></tr><tr><td>4</td><td>CON_TCP2_DDC_AUX_SEL</td></tr><tr><td>5</td><td>CON_TCP2_TX0_N</td></tr><tr><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>GND</td></tr><tr><td>9</td><td>CON_TCP2_TX1_P</td></tr><tr><td>10</td><td>CON_TCP2_TX3_P</td></tr><tr><td>11</td><td>CON_TCP2_TX1_N</td></tr><tr><td>12</td><td>CON_TCP2_TX3_N</td></tr><tr><td>13</td><td>GND</td></tr><tr><td>14</td><td>GND</td></tr><tr><td>15</td><td>CON_TCP2_TX2_P</td></tr><tr><td>16</td><td>CON_TCP2_I2CCLK_AUX_P</td></tr><tr><td>17</td><td>CON_TCP2_TX2_N</td></tr><tr><td>18</td><td>CON_TCP2_I2CCLK_AUX_N</td></tr><tr><td>19</td><td>GND</td></tr><tr><td>20</td><td>P_+3V3_DP2</td></tr></table>

Table 3-13: Mini DisplayPort Pin Definition

# 3.2.8 USB 3.1 Power (S5/S0) Jumper $( \mathsf { J } \mathsf { P } 7 )$

![The image displays a row of three identical rectangular icons near the top, each containing a geometric symbol resembling a square with a smaller square inside. Below the leftmost icon is the number 1.](.sp-titan2-50m-p5300-1010-11-240912/fb687592abec7e2cccc5707fd8d8c60e3b9561961d21ee5deee8242a563a7bdf.jpg)
Figure 3-15: USB 3.1 Power (S5/S0) Jumper (JP7) Pin Definition

<table><tr><td colspan="2">JP7 USB S5/S0 Power</td></tr><tr><td>1-2</td><td>+5V_A (Default)</td></tr><tr><td>2-3</td><td>+5V_S0</td></tr></table>

Table 3-14: USB 3.1 Power (S5/S0) Jumper (JP7)

# 3.2.9 Power & Reset Connector

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/899f5085556aa7168fc697505d70f8204a28a3abfffac1a3d078120c5ed499df.jpg)

Figure 3-16: Power & Reset Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_A</td></tr><tr><td>2</td><td>PWRBTN-L_R</td></tr><tr><td>3</td><td>SYS_RESET-L_R</td></tr><tr><td>4</td><td>SIG_PWRLED-L</td></tr><tr><td>5</td><td>GND</td></tr></table>

Table 3-15: Power & Reset Connector Pin Definition

# 3.2.10 Buzzer Connector

![The image is a black line drawing on a white background depicting the front view of a USB Type-A connector. It features a rectangular metal housing with vertical outlines on the left and right sides. The top section shows an internal plastic insert containing a central U-shaped cutout flanked by two vertical rectangular shapes. Two small rectangular tabs extend downward from the bottom of the housing.](.sp-titan2-50m-p5300-1010-11-240912/5f9d5edc2f551a67e87dee930ec7fe23799c62f54d6f70303c55e436c940d490.jpg)

Figure 3-17: Buzzer Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_S0</td></tr><tr><td>2</td><td>N40235133</td></tr></table>

Table 3-16: Buzzer Connector Pin Definition

# 3.2.11 Mic-in & Line-out Connector

The Mic-in/Line-out supports connecting to speakers via cable.

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/71697ba832c77ad769e2c3764bd9573157c6e35ca945cf79339f441440d2c9ba.jpg)

Figure 3-18: Mic-in & Line-out Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CON_MIC1_IN</td></tr><tr><td>2</td><td>CON_LINE1_OUT_L</td></tr><tr><td>3</td><td>CON_LINE1_OUT_R</td></tr><tr><td>4</td><td>AGND_AUDIO</td></tr></table>

Table 3-17: Mic-in & Line-out Connector Pin Definition

# 3.2.12 Speaker Connector

The speaker connector supports 2 2x 2W speakers via cable.

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/9068b42add53aeae6dda27a474f989bafbd07587ef5da90c65d5491d782b8dd0.jpg)

Figure 3-19: Speaker Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>AMP_L+</td></tr><tr><td>2</td><td>AMP_L-</td></tr><tr><td>3</td><td>AMP_R+</td></tr><tr><td>4</td><td>AMP_R-</td></tr></table>

Table 3-18: Speaker Connector Pin Definition

# 3.2.13 USB 2.0 Connector

![This is a black and white line drawing depicting a schematic layout, likely a floor plan or facade of a building. The image is enclosed within a thin outer rectangular border.\n\nInside the border, there is a large central rectangular section containing a grid of three horizontal rows, with each row consisting of eight vertical rectangular shapes resembling windows or rooms. Flanking this central section on the far left and far right are two narrower vertical rectangular structures.](.sp-titan2-50m-p5300-1010-11-240912/c48e4467b8a28507e4885f196edec14f5bc2f2cd5f31834c7ab643ff52873201.jpg)

Figure 3-20: USB 2.0 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P5V_U2_CAM</td></tr><tr><td>2</td><td>CN_U2_P8_N</td></tr><tr><td>3</td><td>CN_U2_P8_P</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>NC</td></tr><tr><td>6</td><td>NC</td></tr></table>

Table 3-19: USB 2.0 Connector Pin Definition

# 3.2.14 Volume & Backlight Control Connector

Controls volume and adjusts display brightness.

![Pure technical diagram of a rectangular electronic component with no text or symbols](.sp-titan2-50m-p5300-1010-11-240912/3fc36c73ae5e86e4faa63c26e9c52a3b1e2dfa5e47b07f72fc534d84e3f74ab4.jpg)

Figure 3-21: Volume & Backlight Control Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_S0</td></tr><tr><td>2</td><td>EC_BTN_33</td></tr><tr><td>3</td><td>EC_BTN_34</td></tr><tr><td>4</td><td>EC_BTN_35</td></tr><tr><td>5</td><td>EC_BTN_36</td></tr><tr><td>6</td><td>GND</td></tr></table>

Table 3-20: Volume & Backlight Control Connector Pin Definition

# 3.2.15 Key Connector (Optional)

The key connector supports 32 physical keys and 5 control keys with the following default values:

 Directions: ↑, ↓, ←, →
 Numbers: 0 to 9
 Functions: Enter, ESC, TAB, Backspace, Delete, Clear, PagUp, PagDn
 Hot keys: F1 - F10

![39\n40\n1\n2](.sp-titan2-50m-p5300-1010-11-240912/71a5ee647d278c86f5a405e06047a72ee4ff13d7a12d9f9ac3789ed95487b764.jpg)

Figure 3-22: Key Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Function Value</td><td>Key Code</td><td>Pin</td><td>Signal</td><td>Function Value</td><td>Key Code</td></tr><tr><td>1</td><td>GND</td><td>N/A</td><td>N/A</td><td>2</td><td>P_+3V3_S0</td><td>N/A</td><td>N/A</td></tr><tr><td>3</td><td>EC_BTN_17</td><td>^</td><td>48h</td><td>4</td><td>EC_BTN_1</td><td>Tab</td><td>0Fh</td></tr><tr><td>5</td><td>EC_BTN_18</td><td>V</td><td>50h</td><td>6</td><td>EC_BTN_2</td><td>Backspace</td><td>0Eh</td></tr><tr><td>7</td><td>EC_BTN_19</td><td>&gt;</td><td>4Dh</td><td>8</td><td>EC_BTN_3</td><td>Delete</td><td>53h</td></tr><tr><td>9</td><td>EC_BTN_20</td><td>&lt;</td><td>4Bh</td><td>10</td><td>EC_BTN_4</td><td>Space</td><td>39h</td></tr><tr><td>11</td><td>EC_BTN_21</td><td>0</td><td>0Bh</td><td>12</td><td>EC_BTN_5</td><td>Page up</td><td>49h</td></tr><tr><td>13</td><td>EC_BTN_22</td><td>1</td><td>02h</td><td>14</td><td>EC_BTN_6</td><td>Page down</td><td>51h</td></tr><tr><td>15</td><td>EC_BTN_23</td><td>2</td><td>03h</td><td>16</td><td>EC_BTN_7</td><td>F1</td><td>3Bh</td></tr><tr><td>17</td><td>EC_BTN_24</td><td>3</td><td>04h</td><td>18</td><td>EC_BTN_8</td><td>F2</td><td>3Ch</td></tr><tr><td>19</td><td>EC_BTN_25</td><td>4</td><td>5Ch</td><td>20</td><td>EC_BTN_9</td><td>F3</td><td>3Dh</td></tr><tr><td>21</td><td>EC_BTN_26</td><td>5</td><td>06h</td><td>22</td><td>EC_BTN_10</td><td>F4</td><td>3Eh</td></tr><tr><td>23</td><td>EC_BTN_27</td><td>6</td><td>07h</td><td>24</td><td>EC_BTN_11</td><td>F5</td><td>3Fh</td></tr><tr><td>25</td><td>EC_BTN_28</td><td>7</td><td>08h</td><td>26</td><td>EC_BTN_12</td><td>F6</td><td>40h</td></tr><tr><td>27</td><td>EC_BTN_29</td><td>8</td><td>09h</td><td>28</td><td>EC_BTN_13</td><td>F7</td><td>41h</td></tr><tr><td>29</td><td>EC_BTN_30</td><td>9</td><td>0Ah</td><td>30</td><td>EC_BTN_14</td><td>F8</td><td>42h</td></tr><tr><td>31</td><td>EC_BTN_31</td><td>Enter</td><td>1Ch</td><td>32</td><td>EC_BTN_15</td><td>F9</td><td>43h</td></tr><tr><td>33</td><td>EC_BTN_32</td><td>ESC</td><td>01h</td><td>34</td><td>EC_BTN_16</td><td>F10</td><td>44h</td></tr><tr><td>35</td><td>EC_BTN_37</td><td>Power</td><td>N/A</td><td>36</td><td colspan="3">N/C</td></tr><tr><td>37</td><td colspan="2">N/C</td><td>N/A</td><td>38</td><td>P_+3V3_A</td><td>N/A</td><td>N/A</td></tr><tr><td>39</td><td colspan="2">N/C</td><td>N/A</td><td>40</td><td>P_+3V3_A</td><td>N/A</td><td>N/A</td></tr><tr><td>G1</td><td>GND</td><td>N/A</td><td>N/A</td><td>G2</td><td>GND</td><td>N/A</td><td>N/A</td></tr></table>

Table 3-21: Key Connector Pin Definition

# 3.2.16 Fan Connectors

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/b4131b9f32e9760e41330aebf7d88543ef301e816b70e7a60a66e9e7c4b0383d.jpg)

Figure 3-23: Fan Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>FAN_PWR_IN (12V)</td></tr><tr><td>3</td><td>BMC_FAN0_IN</td></tr><tr><td>4</td><td>BMC_FAN0_OUT</td></tr></table>

Table 3-22: Fan Connector Pin Definition

# 3.2.17 Clear CMOS Jumper (JP1501)

Under conditions in which the SP2-TGL fails to boot, clearing the BIOS content stored in CMOS and restoring the default settings may be effective. To clear CMOS (JP1501), short Pin 2 and Pin 3 and wait for 5 seconds. Remove the jumper cap and short Pin 1 and Pin 2.

![The image displays a black and white graphic. At the top is a horizontal rectangle containing three smaller squares arranged side-by-side. Inside each of the three squares is a smaller square. Below this shape is the number '1', followed by a horizontal line.](.sp-titan2-50m-p5300-1010-11-240912/f45b7d45783ad5e0b290287bfbcca76197fb2b739c636bf1430a1d41f3c57677.jpg)
Figure 3-24: Clear CMOS Jumper (JP1501) Pin Definition

<table><tr><td colspan="2">Clear CMOS</td></tr><tr><td>2-3</td><td>Clear CMOS</td></tr><tr><td>1-2</td><td>N/A (default)</td></tr></table>

Table 3-23: Clear CMOS Jumper (JP1501)

# 3.2.18 PCIe Gen4 x4 Connectors (Optional)

![Pure electrical circuit lines without any symbols](.sp-titan2-50m-p5300-1010-11-240912/3e5d93ae35d4fc55055031ae58930f60503479c5656b38a086945f464c5dd547.jpg)

Figure 3-25: PCIe Gen4 x4 Connector Pin Definition

<table><tr><td rowspan="2">Pin</td><td colspan="2">Side B Connector</td><td colspan="2">Side A Connector</td></tr><tr><td>Name</td><td>Description</td><td>Name</td><td>Description</td></tr><tr><td>1</td><td>+12V</td><td>+12 volt power</td><td>PRSNT#1</td><td>Hot plug presence detect</td></tr><tr><td>2</td><td>+12V</td><td>+12 volt power</td><td>+12V</td><td>+12 volt power</td></tr><tr><td>3</td><td>+12V</td><td>+12 volt power</td><td>+12V</td><td>+12 volt power</td></tr><tr><td>4</td><td>GND</td><td>Ground</td><td>GND</td><td>Ground</td></tr><tr><td>5</td><td>SMCLK</td><td>SMBus clock</td><td>JTAG2</td><td>TCK</td></tr></table>

<table><tr><td rowspan="2">Pin</td><td colspan="2">Side B Connector</td><td colspan="2">Side A Connector</td></tr><tr><td>Name</td><td>Description</td><td>Name</td><td>Description</td></tr><tr><td>6</td><td>SMDAT</td><td>SMBus data</td><td>JTAG3</td><td>TDI</td></tr><tr><td>7</td><td>GND</td><td>Ground</td><td>JTAG4</td><td>TDO</td></tr><tr><td>8</td><td>+12V</td><td>+12V power</td><td>JTAG5</td><td>TMS</td></tr><tr><td>9</td><td>JTAG1</td><td>+TRST#</td><td>+3.3V</td><td>+3.3 volt power</td></tr><tr><td>10</td><td>3.3Vaux</td><td>3.3 volt power</td><td>+3.3V</td><td>+3.3 volt power</td></tr><tr><td>11</td><td>WAKE#</td><td>Link Reactivation</td><td>PERST#</td><td>Reset</td></tr><tr><td colspan="5">Mechanical Key</td></tr><tr><td>12</td><td>RSVD</td><td>Reserved</td><td>GND</td><td>Ground</td></tr><tr><td>13</td><td>GND</td><td>Ground</td><td>REFCLK+</td><td>Reference Clock</td></tr><tr><td>14</td><td>HSOp(0)</td><td>Transmitter Lane 0,</td><td>REFCLK-</td><td>Differential pair</td></tr><tr><td>15</td><td>HSOn(0)</td><td>Differential pair</td><td>GND</td><td>Ground</td></tr><tr><td>16</td><td>GND</td><td>Ground</td><td>HSIp(0)</td><td>Receiver Lane 0,</td></tr><tr><td>17</td><td>PRSNT#2</td><td>Hotplug detect</td><td>HSIn(0)</td><td>Differential pair</td></tr><tr><td>18</td><td>GND</td><td>Ground</td><td>GND</td><td>Ground</td></tr><tr><td>19</td><td>HSOp(1)</td><td>Transmitter Lane 1,</td><td>RSVD</td><td>Reserved</td></tr><tr><td>20</td><td>HSOn(1)</td><td>Differential pair</td><td>GND</td><td>Ground</td></tr><tr><td>21</td><td>GND</td><td>Ground</td><td>HSIp(1)</td><td>Receiver Lane 1,</td></tr><tr><td>22</td><td>GND</td><td>Ground</td><td>HSIn(1)</td><td>Differential pair</td></tr><tr><td>23</td><td>HSOp(2)</td><td>Transmitter Lane 2,</td><td>GND</td><td>Ground</td></tr><tr><td>24</td><td>HSOn(2)</td><td>Differential pair</td><td>GND</td><td>Ground</td></tr><tr><td>25</td><td>GND</td><td>Ground</td><td>HSIp(2)</td><td>Receiver Lane 2,</td></tr><tr><td>26</td><td>GND</td><td>Ground</td><td>HSIn(2)</td><td>Differential pair</td></tr><tr><td>27</td><td>HSOp(3)</td><td>Transmitter Lane 3,</td><td>GND</td><td>Ground</td></tr><tr><td>28</td><td>HSOn(0)</td><td>Differential pair</td><td>GND</td><td>Ground</td></tr><tr><td>29</td><td>GND</td><td>Ground</td><td>HSIp(3)</td><td>Receiver Lane 3,</td></tr><tr><td>30</td><td>RSVD</td><td>Reserved</td><td>HSIn(3)</td><td>Differential pair</td></tr><tr><td>31</td><td>PRSNT#2</td><td>Hot plug detect</td><td>GND</td><td>Ground</td></tr><tr><td>32</td><td>GND</td><td>Ground</td><td>RSVD</td><td>Reserved</td></tr></table>

Table 3-24: PCIe Gen4 x4 Connector Pin Definition

# 3.2.19 COM2 Connector

![Pure electrical connector pinout diagram without any text or symbols](.sp-titan2-50m-p5300-1010-11-240912/49962fae57092bffcf08f9be9831ca66b2fc64b8de4abf01b6b19cc4082a6f8d.jpg)

Figure 3-26: COM2 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>COM2_DCD-L_CN</td></tr><tr><td>2</td><td>COM2_RXD_CN</td></tr><tr><td>3</td><td>COM2_TXD_CN</td></tr><tr><td>4</td><td>COM2_DTR-L_CN</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>COM2_DSR-L_CN</td></tr><tr><td>7</td><td>COM2_RTS-L_CN</td></tr><tr><td>8</td><td>COM2_CTS-L_CN</td></tr><tr><td>9</td><td>COM2_RI-L_CN</td></tr><tr><td>10</td><td>NC</td></tr></table>

Table 3-25: COM2 Connector Pin Definition

# 3.2.20 LED Connector

The LED connector supports up to 10 LEDs.

![Pure electrical component diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/11dda01bd52470e74154521bd57116d7d4f144ebf4899e63506c826ee368b6ce.jpg)

Figure 3-27: LED Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>CN_STDBY_PWR</td></tr><tr><td>3</td><td>CN_GP3_LED-L</td></tr><tr><td>4</td><td>CN_GP2_LED-L</td></tr><tr><td>5</td><td>CN_GP1_LED-L</td></tr><tr><td>6</td><td>P_+3V3_A</td></tr><tr><td>7</td><td>CN_COM2_SOUT_LED_L</td></tr><tr><td>8</td><td>CN_COM2_SIN_LED_L</td></tr><tr><td>9</td><td>CN_COM1_SOUT_LED_L</td></tr><tr><td>10</td><td>CN_COM1_SIN_LED_L</td></tr><tr><td>11</td><td>CN_SATA_LED-L_R</td></tr><tr><td>12</td><td>P_+3V3_S0</td></tr><tr><td>13</td><td>CN_WDT_LED-L</td></tr><tr><td>14</td><td>P_+3V3_A</td></tr><tr><td>15</td><td>GND</td></tr><tr><td>16</td><td>GND</td></tr></table>

Table 3-26: LED Connector Pin Definition

<table><tr><td>Pin</td><td>Function</td><td>Color</td><td>Remarks</td></tr><tr><td>10</td><td>COM Tx for COM 1</td><td>LED blinks when COM data is transferring</td><td>HW control</td></tr><tr><td>9</td><td>COM Rx for COM 1</td><td>LED blinks when COM data is transferring</td><td>HW control</td></tr><tr><td>8</td><td>COM Tx for COM 2</td><td>LED blinks when COM data is transferring</td><td>HW control</td></tr><tr><td>7</td><td>COM Rx for COM 2</td><td>LED blinks when COM data is transferring</td><td>HW control</td></tr><tr><td>13</td><td>Watch Dog LED</td><td>One Red color LED onboard</td><td>BMC control</td></tr><tr><td>11</td><td>SATA LED</td><td>One Red color LED onboard</td><td>SOC control</td></tr><tr><td>2</td><td>Standby Power</td><td>ON when system is on standby</td><td>HW control</td></tr><tr><td>5</td><td>User defined</td><td></td><td>SOC control</td></tr><tr><td>4</td><td>User defined</td><td></td><td>SOC control</td></tr><tr><td>3</td><td>User defined</td><td></td><td>SOC control</td></tr></table>

Table 3-27: LED Connector Pin Functions

# 3.2.21 I2C Connector 1 & 2

![The image displays a black and white line drawing of a rectangular component, resembling an integrated circuit. Inside the rectangle are two horizontal rows of eight small squares each. Vertical rectangular shapes are positioned at the far left and right edges. Extending downwards from the bottom edge are eight small rectangular pins. Below the diagram is the number 1.](.sp-titan2-50m-p5300-1010-11-240912/39159fa3ee0ed65d212f4cc36fb514701449512a924c4a8f828eeebff926137e.jpg)

Figure 3-28: I2C Connector 1 & 2 Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_I2C</td></tr><tr><td>2</td><td>P_+3V3_I2C</td></tr><tr><td>3</td><td>DIO_I2C4_SDA</td></tr><tr><td>4</td><td>DIO_I2C4_SCL</td></tr><tr><td>5</td><td>DIO_I2C1_INT</td></tr><tr><td>6</td><td>GND</td></tr></table>

Table 3-28: I2C Connector 1 & 2 Pin Definition

# 3.2.22 RTC Battery Wafer

![The image displays a black-and-white technical line drawing. On the left side, there is a small right-pointing triangle, the number '1', and two small rectangular blocks stacked vertically. On the right side, a larger assembly is depicted in cross-section, featuring various rectangular shapes and lines that suggest an internal mechanical or electronic component.](.sp-titan2-50m-p5300-1010-11-240912/63fb0abba8fc4f7691ef7b68c02bea21c9dfaaaa42bc642a9e11c37500e3dc15.jpg)

Figure 3-29: RTC Battery Wafer Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+VCC_RTC_CN_A</td></tr><tr><td>2</td><td>GND</td></tr></table>

Table 3-29: RTC Battery Wafer Pin Definition

# 3.2.23 DB40 Connector

This connector is particular useful during carrier design and bring up phase. It offers access to the following critical parts of the module:

 Test points measurement of internal power rails
 I2C bus for BIOS POST code readout
 SPI BIOS programming interface
 Embedded Controller programming interface

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/4b2d94efdafbef27a9c5e970aa6ff91fe1335c4b19414296de60cc40f912f6d4.jpg)

Figure 3-30: DB40 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>RESVD</td></tr><tr><td>2</td><td>SMC_STATUS</td></tr><tr><td>3</td><td>BIOS_MODE</td></tr><tr><td>4</td><td>SEL_BIOS</td></tr><tr><td>5</td><td>POSTWDT_DIS#</td></tr><tr><td>6</td><td>SUS_S5#</td></tr><tr><td>7</td><td>SUS_S4#</td></tr><tr><td>8</td><td>SUS_S3#</td></tr><tr><td>9</td><td>CB_PWROK</td></tr><tr><td>10</td><td>CB_RESET#</td></tr><tr><td>11</td><td>SYS_RESET#</td></tr><tr><td>12</td><td>PWRBTN#</td></tr><tr><td>13</td><td>OCD0B</td></tr><tr><td>14</td><td>OCD0A</td></tr><tr><td>15</td><td>CLK</td></tr><tr><td>16</td><td>DATA</td></tr><tr><td>17</td><td>RESET_IN#</td></tr><tr><td>18</td><td>FUMD0</td></tr><tr><td>19</td><td>RXD6</td></tr><tr><td>20</td><td>TXD6</td></tr><tr><td>21</td><td>GND</td></tr><tr><td>22</td><td>3.3V_A</td></tr><tr><td>23</td><td>3.3V_SMC</td></tr><tr><td>24</td><td>LPC_AD0</td></tr><tr><td>25</td><td>LPC_AD1</td></tr><tr><td>26</td><td>LPC_AD2</td></tr><tr><td>27</td><td>LPC_AD3</td></tr><tr><td>28</td><td>LPC_FRAME#</td></tr><tr><td>29</td><td>CLK33_LPC</td></tr><tr><td>30</td><td>RST#</td></tr><tr><td>31</td><td>BIOS_DIS0</td></tr><tr><td>32</td><td>GND</td></tr><tr><td>33</td><td>3V3_LPC</td></tr><tr><td>34</td><td>SPI_BIOS_CLK</td></tr><tr><td>35</td><td>SPI_BIOS_MOSI</td></tr><tr><td>36</td><td>SPI_BIOS_MISO</td></tr><tr><td>37</td><td>SPI_BIOS_CS1#</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>38</td><td>SPI_BIOS_CS0#</td></tr><tr><td>39</td><td>GND</td></tr><tr><td>40</td><td>VCC_SPI_IN</td></tr></table>

Table 3-30: DB40 Connector Pin Definition

# 3.2.24 GPIO Connector

SP2-TGL provides 4 channels of non-isolation digital input and 4 channels of non-isolation digital output circuits.

# 4-channel Digital Input

 VIH: 2.9 to 3.3V
 VIL: 0 to 0.15V

# 4-channel Digital Output

 Output type: open drain N-channel
 MOSFET driver with internal pull-high of 200Ω resistance
 Source/Sink current for all channels: 22mA
 VOH: 2.21 to 3.3V
 VOL: 0 to 0.55V

![Pure electrical component diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/7516660abc5de3d0d35abec919991d77d17c93f0583e421ed1c296db77e62749.jpg)

Figure 3-31: GPIO Connector Pin Definition

<table><tr><td>Pin</td><td>Signal Name</td></tr><tr><td>1</td><td>P_+3V3_S0</td></tr><tr><td>2</td><td>WFR_GPIO_1_R</td></tr><tr><td>3</td><td>WFR_GPIO_2_R</td></tr><tr><td>4</td><td>WFR_GPIO_3_R</td></tr><tr><td>5</td><td>WFR_GPIO_4_R</td></tr><tr><td>6</td><td>WFR_GPIO_5_R</td></tr><tr><td>7</td><td>WFR_GPIO_6_R</td></tr><tr><td>8</td><td>WFR_GPIO_7_R</td></tr><tr><td>9</td><td>WFR_GPIO_8_R</td></tr><tr><td>10</td><td>GND</td></tr></table>

Table 3-31: GPIO Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>PCH GPIO</td><td>Default Value</td><td>Input/Output Voltage Range</td></tr><tr><td>1</td><td>P_+3V3_S0</td><td></td><td></td><td></td></tr><tr><td>2</td><td>GPIO_1</td><td>GPP_B3</td><td>Output High</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>3</td><td>GPIO_2</td><td>GPP_B4</td><td>Output Low</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>4</td><td>GPIO_3</td><td>GPP_E3</td><td>Output High</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>5</td><td>GPIO_4</td><td>GPP_E7</td><td>Output Low</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>6</td><td>GPIO_5</td><td>GPP_A14</td><td>Output High</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>7</td><td>GPIO_6</td><td>GPP_A15</td><td>Output Low</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>8</td><td>GPIO_7</td><td>GPP_A21</td><td>Output High</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>9</td><td>GPIO_8</td><td>GPP_A22</td><td>Output Low</td><td>VIH: 2.9VVIL: 0.15VVOH: 2.211VVOL: 0.55V</td></tr><tr><td>10</td><td>GND</td><td></td><td></td><td></td></tr></table>

# Table 3-32: GPIO Connector Pin Voltage

# 3.2.25 Nano SIM Card Connector

The Nano SIM connector provides 4G/5G communication functionality.

![Pure technical line drawing of a mechanical or electrical component layout without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/a36d409d2372fea19b10e1dc51512b9637aa50c0ec78e956f52929c53a5b12b1.jpg)

Figure 3-32: Nano SIM Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>C1</td><td>P_+3V3_UIM_M2</td></tr><tr><td>C2</td><td>M2_UIM_RST</td></tr><tr><td>C3</td><td>M2_UIM_CLK_R</td></tr><tr><td>CD</td><td>M2_UIM1_CD</td></tr><tr><td>C5</td><td>GND</td></tr><tr><td>C6</td><td>M2_UIM_VPP</td></tr><tr><td>C7</td><td>M2_UIM_DATA</td></tr><tr><td>G1</td><td>GND</td></tr><tr><td>G2</td><td>GND</td></tr><tr><td>G3</td><td>GND</td></tr><tr><td>G4</td><td>GND</td></tr></table>

Table 3-33: Nano SIM Connector Pin Definition

# 3.2.26 Backup Battery Connector (Optional)

An optional backup battery connector is available. Contact ADLINK to for more information.

![Pure electrical connector diagram without any text, numbers, or symbols](.sp-titan2-50m-p5300-1010-11-240912/e7d937d85b09fd04f6ceba5cb41ee4543cb1497d75169f1605a7aad5ec32019b.jpg)

Figure 3-33: Backup Battery Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CHG_PWR</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>CHG_SMBCLK</td></tr><tr><td>4</td><td>CHG_SMBDAT</td></tr><tr><td>5</td><td>SMB_ALERT-L_R</td></tr></table>

Table 3-34: Backup Battery Connector Pin Definition

# 3.2.27 M.2 2280 SATA SSD Connector

The M.2 B+M key supports a SATA SSD.

![2\n74\n1\n75](.sp-titan2-50m-p5300-1010-11-240912/7f98b37c189c805924d9b40de95db97cafdf833e9ada0053aade6983319e7229.jpg)

Figure 3-34: M.2 2280 Connector Pin Definition

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>P_+3V3_S0</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>P_+3V3_S0</td></tr><tr><td>5</td><td>NC</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>NC</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>P_+3V3_S0</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>P_+3V3_S0</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>P_+3V3_S0</td></tr><tr><td>17</td><td>NC</td><td>18</td><td>P_+3V3_S0</td></tr><tr><td>19</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>NC</td><td>22</td><td>NC</td></tr><tr><td>23</td><td>NC</td><td>24</td><td>NC</td></tr><tr><td>25</td><td>NC</td><td>26</td><td>NC</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>NC</td><td>30</td><td>NC</td></tr><tr><td>31</td><td>NC</td><td>32</td><td>NC</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>NC</td></tr><tr><td>35</td><td>NC</td><td>36</td><td>NC</td></tr><tr><td>37</td><td>NC</td><td>38</td><td>PCH_DEVSLP0</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>NC</td></tr><tr><td>41</td><td>SATA_RX0_P</td><td>42</td><td>NC</td></tr><tr><td>43</td><td>SATA_RX0_N</td><td>44</td><td>NC</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td></tr><tr><td>47</td><td>SATA_TX0_N</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>SATA_TX0_P</td><td>50</td><td>NC</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>NC</td></tr><tr><td>53</td><td>NC</td><td>54</td><td>NC</td></tr><tr><td>55</td><td>NC</td><td>56</td><td>NC</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>NC</td></tr><tr><td>67</td><td>NC</td><td>68</td><td>NC</td></tr><tr><td>69</td><td>NC</td><td>70</td><td>P_+3V3_S0</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>P_+3V3_S0</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>P_+3V3_S0</td></tr><tr><td>75</td><td>NC</td><td>-</td><td>-</td></tr><tr><td>G1</td><td>GND</td><td>G2</td><td>GND</td></tr><tr><td>N1</td><td>NC</td><td>N2</td><td>NC</td></tr></table>

Table 3-35: M.2 2280 Connector Pin Definition

# 4 BIOS Setup

BIOS can be configured via the BIOS Setup Utility that is invoked during BIOS boot phase. The BIOS configuration is kept in NVRAM which is the same hardware part where the BIOS is stored. All settings will remain after the system is powered down.

![This image displays an icon representing a document or checklist. It features a white rectangular sheet with the top-right corner folded down. Faint gray horizontal lines are visible across the page, suggesting text or a form. A large, bold red checkmark is superimposed over the center of the document, extending from the bottom left to the top right.](.sp-titan2-50m-p5300-1010-11-240912/6bfb700357c414ba106c1bc6ac2d28cfea4df101fa1a664c3cf49d458918cbdc.jpg)
NOTE:

BIOS options used in this manual are for reference only, and are subject to change. Users can download the latest BIOS version from the ADLINK website.

![The image displays a red equilateral triangle with rounded corners centered on a white background. Inside the triangle is a white exclamation mark. A black horizontal bar is visible along the very top edge of the image.](.sp-titan2-50m-p5300-1010-11-240912/ebc8cc485729e0b0c5cd33de4ff2631f23e2883893fbc5080f41147484d347e5.jpg)
WARNING:

Changing BIOS settings may lead to unexpected system behavior and the possible inability to boot.

# 4.1 BIOS Setup Menu

The BIOS Setup Utility is invoked by pressing &lt;ESC&gt; or &lt;DEL&gt; when the system boots. A system reboot is required when changes are made in the BIOS Setup Utility.

The BIOS Setup Utility includes the following hotkeys.

 &lt;F1&gt;: General help
 &lt;F8&gt;: Load previous BIOS values
 &lt;F9&gt;: Load BIOS default values
 &lt;F10&gt;: Save & Exit the Setup Utility

# Menu Selection Bar

The Menu Selection Bar is located at the top of the screen. It displays the top level menus available to the user.

 Main Menu
 Advanced Menu
 Chipset Menu
 Security Menu
 Boot Menu
 Save & Exit Menu

# Menu Conventions

The appearance of the setup menus and items listed in this chapter are based on a VT100 terminal connection via serial console with the following menu conventions.

 Using color

The default BIOS setup fields are black. The BIOS setup fields currently not used are grey. The display strings are black.

 Using brackets

Editable menu options are marketed with square brackets, ‘[‘ and ‘]’.

# 4.2 Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following tables as a quick reference for the contents of the BIOS Setup Utility. The remainder of this chapter describe the submenus and options for each menu item. The default settings are presented in bold, and the function of each setting is described in the right hand column of the table.

<table><tr><td>Main</td><td>Advanced</td></tr><tr><td>- BIOS Information- System Information- Board Information</td><td>- CPU Configuration ▶- Graphics Configuration ▶- Power Management ▶- System Management ▶- Thermal Management ▶- Watchdog Timer ▶- Super IO Configuration ▶- Serial Console Redirection ▶- Network Stack Configuration ▶- Trusted Computing ▶- Engineering Mode Configuration ▶- USB Configuration ▶</td></tr></table>

<table><tr><td>Chipset</td><td>Security</td></tr><tr><td>- System Agent (SA) Configuration ▶- PCH-IO Configuration ▶Boot</td><td>- Secure Boot menuSave &amp; Exit</td></tr><tr><td>- Boot Configuration- UEFI Hard Disk Drive BBS Priorities- UEFI NVME Drive BBS Priorities- UEFI CDROM/DVD Drive BBS Priorities- UEFI SD Drive BBS Priorities- UEFI USB Hard Disk Drive BBS Priorities- UEFI USB CDROM/DVD Drive BBS Priorities- UEFI USB Key Drive BBS Priorities- UEFI USB Floppy Drive BBS Priorities- UEFI USB Lan Drive BBS Priorities- UEFI NETWORK Drive BBS Priorities</td><td>- Save Changes and Exit- Discard Changes and Exit- Save Changes and Reset- Discard Changes and Reset- Save Options- Save Changes- Discard Changes- Restore Defaults- Save as User Defaults- Restore User Defaults- Boot Override- Launch EFI Shell from filesystem device</td></tr></table>

![The image features a white document icon with horizontal gray lines and a folded top-right corner. A large red checkmark is superimposed over the document.](.sp-titan2-50m-p5300-1010-11-240912/325b33f73b58aa77129e016264a1456bd5fc406514bccc18136f20431685ac0b.jpg)
NOTE:

- ► indicates a submenu
- Gray text indicates info only
- Bold text indicates a default setting

# 4.3 Main Menu

This menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below for details of the submenus and settings.

# 4.3.1 Main > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>BIOS Vendor</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>BIOS Version.</td></tr><tr><td>Build Date</td><td>Info only</td><td>BIOS build date</td></tr><tr><td>MRC Version</td><td>Info only</td><td>MRC Version</td></tr><tr><td>GOP Version</td><td>Info only</td><td>GOP Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>ME FW Version</td></tr><tr><td>EC Version</td><td>Info only</td><td>EC FW Version</td></tr></table>

# 4.3.2 Main > System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Project Name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>CPU Board Version</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>CPU Brand String</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>CPU Frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Total Memory</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Memory Frequency</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>PCH SKU</td></tr><tr><td>FM Board</td><td>Info only</td><td>FM Board</td></tr></table>

# 4.3.3 Main > Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Number</td><td>Info only</td><td>Serial Number</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Manufacturing Date</td></tr><tr><td>Last Repair Date</td><td>Info only</td><td>Last Repair Date</td></tr><tr><td>Runtime Statistics</td><td>Info only</td><td>Runtime Statistics</td></tr><tr><td>Total Runtime</td><td>Info only</td><td>Total Runtime</td></tr><tr><td>Current Runtime</td><td>Info only</td><td>Current Runtime</td></tr><tr><td>Power Cycles</td><td>Info only</td><td>Power Cycles</td></tr><tr><td>Boot Cycles</td><td>Info only</td><td>Boot Cycles</td></tr><tr><td>Boot Reason</td><td>Info only</td><td>Boot Reason</td></tr></table>

# 4.4 Advanced Menu

This menu contains the settings for most of the user interfaces in the system.

4.4.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info only</td><td>Displays the Processor Type</td></tr><tr><td>ID</td><td>Info only</td><td>Displays the Processor ID</td></tr><tr><td>Package</td><td>Info only</td><td>Displays the Processor Package</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>CPU Microcode Revision</td></tr><tr><td>Speed</td><td>Info only</td><td>Displays the Processor Speed.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Displays the Processor L1 Data Cache size.</td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td>Displays the Processor L1 Instruction Cache size.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Displays the Processor L2 Cache size.</td></tr><tr><td>L3 Cache</td><td>Info only</td><td>Displays the Processor L3 Cache size.</td></tr><tr><td>L4 Cache</td><td>Info only</td><td>Displays the Processor L4 eDRAM size.</td></tr><tr><td>VMX</td><td>Info only</td><td>VMX Supported or Not</td></tr><tr><td>SMX/TXT</td><td>Info only</td><td>SMX/TXT Supported or Not</td></tr><tr><td>Intel(R)SpeedStep(tm)</td><td>DisabledEnabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Enables/Disables processor Turbo Mode (requires EMTTM enabled).AUTO means enabled.</td></tr><tr><td>C states</td><td>DisabledEnabled</td><td>Enables/Disables CPU Power Management. Allows CPU to go to C states when not 100% utilized.</td></tr><tr><td>Enhanced C-states</td><td>DisabledEnabled</td><td>Enables/Disables C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State.</td></tr><tr><td>C-State Auto Demotion</td><td>DisabledC1</td><td>Configure C-State Auto Demotion</td></tr><tr><td>C-State Un-demotion</td><td>DisabledC1</td><td>Configure C-State Un-demotion</td></tr><tr><td>Package C-State Demotion</td><td>DisabledEnabled</td><td>Package C-State Demotion</td></tr><tr><td>Package C-State \ Un-demotion</td><td>DisabledEnabled</td><td>Package C-State Un-demotion</td></tr><tr><td>DTS SMM</td><td>DisabledEnabledCritical TempReporting (Out Of spec.)</td><td>Disabled: ACPI thermal management uses EC reported temperature values.</td></tr></table>

4.4.2 Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>LVDS</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enables/Disables eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>Auto640x480800x6001024x7681280x1024LVDS11400x1050LVDS21600x12001366x7681680x10501920x12001440x9001600x9001280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>FM Board DDI port</td><td>No DeviceDisplayPortHDMIDisplayPort with HDMI/DVI Compatible</td><td>DDI port 1 functions as DisplayPort or HDMI</td></tr><tr><td>Data format and Color Depth</td><td>AutoVESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>AutoDual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>LVDS Backlight Brightness</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0xFF, 0x00, 0x01]</td><td>A change takes effect immediately.</td></tr></table>

# 4.4.3 Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>DisabledEnabled</td><td>Enables/Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables/Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disabled S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>PCI Wake</td><td>DisabledEnabled</td><td>Enables/Disables PCIe wake function</td></tr><tr><td>RI Wake</td><td>DisabledEnabled</td><td>Enables/Disables RI wake Function.</td></tr><tr><td>RTC Wake system from S5</td><td>DisabledFixed TimeDynamic Time</td><td>Enables/Disables System wake on alarm event.Select FixedTime, system will wake on the hr::min::sec specified.Select DynamicTime,System will wake on the current time + Increase minute(s)</td></tr><tr><td>Wake up hour</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0x17, 0x00, 0x01]</td><td>Range: 0-23 hr</td></tr><tr><td>Wake up minute</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0x3B, 0x00, 0x01]</td><td>Range: 0-59 min</td></tr><tr><td>Wake up second</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0x3B, 0x00, 0x01]</td><td>Range: 0-59 sec</td></tr><tr><td>Wake up minute increase</td><td>[ Max-Value, Min-Value, Step-Value] = [ 0x05, 0x01, 0x01]</td><td>Range: 1-5 min</td></tr><tr><td>Emulation AT/ATX</td><td>Emulation ATATX</td><td>Select Emulation AT or ATX function. If this option is set to [Emulation AT], BIOS will report no suspend functions to ACPI OS. On Windows XP, the OS will show a shutdown message during system shutdown.</td></tr></table>

# 4.4.4 Advanced > Power Management > Power Consumption

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power Consumption</td><td>Info only</td><td></td></tr><tr><td>Current Input Current</td><td>Info only</td><td>Current Input Current</td></tr><tr><td>Current Input Power</td><td>Info only</td><td>Current Input Power</td></tr><tr><td>VIN</td><td>Info only</td><td>VIN</td></tr><tr><td>5VSBY</td><td>Info only</td><td>5VSBY</td></tr><tr><td>RTC</td><td>Info only</td><td>RTC</td></tr><tr><td>AIN3</td><td>NA</td><td>AIN3</td></tr><tr><td>AIN4</td><td>NA</td><td>AIN4</td></tr><tr><td>AIN5</td><td>NA</td><td>AIN5</td></tr><tr><td>AIN6</td><td>NA</td><td>AIN6</td></tr><tr><td>AIN7</td><td>NA</td><td>AIN7</td></tr><tr><td>AIN8</td><td>NA</td><td>AIN8</td></tr><tr><td>AIN9</td><td>NA</td><td>AIN9</td></tr><tr><td>AIN10</td><td>NA</td><td>AIN10</td></tr><tr><td>AIN11</td><td>NA</td><td>AIN11</td></tr><tr><td>AIN12</td><td>NA</td><td>AIN12</td></tr><tr><td>AIN13</td><td>NA</td><td>AIN13</td></tr><tr><td>AIN14</td><td>NA</td><td>AIN14</td></tr><tr><td>AIN15</td><td>NA</td><td>AIN15</td></tr></table>

# 4.4.5 Advanced > System Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>EC Version</td><td>Info only</td><td>Version of EC Firmware</td></tr><tr><td>SEMA Firmware</td><td>Info only</td><td>Version of SEMA Firmware</td></tr><tr><td>Build Date</td><td>Info only</td><td>Build Date of SEMA Firmware</td></tr><tr><td>SEMA Bootloader</td><td>Info only</td><td>Version of SEMA Bootloader</td></tr><tr><td>Build Date</td><td>Info only</td><td>Build Date of SEMA Bootloader</td></tr></table>

# 4.4.6 Advanced > System Management > SEMA Features

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SEMA Features</td><td>Info only</td><td></td></tr><tr><td>Uptime &amp; Power Cycles Counter</td><td>Info only</td><td>Uptime &amp; Power Cycles Counter</td></tr><tr><td>System Restart Event</td><td>Info only</td><td>System Restart Event</td></tr><tr><td>1024 Bytes User-Flash</td><td>Info only</td><td>1024 Bytes User-Flash</td></tr><tr><td>Watchdog</td><td>Info only</td><td>Watchdog</td></tr><tr><td>Temperatures</td><td>Info only</td><td>Temperatures</td></tr><tr><td>Voltage Monitor</td><td>Info only</td><td>Voltage Monitor</td></tr><tr><td>Power-Up Watchdog</td><td>Info only</td><td>Power-Up Watchdog</td></tr><tr><td>Power Monitor (current sense)</td><td>Info only</td><td>Power Monitor (current sense)</td></tr><tr><td>System Fan 1</td><td>Info only</td><td>System Fan 1</td></tr><tr><td>ACPI Thermal Trigger</td><td>Info only</td><td>ACPI Thermal Trigger</td></tr><tr><td>DTS register available</td><td>Info only</td><td>DTS register available</td></tr><tr><td>TIVA BMC</td><td>Info only</td><td>TIVA BMC</td></tr><tr><td>SEMA Error Log</td><td>Info only</td><td>SEMA Error Log</td></tr></table>

# 4.4.7 Advanced > System Management > Flags

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BMC Flags</td><td>Info only</td><td>BMC Flags</td></tr><tr><td>BIOS Select</td><td>Info only</td><td>BIOS Select</td></tr><tr><td>ATX/AT-Mode</td><td>Info only</td><td>ATX/AT-Mode</td></tr><tr><td>Exception Code</td><td>Info only</td><td>Exception Code</td></tr></table>

# 4.4.8 Advanced > System Management $> \mathbb { S } E M A > { \mathsf { T e m } } -$ perature

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CPU Temperature ▶</td><td>Sub-Menu</td><td></td></tr><tr><td>Current</td><td>Info only</td><td>Current CPU temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Startup CPU temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Min. CPU temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Max. CPU temperature</td></tr><tr><td>Board Temperatures ▶</td><td>Sub-Menu</td><td></td></tr><tr><td>Current</td><td>Info only</td><td>Current Board temperature</td></tr><tr><td>Startup</td><td>Info only</td><td>Startup Board temperature</td></tr><tr><td>Min</td><td>Info only</td><td>Min. Board temperature</td></tr><tr><td>Max</td><td>Info only</td><td>Max. Board temperature</td></tr><tr><td>System Fan Speed</td><td>Info only</td><td>System Fan Speed</td></tr></table>

# 4.4.9 Advanced > Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Power-Up Watchdog</td><td>Disabled Enabled</td><td>Enbles/Disables the Watchdog Timer</td></tr><tr><td>Timeout</td><td>[Max-Value, Min-Value, Step-Value] = [0xFFFF, 0x0018, 0x0001]</td><td>The time the Power Up Watchdog should wait until it resets the system.</td></tr><tr><td>RunTime Watchdog</td><td>Disabled Enabled</td><td>The RunTime Watchdog resets the system after a certain amount of time after power up.</td></tr><tr><td>Timeout</td><td>[Max-Value, Min-Value, Step-Value] = [0xFFFF, 0x0018, 0x0001]</td><td>The time the Power Up Watchdog should wait until it resets the system.</td></tr><tr><td>ATTENTION: Pressing F12 during start up disables the Power Up Watchdog.</td><td>Info only</td><td></td></tr></table>

# 4.4.10 Advanced > Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr></table>

# 4.4.11 Advanced > Super IO Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables/Disables the serial port (COM)</td></tr><tr><td>Device Settings</td><td>IO=3F8h; IRQ=4</td><td></td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h; IRQ=4IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12</td><td>Selects optimal settings for Super IO Device</td></tr><tr><td>COM1 Control</td><td>RS232RS422RS485</td><td>Sets COM1 mode as RS-232, RS-422 or RS-485</td></tr></table>

# 4.4.12 Advanced > Super IO Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables/Disables the serial port (COM)</td></tr><tr><td>Device Settings</td><td>IO=2F8h; IRQ=3</td><td></td></tr><tr><td>Change Settings</td><td>AutoIO=3F8h; IRQ=4IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12</td><td>Selects optimal settings for Super IO Device</td></tr><tr><td>COM2 Control</td><td>RS232RS422RS485</td><td>Sets COM2 mode as RS-232, RS-422 or RS-485</td></tr></table>

# 4.4.13 Advanced > Super IO Configuration > Serial Port 3 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables/Disables the serial port (COM)</td></tr><tr><td>Device Settings</td><td>Reset Required</td><td></td></tr><tr><td>Change Settings</td><td>AutoIO=3E8h; IRQ=7IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12IO=220h; IRQ=3,4,5,6,7,9,10,11,12IO=228h; IRQ=3,4,5,6,7,9,10,11,12</td><td>Selects optimal settings for Super IO Device</td></tr></table>

# 4.4.14 Advanced > Super IO Configuration > Serial Port 4 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enables/Disables the serial port (COM)</td></tr><tr><td>Device Settings</td><td>Reset Required</td><td></td></tr><tr><td>Change Settings</td><td>AutoIO=3E8h; IRQ=7IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12IO=220h; IRQ=3,4,5,6,7,9,10,11,12IO=228h; IRQ=3,4,5,6,7,9,10,11,12</td><td>Selects optimal settings for Super IO Device</td></tr></table>

# 4.4.15 Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM0</td><td></td><td></td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Enables/Disables console redirection on COM0 port.</td></tr><tr><td>COM1</td><td></td><td></td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Enables/Disables console redirection on COM1 port.</td></tr><tr><td>COM2</td><td></td><td></td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Enables/Disables console redirection on COM2 port.</td></tr><tr><td>COM3</td><td></td><td></td></tr><tr><td>Console Redirection</td><td>Disabled Enabled</td><td>Enables/Disables console redirection on COM3 port.</td></tr></table>

# 4.4.16 Advanced > Console Redirection > COM 0 > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VT100VT100PlusVT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII character set.VT100: ASCII character set.VT100Plus: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on both connected systems. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0.Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareRTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow.Hardware flow control uses two wires to send start/stop</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables/Disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

4.4.17 Advanced > Console Redirection > COM 1 > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VT100VT100PlusVT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII character set.VT100: ASCII character set.VT100Plus: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on both connected systems. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0.Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareRTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow.Hardware flow control uses two wires to send start/stop</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables/Disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

# 4.4.18 Advanced > Console Redirection > COM 2 > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VT100VT100PlusVT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII character set.VT100: ASCII character set.VT100Plus: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on both connected systems. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0.Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareRTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow.Hardware flow control uses two wires to send start/stop</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables/Disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

4.4.19 Advanced > Console Redirection > COM 3 > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Terminal Type</td><td>VT100VT100PlusVT-UTF8ANSI</td><td>Emulation:ANSI: Extended ASCII character set.VT100: ASCII character set.VT100Plus: Extends VT100 to support color, function keys, etc.VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.The speed must be matched on both connected systems. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors.Even: parity bit is 0 if the num of 1's in the data bits is even.Odd: parity bit is 0 if num of 1's in the data bits is odd.Mark: parity bit is always 1.Space: Parity bit is always 0.Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr><tr><td>Flow Control</td><td>NoneHardwareRTS/CTS</td><td>Flow control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a 'stop' signal can be sent to stop the data flow.Once the buffers are empty, a 'start' signal can be sent to re-start the flow.Hardware flow control uses two wires to send start/stop</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnabled</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals</td></tr><tr><td>Recorder Mode</td><td>DisabledEnabled</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnabled</td><td>Enables/Disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

# 4.4.20 Advanced > Miscellaneous > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Disabled Enabled</td><td>Enables/Disables UEFI Network Stack</td></tr><tr><td>Ipv4 PXE Support</td><td>Disabled Enabled</td><td>Enables/Disables IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>Ipv6 PXE Support</td><td>Disabled Enabled</td><td>Enables/Disables IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>PXE boot wait time</td><td>[Max-Value, Min-Value, Step-Value] = [0x05, 0x00, 0x01]</td><td>Wait time in seconds to press ESC key to abort PXE boot. Use either +/- or numeric keys to set the value.</td></tr></table>

# 4.4.21 Advanced > Trusted Computing > TPM 1.2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Configuration</td><td>Info only</td><td></td></tr><tr><td>Security Device Support</td><td>Disabled Enabled</td><td>Enables/Disables BIOS support for security device. OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td>TPM State</td><td>Disabled Enabled</td><td>Enables/Disables Security Device. The computer will reboot in order to change State of the Device.</td></tr><tr><td>Pending Operation</td><td>None TPM Clear</td><td>Schedule an Operation for the Security Device. The computer will reboot in order to change State of the Device.</td></tr><tr><td>Security Device Support</td><td>Disabled Enabled</td><td>Enables/Disables BIOS support for security device. OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td>TCM State</td><td>Disabled Enabled</td><td>Enables/Disables Security Device. The computer will reboot in order to change State of the Device.</td></tr><tr><td>Pending Operation</td><td>None TPM Clear</td><td>Schedule an Operation for the Security Device. The computer will reboot in order to change State of the Device.</td></tr><tr><td>Device Select</td><td>TPM 1.2 TPM 2.0 Auto</td><td>TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated</td></tr><tr><td>Current Information</td><td>Info only</td><td></td></tr><tr><td>TPM Enabled Status</td><td>N/A, reset required</td><td></td></tr><tr><td>TPM Active Status</td><td>N/A, reset required</td><td></td></tr><tr><td>TPM Owner Status</td><td>N/A, reset required</td><td></td></tr><tr><td>TPM Enabled Status</td><td>N/A, reset required</td><td></td></tr><tr><td>TPM Active Status</td><td>N/A, reset required</td><td></td></tr><tr><td>TPM Owner Status</td><td>N/A, reset required</td><td></td></tr></table>

4.4.22 Advanced > TPM 2.0 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>IFX</td><td></td><td></td></tr><tr><td>7.85</td><td></td><td></td></tr><tr><td>Security Device Support</td><td>Disabled Enabled</td><td>Enables/Disables BIOS support for security device. OS will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr><tr><td>Active PCR banks</td><td>N/A, reset required</td><td></td></tr><tr><td>Available PCR banks</td><td>N/A, reset required</td><td></td></tr><tr><td>SHA-1 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SHA-1 PCR Bank</td></tr><tr><td>SHA256 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SHA256 PCR Bank</td></tr><tr><td>SHA384 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SHA384 PCR Bank</td></tr><tr><td>SHA512 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SHA512 PCR Bank</td></tr><tr><td>SM3_256 PCR Bank</td><td>Disabled Enabled</td><td>Enables/Disables SM3_256 PCR Bank</td></tr><tr><td>SM3_256 PCR Band</td><td>Disabled Enabled</td><td>Enables/Disables SM3_256 PCR Bank</td></tr><tr><td>Pending operation</td><td>None TPM Clear</td><td>Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device.</td></tr><tr><td>Platform Hierarchy</td><td>Disabled Enabled</td><td>Enables/Disables Platform Hierarchy</td></tr><tr><td>Storage Hierarchy</td><td>Disabled Enabled</td><td>Enables/Disables Storage Hierarchy</td></tr><tr><td>Endorsement Hierarchy</td><td>Disabled Enabled</td><td>Enables/Disables Endorsement Hierarchy</td></tr><tr><td>TPM2.0 UEFI Spec Version</td><td>TCG_1_2 TCG_2</td><td>Select the TCG2 Spec Version Support</td></tr><tr><td>Physical Presence Spec Version</td><td>1.2 1.3</td><td>Select to Tell OS to support PPI Spec Version 1.2 or 1.3. Note some HCK tests might not support 1.3.</td></tr><tr><td>Device Select</td><td>TPM 1.2 TPM 2.0 Auto</td><td>TPM 1.2 will restrict support to TPM 1.2 devices, TPM 2.0 will restrict support to TPM 2.0 devices, Auto will support both with the default set to TPM 2.0 devices if not found, TPM 1.2 devices will be enumerated.</td></tr></table>

# 4.4.23 Advanced > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Hand-off</td><td>EnabledDisabled</td><td>This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by the XHCI driver.</td></tr><tr><td>USB Mass Storage Driver Support</td><td>Disabled Enabled</td><td>Enables/Disables USB Mass Storage Driver Support.</td></tr><tr><td colspan="3">USB hardware delays and time-outs:</td></tr><tr><td>USB transfer time-out</td><td>1 sec5 sec10 sec20 sec</td><td>The time-out value for Control, Bulk, and Interrupt transfers.</td></tr><tr><td>Device reset time-out</td><td>10 sec20 sec30 sec40 sec</td><td>USB mass storage device Start Unit command time-out.</td></tr><tr><td>Device power-up delay</td><td>Auto Manual</td><td>Maximum time the device will take before it properly reports itself to the Host Controller. 'Auto' uses the default value: 100 ms for a Root port, for a Hub port the delay is taken from the Hub descriptor.</td></tr><tr><td>Device power-up delay in seconds</td><td>[Max-Value, Min-Value, Step-Value] = [0x28, 0x01, 0x01]</td><td>Delay range is 1 to 40 seconds, in one second increments.</td></tr></table>

4.4.24 Advanced > Engineering Mode Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Reset before POST</td><td>Disabled Enabled</td><td>Enables/Disables reset events before POST.</td></tr><tr><td>- Count of reset events</td><td>[Max-Value, Min-Value, Step-Value] = [0x0A, 0x01, 0x01]</td><td>Number of reset event before POST (Note: this option is disabled when Reset before POST is disabled)</td></tr><tr><td>- Delay time</td><td>[Max-Value, Min-Value, Step-Value] = [0x2710, 0x0001, 0x0001]</td><td>Set the delay time before generating a Reset event if timing needs adjustment (ms)</td></tr><tr><td>- Reset Type</td><td>Cold ResetWarm Reset</td><td>Select a warm or cold reset.</td></tr></table>

# 4.5 Chipset

# 4.5.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>VT-d</td><td>Supported</td><td></td></tr></table>

# 4.5.2 Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td></td></tr><tr><td>Memory Speed</td><td>Info only</td><td></td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td></td></tr><tr><td>Controller 0 Channel 0 Slot 0</td><td>Info only</td><td></td></tr><tr><td>Controller 0 Channel 0 Slot 1</td><td>Info only</td><td></td></tr><tr><td>Maximum Memory Frequency</td><td>Auto, 1067, 1200, 1333, 1467, 1733, 1867, 2133, 2267, 2533, 2667, 2933, 3067, 3333, 3467, 3733, 3867, 4133, 4267, 4533, 4667, 4933, 5067, 5333, 5467, 5733, 5867, 6133, 6267, 6533, 6667, 6933, 7067, 7467, 7733, 7867, 8000, 8133, 8267, 1400, 1500, 1700, 1800, 1900, 2100, 2200, 2300, 2500, 2600, 2700, 2900, 3000, 3100, 3300, 3400, 3500, 3700, 3800, 3900, 4100, 4200, 4300, 4500, 4600, 4700, 4900, 5000, 5100, 5300, 5400, 5500, 5700, 5800, 5900, 6100, 6200, 6300, 6500, 6600, 6700, 6900, 7000, 7100, 7300, 7400, 7500, 7700, 7800, 7900, 8400, 8400, 8400, 1600, 2000, 2400, 2800, 3200, 3600, 4000, 4400, 4800, 5200, 5600, 6000, 6400, 6800, 7200, 7600, 8400</td><td>Maximum Memory Frequency in Mhz</td></tr><tr><td>Max TOLUD</td><td>Dynamic, 1 GB,1.25 GB, 1.5 GB,1.75 GB, 2 GB, 2.25 GB, 2.5 GB,2.75 GB, 3 GB, 3.25 GB, 3.5 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphics controller.</td></tr></table>

# 4.5.3 Chipset > System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Sets GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB</td><td>Sets Aperture Size</td></tr><tr><td>DVMT Pre-Allocated</td><td>0M32M64M96M128M160M4M8M12M16M20M24M28M32M/F736M40M44M48M52M56M60M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMAX</td><td>DVMT5.0 Total Graphic Memory size used by the Internal Graphics Device.</td></tr><tr><td>VDD Enable</td><td>DisabledEnabled</td><td>Enables/Disables forcing of VDD in the BIOS</td></tr></table>

# 4.5.4 Chipset > System Agent (SA) Configuration > VDM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable VMD controller</td><td>Disabled Enabled</td><td>Enables/Disables VMD controller</td></tr><tr><td>Enable VMD Global Mapping</td><td>Disabled Enabled</td><td>Enables/Disables VMD Global Mapping.</td></tr><tr><td>Map this Root Port under VMD</td><td>Disabled Enabled</td><td>Maps/UnMaps this Root Port to VMD</td></tr><tr><td>Root Port BDF details</td><td></td><td>SATA Controller</td></tr><tr><td>RAID0</td><td>Disabled Enabled</td><td>Enables/Disables RAID0 support</td></tr><tr><td>RAID1</td><td>Disabled Enabled</td><td>Enables/Disables RAID1 support</td></tr><tr><td>RAID5</td><td>Disabled Enabled</td><td>Enables/Disables RAID5 support</td></tr></table>

# 4.5.5 Chipset > System Agent (SA) Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Clock Gating</td><td>DisabledEnabled</td><td>Enables/Disables PCI ExpressClock Gating for each root port.</td></tr><tr><td>Fia Programming</td><td>DisabledEnabled</td><td>Enables/Disables loading FiaConfiguration for each root port.</td></tr><tr><td>PCI Express Power Gating</td><td>DisabledEnabled</td><td>Enables/Disables PCI ExpressPower Gating for each root port.</td></tr><tr><td>Compliance Test Mode</td><td>DisabledEnabled</td><td>Enable when using ComplianceLoad Board</td></tr><tr><td>PCIe function swap</td><td>DisabledEnabled</td><td>When Disabled, prevents PCIERootport function swap. If anyfunction other than Oth is enabled,Oth will become visible.</td></tr><tr><td>CDR Relock for PEG60</td><td>DisabledEnabled</td><td>Enables/Disables CDR Relock</td></tr><tr><td>NewFOM for PEG60</td><td>DisabledEnabled</td><td>Enables/Disables New FOM</td></tr><tr><td>CDR Relock for PEG10</td><td>DisabledEnabled</td><td>Enables/Disables CDR Relock</td></tr><tr><td>NewFOM for PEG10</td><td>DisabledEnabled</td><td>Enables/Disables New FOM</td></tr><tr><td>Assertion on Link Down GPIOs</td><td>DisabledEnabled</td><td>GPIO Assertion on Link Down</td></tr><tr><td>Enable ClockReq Messaging</td><td>DisabledEnabled</td><td>Enables/Disables ClockReq Messaging</td></tr><tr><td>PCI Express Slot Selection</td><td>M2CEMx4 Slot</td><td>Selects the PCIe M2 or CEMx4 slot</td></tr><tr><td>PCIE Resizable BAR Support</td><td>DisabledEnabled</td><td>Enables/Disables PCIE Resizable BAR Support</td></tr><tr><td>Enable RST GPIO Delay</td><td>DisabledEnabled</td><td>Enables/Disables RST GPIO Delay</td></tr><tr><td>RST GPIO Delay</td><td>100</td><td>RST GPIO Delay (ms)</td></tr><tr><td>SA0XC</td><td>DisabledEnabled</td><td></td></tr><tr><td colspan="3">&gt; PCI Express Root Port 1</td></tr></table>

# 4.5.6 Chipset > PCH-IO Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Legacy IO Low Latency</td><td>DisabledEnabled</td><td>Set to enable low latency of legacy IO. Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.</td></tr><tr><td>DMI Link ASPM Control</td><td>DisabledL0sL1L0sL1Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>Port8xh Decode</td><td>Disabled,Enabled</td><td>Enables/Disables PCI Express Port8xh Decode.</td></tr><tr><td>Port8xh Decode Port#</td><td>[Max-Value, Min-Value, Step-Value] = [0x17, 0x00, 0x01]</td><td>Selects PCI Express Port8xh Decode Root Port. User to ensure port availability.</td></tr><tr><td>Peer Memory Write Enable</td><td>Disabled Enabled</td><td>Enables/Disables Peer Memory Write</td></tr><tr><td>Compliance Test Mode</td><td>Disabled Enabled</td><td>Enable when using Compliance Load Board</td></tr><tr><td>&gt; PCI Express Root Port 5</td><td></td><td></td></tr><tr><td>&gt; PCI Express Root Port 6</td><td></td><td></td></tr><tr><td>&gt; PCI Express Root Port 7</td><td></td><td></td></tr><tr><td>&gt; PCI Express Root Port 8</td><td></td><td></td></tr></table>

# 4.5.7 Chipset > PCH-IO Configuration > SATA and RST Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>DisabledEnabled</td><td>Enables/Disables SATA Device.</td></tr><tr><td>SATA Test Mode</td><td>DisabledEnabled</td><td>Enables/Disables Test Mode (Loop Back).</td></tr><tr><td colspan="3">&gt;Software Feature Mask Configuration</td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enables/Disables PCH to aggressively enter link power state.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>Serial ATA Port</td><td></td><td></td></tr><tr><td>Software Preserve</td><td></td><td></td></tr><tr><td>Port 0</td><td>DisabledEnabled</td><td>Enables/Disables SATA Port</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable</td></tr><tr><td>Configured as eSATA</td><td>Hot Plug supported</td><td></td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any ports, Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk Drive, Solid State Drive</td><td>Identifies if the SATA port is connected to a Solid State Drive or Hard Disk Drive.</td></tr><tr><td>Topology</td><td>UnknownISATADirect ConnectFlexM2</td><td>SATA topology</td></tr><tr><td>SATA Port 0 DevSlp</td><td>DisabledEnabled</td><td>Enables/Disables SATA Port 0 DevSlp. For DevSlp to work, both the hard drive and SATA port need to support the DevSlp function, otherwise unexpected behavior might happen. Check board design before enabling it.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enables/Disables DITO Configuration</td></tr><tr><td>DITO Value</td><td>625</td><td></td></tr><tr><td>DM Value</td><td>15</td><td></td></tr><tr><td>Port 1</td><td>DisabledEnabled</td><td>Enables/Disables SATA Port</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable</td></tr><tr><td>Configured as eSATA</td><td>Hot Plug supported</td><td></td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port external.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any port, Staggered Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk Drive, Solid State Drive</td><td>Identifies if the SATA port is connected to a Solid State Drive or Hard Disk Drive.</td></tr><tr><td>Topology</td><td>Unknown ISATA Direct Connect Flex M2</td><td>SATA topology</td></tr><tr><td>SATA Port 1 DevSlp</td><td>Disabled Enabled</td><td>Enables/Disables SATA Port 0 DevSlp. For DevSlp to work, both the hard drive and SATA port need to support the DevSlp function, otherwise unexpected behavior might happen. Check board design before enabling it.</td></tr><tr><td>DITO Configuration</td><td>Disabled Enabled</td><td>Enables/Disables DITO Configuration</td></tr><tr><td>DITO Value</td><td>625</td><td></td></tr><tr><td>DM Value</td><td>15</td><td></td></tr></table>

# 4.5.8 Chipset > PCH-IO Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>xDCI Support</td><td>DisabledEnabled</td><td>Enables/Disables xDCI(USB OTG Device).</td></tr><tr><td>USB2 PHY Sus Well Power Gating</td><td>DisabledEnabled</td><td>Select 'Enabled' to enable SUS Well PG for USB2 PHY. This option has no effect on PCH-H</td></tr><tr><td>USB3 Link Speed Selection</td><td>GEN1GEN2</td><td>This option is to select USB3 Link Speed GEN1 or GEN2</td></tr><tr><td>USB Port Disable Override</td><td>DisabledSelect Per-Pin</td><td>Selectively Enables/Disables the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB SS Physical Connector #0</td><td>DisabledEnabled</td><td rowspan="12">Enables/Disables this USB Physical Connector (physical port). Once disabled, any USB devices plugged into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB SS Physical Connector #1</td><td>DisabledEnabled</td></tr><tr><td>USB SS Physical Connector #2</td><td>DisabledEnabled</td></tr><tr><td>USB SS Physical Connector #3</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #0</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #1</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #2</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #3</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #4</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #5</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #6</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #7</td><td>DisabledEnabled</td></tr><tr><td>USB HS Physical Connector #8</td><td>DisabledEnabled</td><td rowspan="2">Enables/Disables this USB Physical Connector (physical port). Once disabled, any USB devices plugged into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #9</td><td>DisabledEnabled</td></tr></table>

# 4.5.9 Chipset > PCH-IO Configuration > Miscellaneous Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>RTC Memory Lock</td><td>DisabledEnabled</td><td>Enabling will lock bytes 38h-3Fh in the lower/upper 128-byte bank of RTC RAM</td></tr><tr><td>BIOS Lock</td><td>Disabled Enabled</td><td>Enables/Disables the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr><tr><td>State After G3</td><td>S0 State S5 State</td><td>Specifies what state to go to when power is re-applied after a power failure (G3 state).</td></tr></table>

# 4.5.10 Chipset > PCH-IO Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>Disabled Enabled</td><td>Controls detection of the HD-Audio device.</td></tr><tr><td>Audio Output Selection</td><td>Speaker-out Line-out</td><td>Audio Output Selection</td></tr></table>

# 4.5.11 Chipset > PCH-IO Configuration > SerialIO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>I2C3 Controller</td><td>Disabled Enabled</td><td>Enables/Disables Seriallo Controller</td></tr><tr><td>I2C4 Controller</td><td>Disabled Enabled</td><td></td></tr></table>

# 4.6 Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Minimum length</td><td>3</td><td></td></tr><tr><td>Maximum length</td><td>20</td><td></td></tr></table>

# 4.7 Boot

4.7.1 Boot > Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td><td></td></tr><tr><td>Setup Prompt Timeout</td><td>[Max-Value, Min-Value, Step-Value] = [0xFFFF, 0x0001, 0x0001]</td><td colspan="2">Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td colspan="2">Selects the keyboard NumLock state.</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td colspan="2">Enables/Disables Quiet Boot option.</td></tr><tr><td>Fast Boot</td><td>Disabled Enabled</td><td colspan="2">Enables/Disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>Boot Option #1</td><td rowspan="10">Hard Disk NVME CD/DVD SD USB Hard Disk USB CD/DVD USB Key USB Floppy USB Lan Network Disabled</td><td>Hard Disk</td><td rowspan="10">Sets the system boot order</td></tr><tr><td>Boot Option #2</td><td>NVME</td></tr><tr><td>Boot Option #3</td><td>CD/DVD</td></tr><tr><td>Boot Option #4</td><td>SD</td></tr><tr><td>Boot Option #5</td><td>USB Hard Disk</td></tr><tr><td>Boot Option #6</td><td>USB CD/DVD</td></tr><tr><td>Boot Option #7</td><td>USB Key</td></tr><tr><td>Boot Option #8</td><td>USB Floppy</td></tr><tr><td>Boot Option #9</td><td>USB Lan</td></tr><tr><td>Boot Option #10</td><td>Network</td></tr></table>

# 4.8 Save & Exit

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td>YesNo</td><td>Exits system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td>YesNo</td><td>Exits system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td>YesNo</td><td>Resets the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td>YesNo</td><td>Resets system setup without saving any changes.</td></tr><tr><td>Save Options</td><td colspan="2">Info only</td></tr><tr><td>Save Changes</td><td>YesNo</td><td>Saves changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td>YesNo</td><td>Discards changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td>YesNo</td><td>Restores/Loads default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td>YesNo</td><td>Saves the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td>YesNo</td><td>Restores the User Defaults to all the setup options.</td></tr><tr><td>Boot Override</td><td colspan="2">Info only</td></tr><tr><td>Launch EFI Shell from filesystem device</td><td colspan="2"></td></tr></table>

# 5 Driver & Application Installation

After installing the operating system, all related drivers must be installed for the system to function properly. This section describes the drivers needed for Windows operating systems and the procedures to install them. For other operating system support, contact ADLINK for further information.

Visit the ADLINK web site to download drivers:

https://www.adlinktech.com/Products/Panel\_PCs\_Monitors/Panel\_PCs\_Monitors/Titan2

# 5.1 Driver Installation Order

Install drivers in the following order.

1. Fully install Microsoft Windows before installing any drivers. Most standard I/O device drivers have been included in Microsoft Windows. For Windows 10 IoT Enterprise users, Administrator privilege is required to install the drivers.
2. Install the chipset driver.
3. Install the graphics driver.
4. Install the Ethernet driver.
5. Install the Management Engine driver.
6. Install the Serial I/O driver.
7. Install the DI/O Driver.

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# Important Safety Instructions

For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage.

 Read these safety instructions carefully.
 Keep the User’s Manual for future reference.
 Read the Specifications section of this manual for detailed information on the recommended operating environment.
It is recommended that the device be installed in Information Technology Rooms that are in accordance with Article 645 of the National Electrical Code and NFPA 75.
? When installing/mounting or uninstalling/removing device is required:
 Turn off power and unplug any power cords/cables.
 Reinstall all chassis covers before restoring power.
 To avoid electrical shock and/or damage to device:
 Keep device away from water or liquid sources.
 Keep device away from high heat or humidity.
 Keep device properly ventilated (do not block or cover ventilation openings).
 Always use recommended voltage and power source settings.
 Always install and operate device near an easily accessible electrical outlet.
 Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate device on stable surfaces and/or recommended mountings.
 The device is powered by an adapter or DC source. Ensure that the adapter or DC source is properly grounded.
 If the device will not be used for long periods of time, turn off and unplug from its power source.
 Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools.

 A Lithium-type battery may be provided for uninterrupted backup or emergency power.

![A yellow triangular warning sign featuring a black exclamation point in the center is displayed above the text 'CAUTION:' in black capital letters.](.sp-titan2-50m-p5300-1010-11-240912/00a6cc6c7ac7d888d833688468426460d5d6539449b8490bcc301ac949376d6f.jpg)

Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

 The device must be serviced by authorized technicians when:

 The power cord or plug is damaged
 Liquid has entered the device interior
 The device has been exposed to high humidity and/or moisture
 The device is not functioning or does not function according to the User’s Manual
 The device has been dropped and/or damaged and/or shows obvious signs of breakage

Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

 It is recommended that the device be installed only in a server room or computer room where access is:

 Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required
 Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.sp-titan2-50m-p5300-1010-11-240912/e13593c5425c90d974867bcbb4c799d3adc596ca15db1d47f7d0f36f6944317e.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# Consignes de Sécurité Importante

Pour la sécurité de l'utilisateur, veuillez lire et suivre toutes les instructions, avertissements, mises en garde et notes marqués dans ce manuel et sur l'appareil associé avant de manipuler/d'utiliser l'appareil, afin d'éviter toute blessure ou tout dommage.

 Lisez attentivement ces consignes de sécurité
? Conservez le manuel de l'utilisateur pour pouvoir le consulter ultérieurement
Lisez la section Spécifications de ce manuel pour des informations détaillées sur l'environnement d'exploitation recommandé
? Il est recommandé d'installer l'appareil dans Information Salles technologiques conformes à l'article 645 du Code national de l'électricité et NFPA 75.

Lorsque l'installation/le montage ou la désinstallation/le retrait du périphérique est requis:

 Mettez l'appareil hors tension et débranchez tous les cordons/câbles d'alimentation
 Réinstallez tous les couvercles de châssis avant de rétablir l'alimentation

 Pour éviter les chocs électriques et/ou d’endommager l’appareil:

 Tenez l'appareil à l'écart de toute source d'eau ou de liquide.

 Tenez l'appareil à l'écart d'une forte chaleur ou d'une humidité élevée.

 Maintenez l'appareil correctement ventilé (n'obstruer ou ne couvrez pas les ouvertures de ventilation).

 Utilisez toujours les réglages de tension et de source d'alimentation recommandés.

 Installez et utilisez toujours l'appareil près d'une prise de courant facilement accessible.

 Fixez le cordon d'alimentation (ne placez aucun objet sur le cordon d'alimentation).

 Installez/fixez et utilisez l'appareil uniquement sur des surfaces stables et/ou sur les fixations recommandées.
 L'ordinateur Smart Touch est alimenté par un adaptateur ou une source CC. Veuillez vous assurer que l'adaptateur ou la source CC doit conserver la connexion à la terre s'il est doté d'une protection.

Si l'appareil ne doit pas être utilisé pendant de longues périodes, éteignez-le et débranchez-le de sa source d'alimentation
N'essayez jamais de réparer l'appareil, qui ne doit être réparé que par un personnel technique qualifié à l'aide d'outils appropriés
 Une batterie de type Lithium peut être fournie pour une alimentation de secours ininterrompue ou d'urgence.

![A vertical safety sign featuring a yellow triangle with a thick black border containing a black exclamation point. Below the triangle is the word 'CAUTION' in black capital letters.](.sp-titan2-50m-p5300-1010-11-240912/32d6a93bbf20b1ef1e1b97544fee04339878ae61506483a8603a0a192ecda06b.jpg)

ATTENTION: Risque d’explosion si la pile est remplacée par une autre de type incorrect. Veuillez jeter les piles usagées de façon appropriée.

 L'appareil doit être entretenu par des techniciens agrees lorsque:

 Le cordon d’alimentation ou la prise est endommagé(e)
 Un liquide a pénétré à l'intérieur de l'appareil.
 L'appareil a été exposé à une forte humidité et/ou de la buée.
 L'appareil ne fonctionne pas ou ne fonctionne pas selon le manuel de l'utilisateur.
 L'appareil est tombé et/ou a été endommagé et/ou présente des signes évidents de dommage.

Débranchez le cordon d'alimentation avant de desserrer les vis à oreilles et serrez toujours les vis à oreilles avec un tournevis avant de mettre le système en marche.

 Il est recommandé d'installer l'appareil uniquement dans une salle de serveurs ou une salle informatique où l'accès est:

 Réservé au personnel de service qualifié ou aux utilisateurs familiarisés avec les restrictions appliquées à l'emplacement, aux raisons de ces restrictions et toutes les précautions requises

 Uniquement autorisé par l'utilisation d'un outil, d'une serrure et d'une clé, ou d'un autre moyen de sécurité, et contrôlé par l'autorité responsable de l'emplacement.

![Yellow triangular warning sign with black smoke symbol indicating hot weather](.sp-titan2-50m-p5300-1010-11-240912/ef6e45331b5eee098d5085dd7688f4af2f15530ccba60535e36d642a4dee5fae.jpg)

# RISQUE DE BRÛLURES

Partie chaude! Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

# EMC Compliance

# CE Warning

This is a Class B product. In a domestic environment, this product may cause radio interference, in which case the user may be required to take adequate measures.

# FCC Warning

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

 Reorient or relocate the receiving antenna.
 Increase the separation between the equipment and receiver.
 Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
 Consult the dealer or an experienced radio/TV technician for help.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert.aspx

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District,

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Straße 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.sp-titan2-50m-p5300-1010-11-240912/sp-titan2-50m-p5300-1010-11-240912.pdf)