# SP2-MTL Series

User’s Guide

intel

![Exploded view of a computer monitor showing internal circuit board and fan components (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/089a209a0675befd4f6e3904c72bb356f04b0ac2576b2f28ef3ffc017ea2be19.jpg)

Revision: Rev. 1.1

Date: 2025-05-15

CopyrighPart Number: 2025 ADLINK Tech50M-P1600-1010

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2025-05-09</td><td>AL</td></tr><tr><td>1.1</td><td>Introduction, specifications, pinouts and connectors, and getting started updated</td><td>2025-05-15</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![A yellow triangle with a thick black border containing a black exclamation point in the center.](.sp2-mtl-50m-p1600-1010-11/7ed631145aaec2fdc4b3892d360a3649d7ce07fe2c62be2bc4a6eeb3bae3c03b.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black and white line drawing of a wheeled trash bin with a lid. A large 'X' is drawn over the bin, indicating it should not be used or disposed of. Below this symbol is a solid black rectangular bar.](.sp2-mtl-50m-p1600-1010-11/cf01d289f5dd89459057ebcd75da403466b69e3104ec996044306197a6b0a441.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2025 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully:

Keep the User’s Manual for future reference.
• Read the Specifications section of this manual for detailed information on the recommended operating environment.
It is recommended that the device be installed in Information
• Technology Rooms that are in accordance with Article 645 of the National Electrical Code and NFPA 75.
• When installing/mounting or uninstalling/removing device is required:

o Turn off power and unplug any power cords/cables.
o Reinstall all chassis covers before restoring power.

• To avoid electrical shock and/or damage to device:

o Keep device away from water or liquid sources.
o Keep device away from high heat or humidity.
o Keep device properly ventilated (do not block or cover ventilation openings).
o Always use recommended voltage and power source settings.
o Always install and operate device near an easily accessible electrical outlet.
o Secure the power cord (do not place any object on/over the power cord).
o Only install/attach and operate device on stable surfaces and/or recommended mountings.

o The device is powered by an adapter or DC source. Ensure that the adapter or DC source is properly grounded.

• If the device will not be used for long periods of time, turn off and unplug from its power source.

• Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools.

• A Lithium-type battery may be provided for uninterrupted backup or emergency power.

• The device must be serviced by authorized technicians when:

o The power cord or plug is damaged.
o Liquid has entered the device interior.
o The device has been exposed to high humidity and/or moisture.
o The device is not functioning or does not function according to the User’s Manual.
o The device has been dropped and/or damaged and/or shows obvious signs of breakage.

• Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

• It is recommended that the device be installed only in a server room or computer room where access is:

o Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.
o Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

![The image displays a standard warning symbol. It features a yellow triangle with rounded corners pointing upward. Centered inside the triangle is a white exclamation point. The background is white.](.sp2-mtl-50m-p1600-1010-11/9de578bf12b941c57b02f537438e76b4059c1de61ee48d7b7c1ef806960a7be5.jpg)

Caution: Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

![The image shows a triangular warning sign with a yellow background and a thick black border. Inside the triangle is a black symbol depicting a horizontal line at the bottom with three wavy vertical lines rising from it, representing heat or a hot surface.](.sp2-mtl-50m-p1600-1010-11/e5b499c85293638248e6ebe49f21642d3acb8e4b9e4423068ff908687c68dc81.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# Consignes de Sécurité Importante

Pour la sécurité de l'utilisateur, veuillez lire et suivre toutes les instructions, avertissements, mises en garde et notes marqués dans ce manuel et sur l'appareil associé avant de manipuler/d'utiliser l'appareil, afin d'éviter toute blessure ou tout dommage.

• Lisez attentivement ces consignes de sécurité
• Conservez le manuel de l'utilisateur pour pouvoir le consulter Ultérieurement
• Lisez la section Spécifications de ce manuel pour des informations détaillées sur l'environnement d'exploitation recommandé
Il est recommandé d'installer l'appareil dans Information Salles technologiques conformes à l'article 645 du Code national de l'électricité et NFPA 75.

• Lorsque l'installation/le montage ou la désinstallation/le retrait du périphérique est requis:

o Mettez l'appareil hors tension et débranchez tous les cordons/câbles d'alimentation
o Réinstallez tous les couvercles de châssis avant de rétablir l'alimentation

• Pour éviter les chocs électriques et/ou d’endommager l’appareil:

o Tenez l'appareil à l'écart de toute source d'eau ou de liquide.
o Tenez l'appareil à l'écart d'une forte chaleur ou d'une humidité élevée.
o Maintenez l'appareil correctement ventilé (n'obstruer ou ne couvrez pas les ouvertures de ventilation).
o Utilisez toujours les réglages de tension et de source d'alimentation recommandés.
o Installez et utilisez toujours l'appareil près d'une prise de courant facilement accessible.
o Fixez le cordon d'alimentation (ne placez aucun objet sur le cordon d'alimentation).
o Installez/fixez et utilisez l'appareil uniquement sur des surfaces stables et/ou sur les fixations recommandées.

o L'ordinateur Smart Touch est alimenté par un adaptateur ou une source CC. Veuillez vous assurer que l'adaptateur ou la source CC doit conserver la connexion à la terre s'il est doté d'une protection.

• Si l'appareil ne doit pas être utilisé pendant de longues périodes, éteignez-le et débranchez-le de sa source d'alimentation
• N'essayez jamais de réparer l'appareil, qui ne doit être réparé que par un personnel technique qualifié à l'aide d'outils appropriés
• Une batterie de type Lithium peut être fournie pour une alimentation de secours ininterrompue ou d'urgence.
L'appareil doit être entretenu par des techniciens agrees lorsque:

o Le cordon d’alimentation ou la prise est endommagé(e)
o Un liquide a pénétré à l'intérieur de l'appareil.
o L'appareil a été exposé à une forte humidité et/ou de la buée.
o L'appareil ne fonctionne pas ou ne fonctionne pas selon le manuel de l'utilisateur.
o L'appareil est tombé et/ou a été endommagé et/ou présente des signes évidents de dommage.

• Débranchez le cordon d'alimentation avant de desserrer les vis à oreilles et serrez toujours les vis à oreilles avec un tournevis avant de mettre le système en marche.
• Il est recommandé d'installer l'appareil uniquement dans une salle de serveurs ou une salle informatique où l'accès est:

o Réservé au personnel de service qualifié ou aux utilisateurs familiarisés avec les restrictions appliquées à l'emplacement, aux raisons de ces restrictions et toutes les précautions requises
o Uniquement autorisé par l'utilisation d'un outil, d'une serrure et d'une clé, ou d'un autre moyen de sécurité, et contrôlé par l'autorité responsable de l'emplacement.

![The image displays a yellow triangular warning sign with a thick black border. Inside the triangle, three black wavy lines rise upward above a single horizontal black line, indicating a hot surface.](.sp2-mtl-50m-p1600-1010-11/88fa76cbd3698fd7970a566291cea737950635e73e986afc0851c99b68a254fa.jpg)

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

# EMC Compliance

# CE Warning

This is a Class B product. In a domestic environment, this product may cause radio interference, in which case the user may be required to take adequate measures.

# FCC warning

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy. If not installed and used in accordance with the instructions, it may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.

If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try one or more of the following measures to correct the interference:

Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and the receiver.
• Connect the equipment to an outlet on a circuit different from the one to which the receiver is connected.
. Consult the dealer or an experienced radio/TV technician for assistance.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information.

![The image displays a red icon on a white background. It features a square outline with the top-right corner folded down, resembling a document. Inside the outline are three horizontal red lines stacked vertically.](.sp2-mtl-50m-p1600-1010-11/906524ede03e4c78098073a532c304c040554d6aa401b358344539b1f55ecc48.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image shows a yellow triangular warning sign containing a white exclamation mark in its center.](.sp2-mtl-50m-p1600-1010-11/36995a41c27014f3e2e6c830bed469726081e60ec705a176031f5d07d4f2830c.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a red, upward-pointing triangle containing a white exclamation point in its center.](.sp2-mtl-50m-p1600-1010-11/96bef00dd07e85b68d58b2c0a652ffaa12d050cdfbfb3aaf0ecdfe7f21f023bd.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

List of Figures .. .12

1. Introduction .. .13

1.1. Overview... ... 13
1.2. Features .. .... 13
1.3. Package Contents... .. 13
1.4. Optional Accessories... .. 14

2. Block Diagram .. .16
3. Specifications.. 17
4. Mechanical Layout... ..20

4.1. Mechanical Dimensions.. .. 20

4.2. I/O Panel Connector Locations.. . 23

4.3. Mainboard Connector Locations .. ... 24

5. Thermal Options.. .25

5.1. Heatsink Dimensions .. . 25
5.2. Active Cooling Heatsink.. .. 26

6. Pinouts and Connectors.. .27

6.1. Power Connector... . 27
6.2. SATA Power Connector... ... 27
6.3. SATA Data Connector.. ... 28
6.4. Capacitive Touch Connector.. .. 28
6.5. Mini PCIe Connector .. . 29
6.6. M.2 2230, E Key for Wi-Fi/Bluetooth Modules... . 30
6.7. Function Module Board Connector .. .. 31
6.8. LVDS/e-DP Connector... .. 33
6.9. Mini DP Connector.. ... 34
6.10. Internal USB2.0 Wafer.. . 34
6.11. GSPI Wafer .. ... 35
6.12. PWR/RST Wafer... . 35
6.13. Buzzer Wafer ... ... 35
6.14. MXM Fan Wafer .. .. 36

6.15. Volume/Backlight Wafer ... .. 36

6.16. 33 Keypad Wafer ... . 37

6.17. PCIE X8 Gen4 Slot... ... 38

6.18. CPU Fan Wafer... .. 39

6.19. LAN2 PD Wafer... .. 40

6.20. Line Out/Mic In Wafer.. . 40

6.21. Speaker Wafer... .. 41

6.22. LED Wafer .. .. 41

6.23. EC SMbus Wafer for UPS... . 42

6.24. SoC 1st I2C Wafer.. .. 42

6.25. SoC 2nd I2C Wafer... .. 42

6.26. COM Port 1 Wafer.. .. 43

6.27. COM Port 2 Wafer.. .. 43

6.28. RTC Battery Wafer... ... 44

6.29. GPIO Wafer ... ... 44

6.29.1 4-Channel Digital Input... . 44

6.29.2 4-Channel Digital Output .. .... 45

6.30. M.2 2280, M Key for SATA/PCIE X4 NVME Modules. .. 48

6.31. Thunderbolt Type C Connector.. .. 49

6.32. USB3.2 Gen2 Dual Port 1 Connector.. ... 49

6.33. USB3.2 Gen2 Dual Port 2 Connector... .. 50

6.34. DP Connector... ... 50

6.35. LAN1 RJ45 Connector... .. 51

6.36. LAN2 RJ45 Connector.. ... 51

6.37. LAN (I226) LED Connector Position .. . 52

6.37.1 LAN1/2 Active/Link LED .. . 52

6.38. Jumper Setting... . 53

7. Getting Started .. .54

7.1. Adding or Changing Memory ... .. 54

7.2. Installing a Wi-Fi-Module .... ... 55

7.3. Installing an LTE Module ... ... 58

7.4. Mounting .. ..... 61

7.4.1 Panel Mounting . ... 62

7.4.2 VESA Mounting.. ... 68

8. Driver and Application Installation . .69

9. BIOS Setup...... ...70

9.1. Menu Structure... ... 70

9.2. Main ..... ... 71

9.2.1 BIOS Information... . 71
9.2.2 System Information.. . 71
9.2.3 Board Information . . 72
9.2.4 System Date and Time. . 72

9.3. Advanced ... . 73

9.3.1 CPU Configuration.. ... 73
9.3.2 Power Management .. . 73
9.3.3 Graphic Configuration .. . 74
9.3.4 Super I/O Configuration.. . 76
9.3.5 BIOS Watchdog Timer .. . 79
9.3.6 Serial Console Redirection . . 79
9.3.7 Hardware Monitor .. . 81
9.3.8 NVMe Configuration .. . 82
9.3.9 Trusted Computing .. ... 83
9.3.10 Miscellaneous ...
9.3.11 Network Stack Configuration... . 83

9.4. Chipset .. . 84

9.4.1 System Agent (SA) Configuration .. . 84
9.4.2 PCH-I/O Configuration.. . 84

9.5. Security .... . 91

9.5.1 Secure Boot Menu.. ... 92
9.6. Boot .... . 93
9.6.1 Boot Configuration.. ... 93
9.7. Save & Exit... . 94
9.7.1 Save Options.. . 94

# List of Figures

Figure 1 - Module function diagram . .16
Figure 2 - SP2-10WP-MTL mechanical dimensions.. ..20
Figure 3 - SP2-15WP-MTL mechanical dimensions.. .2
Figure 4 - SP2-21WP-MTL mechanical dimensions.. .22
Figure 5 - I/O panel connector locations... .23
Figure 6 - Mainboard connector locations .... .24
Figure 7 - Module function diagram . .25
Figure 8 - Active cooling heatsink .. ..26
Figure 9 - Digital input circuit ... ..46
Figure 10 - Digital output circuit...... ...46
Figure 11 - SP2-10WP cutout dimensions .... .62
Figure 12 - SP2-15WP cutout dimensions . ..63
Figure 13 - SP2-21WP cutout dimensions .... ..64
Figure 14 - Mounting clip dimensions.. ..67

# 1. Introduction

# 1.1. Overview

The SP2-MTL Series open-frame panel PC is based on Intel® Core™ Ultra processors, providing flexible I/O options. The SP2-MTL Series is a compactsized solution that offers efficient capabilities, making it easy to integrate into kiosks and panel PC applications.

# 1.2. Features

• High power efficiency with $1 4 ^ { \mathrm { t h } }$ Gen Intel® Core™ series processors (formerly Meteor Lake-H).
• Extensive I/O and function expansion through wire-to-board connectors and custom function modules.
• Comprehensive expansion and customization options for fast and easy integration with all form factors, kiosks, and all-in-one panel PC applications.
• Enhanced protection in case of sudden power outage with support for back-up battery (Optional).
• Pre-compliance EMC testing and high ESD tolerance.
• High reliability in case of power fluctuation, with an optional 9V-36V DC voltage range.
Simple cabling with optional Power Over Ethernet (60W).
• Supports up to 4 displays, including integrated panel, DisplayPort, Mini DisplayPort, and USB Type-C (Optional).

# 1.3. Package Contents

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any products to ADLINK.

Ensure that the following items are included in the package.

• 1x SP2-MTL Series Smart Panel

# 1.4. Optional Accessories

Adapter and Power Cables

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>120W (12V 10A)</td><td>31-62163-0000-A0</td><td></td></tr><tr><td>Power cable</td><td>30-21863-0000-A0</td><td>Connecting between adapter and mainboard</td></tr></table>

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>SP2/OM-215_Clip_Kits</td><td>91-95337-0010</td><td>With 17 pcs clips</td></tr><tr><td>SP2/OM-156_Clip_Kits</td><td>91-95337-1010</td><td>With 14 pcs clips</td></tr><tr><td>SP2/OM-101_Clip_Kits</td><td>91-95337-2010</td><td>With 8 pcs clips</td></tr></table>

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>SP2-MTL_215 Rear cover</td><td>91-95394-100E</td><td></td></tr><tr><td>SP2-MTL_101/156 Rear cover</td><td>91-9539-100E</td><td></td></tr><tr><td>VESA bracket</td><td>91-95240-0010</td><td>The VESA bracket screws on rear cover</td></tr></table>

Wireless modules

<table><tr><td>Item</td><td>Part Number</td></tr><tr><td>Wi-Fi kit – ENL-R8852BE</td><td>91-95266-400E</td></tr><tr><td>LTE module</td><td>91-95277-0010</td></tr></table>

Connector Cables

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>USB 2.0 cable</td><td>30-21348-0000-A0</td><td>Wafer to wafer</td></tr><tr><td>USB 2.0 dongle</td><td>30-21401-0000-A0</td><td>Wafer to USB type A female</td></tr><tr><td>Audio Mic/Line Out Jack cable</td><td>30-22087-0000-A0</td><td>Wafer to 2x 3.5φ phone Jack</td></tr><tr><td>Power/Reset buttons, LED notification</td><td>30-21350-0000-A0</td><td>Wafer to 2x buttons and 1x LED</td></tr><tr><td>SPI</td><td></td><td>Wafer to open end cables</td></tr><tr><td>Power switch</td><td>30-21429-0020-A0</td><td>Wafer to power switch</td></tr><tr><td>LED cable</td><td>30-22249-0000-A0</td><td>Wafer to LEDs</td></tr><tr><td>GPIO cable</td><td>30-21352-0000-A0</td><td>Wafer to open cables</td></tr><tr><td>I2C cable</td><td>30-21353-0000-A0</td><td>Wafer to open cables</td></tr><tr><td>COM port</td><td>30-21862-0010-A0</td><td>Wafer to 1x DB9</td></tr><tr><td>Buzzer</td><td>23-52111-0A00</td><td>Wafer to 1x buzzer</td></tr><tr><td>Fan</td><td>32-00086-3000-A0</td><td>Wafer to 1x 12V fan</td></tr></table>

Thermal Parts

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>Fan</td><td>32-00086-3000-A0</td><td>Wafer to 1x 12V fan</td></tr><tr><td>Fan with heatsink</td><td>TBD</td><td>1x heatsink, 1x bracket, 1x fan, 4x screws</td></tr></table>

# 2. Block Diagram

![Based on the provided block diagram, here is an accurate and concise description of the labeled blocks and their connections. The central component is the **Intel® Meteor Lake-U/H Processor**.\n\n**Left Side Connections (Inputs/Outputs to Processor):**\n*   **PEG X8 slot**: Connected via 'PCIe X8 Gen4, H series only' to 'PCIe_21-28'.\n*   **LVDS / eDP CN**: Connected to 'eDP to LVDS PTN3460', then '0 ohm Option', then 'DDI', and finally 'DDI_A'.\n*   **DP CN**: Connected to '0 ohm Option', then 'TCP', and finally 'TCP_3'.\n*   **Mini DP CN**: Connected to 'DDI_B'.\n*   **Thunderbolt 5V/3A**: A block containing 'Protector RT1738AGQW', 'Re-timer JHL9040R SRLDH', and 'PD TPS65994BH'.\n    *   Connected via 'TCP' to 'TCP_0'.\n    *   Connected via 'USB2' to 'U2_5'.\n*   **TPM SLB9672**: A block containing 'TPM SLB9672', 'BIOS', 'DB40', '0 ohm Option', and 'Wafer'.\n    *   'TPM SLB9672', 'BIOS', and 'DB40' connect to 'SPI'.\n    *   '0 ohm Option' and 'Wafer' connect to 'GSPI'.\n    *   Both 'SPI' and 'GSPI' connect to 'GP1'.\n*   **RJ45 CN**: Connected to 'I226', then '0 ohm Option', then 'PCIe', and finally 'PCIe_5'.\n*   **RJ45 CN (MDI wafer To PoE)**: Connected to '0 ohm Option', then 'I226', then '0 ohm Option', then 'PCIe', and finally 'PCIe_6'.\n*   **wafer**: Connected to 'RTC' (which connects to the processor bus near 'PCIe_7' and 'PCIe_8').\n\n**Right Side Connections (Inputs/Outputs to Processor):**\n*   **Memory**: 'DDR CH1' and 'DDR CH2' connect to 'DDR5 SO-DIMM'.\n*   **Storage (SATA/M.2)**:\n    *   **SATA_1**: Connects to 'SATA' (also connected to 'PCIe_13-16').\n    *   'SATA' connects to 'Mux TMUXHS4212IRKSR', which connects to 'SATA', then 'PCIe X4', and finally 'M.2 M Key 2280 (PCIEx4/SATA)'.\n    *   **SATA_0**: Connects to 'SATA' and then '2.5' SSD'.\n*   **Expansion Slots**:\n    *   **PCIe_4 / U2_7**: 'PCIe_4' connects to 'PCIe' and 'U2_7' connects to 'USB2'. The 'USB2' line connects to 'M.2 E Key 2230 (Wi-Fi/BT)'.\n    *   **PCIe_3 / U2_6**: 'PCIe_3' connects to 'PCIe' and 'U2_6' connects to 'USB2'. The 'USB2' line connects to 'Mini PCIE Full Slot'.\n*   **Audio**:\n    *   **HDA**: Connects to 'Codec 92HD91B'.\n    *   'Codec' connects to 'SPEAKER' -) 'Wafer' and 'LINE OUT/MIC IN' -) 'Wafer'.\n*   **USB Interfaces**:\n    *   **U3_1 / U3_2**: Connect to 'USB3', then '0 ohm Option', and finally 'Dual USB3.2 typeA'.\n    *   **U2_1 / U2_2**: Connect to 'USB2', then '0 ohm Option', and finally 'Dual USB3.2 typeA'.\n    *   **TCP_1 / TCP_2**: Connect to 'TCP_USB3' and finally 'Dual USB3.2 typeA'.\n    *   **U2_3 / U2_4**: Connect to 'USB2', then '0 ohm Option', and finally 'Dual USB3.2 typeA'.\n    *   **U2_8**: Connects to 'USB2' and then 'CAP touch panel'.\n    *   **U2_9**: Connects to 'USB2' and then 'Wafer for camera module'.\n*   **I2C & GPIO**:\n    *   **I2C**: Connects to 'EEPROM M24C02-FDW6TP 2Kb', 'Wafer for DIO board', and 'Wafer for 2nd I2C'.\n    *   **4DO / 4DI**: Connects to 'Wafer for GPIO'.\n    *   **Wafer for Buzzer**: Connected to the same line as 'Wafer for GPIO'.\n*   **System Controller (SIO/EC)**:\n    *   **eSPI**: Connects to 'SIO NCT5525D'.\n    *   **SIO**: Connects to 'SP339E' -) 'COM1 wafer' and 'SP339E' -) 'COM2 wafer'. Also connects to '80 Port', 'CPU Fan wafer', and '2nd Fan wafer'.\n    *   **EC IT5121VG**: Connects to 'GPIO*32' -) '32 Keypad Wafer', 'SMBus' -) 'UPS', 'PWM*4' -) 'BL/Volume wafer', and 'I2C' -) 'Ambient sensor'.\n    *   **eSPI to LPC F85227N**: Connects to 'LPC' and then 'DB40'.](.sp2-mtl-50m-p1600-1010-11/1b865acef33164f60979a20e2bbe7165db4ca287ead8ba42e1aa03e0834d5e18.jpg)

Figure 1 – Module function diagram

3. Specifications

<table><tr><td>Model</td><td>SP2-10WP-MTL</td><td>SP2-15WP-MTL</td><td>SP2-21WP-MTL</td></tr><tr><td>Processor</td><td>Core Ultra 5 processor 125H, 4.50GHz or Core Ultra 7 processor 155H, 4.80GHz</td><td>Core Ultra 5 processor 125H, 4.50GHz or Core Ultra 7 processor 155H, 4.80GHz</td><td>Core Ultra 5 processor 125H, 4.50GHz or Core Ultra 7 processor 155H, 4.80GHz</td></tr><tr><td>Memory</td><td>2x SODIMM socket, DDR5 5600MHz</td><td>2x SODIMM socket, DDR5 5600MHz</td><td>2x SODIMM socket, DDR5 5600MHz</td></tr><tr><td>Storage</td><td>1x M.2 SATA M key 2280, support SATA SSD and NVME (PCIe x4)1x 2.5" SSD/HDD SATA 6 Gbps port</td><td>1 x M.2 SATA M key 2280, support SATA SSD and NVME (PCIe x4)1x 2.5" SSD/HDD SATA 6 Gbps port</td><td>1x M.2 SATA M key 2280, support SATA SSD and NVME (PCIe x4)1x 2.5" SSD/HDD SATA 6 Gbps port</td></tr><tr><td colspan="4">Display and Touch</td></tr><tr><td>Size</td><td>10.1"</td><td>15.6"</td><td>21.5"</td></tr><tr><td>Resolution</td><td>1280 x 800</td><td>1920 x 1080</td><td>1920 x1080</td></tr><tr><td>Contrast Ratio</td><td>800:1</td><td>1000:1</td><td>1000:1</td></tr><tr><td>Brightness (Nits)</td><td>400 cd/m2 (typ.)</td><td>400 cd/m2 (typ.)</td><td>400 cd/m2 (typ.)</td></tr><tr><td>Backlight Life (hrs.)</td><td>50,000</td><td>50,000</td><td>50,000</td></tr><tr><td>Viewing Angle (U/D/R/L)</td><td>89/89/89/89</td><td>89/89/89/89</td><td>89/89/89/89</td></tr><tr><td>Touch Points</td><td>10 Points</td><td>10 Points</td><td>10 Points</td></tr><tr><td>Touch Structure</td><td>Glass/Glass</td><td>Glass/Glass</td><td>Glass/Glass</td></tr><tr><td>Surface Hardness</td><td>7H</td><td>7H</td><td>7H</td></tr><tr><td>Surface Treatment</td><td>Anti-Fingerprint coating</td><td>Anti-Fingerprint coating</td><td>Anti-Fingerprint coating</td></tr><tr><td colspan="4">External I/O</td></tr><tr><td>Ethernet</td><td>2x GbE (Intel® I226), RJ-45, WOL (optional TSN support)</td><td>2x GbE (Intel® I226), RJ-45, WOL (optional TSN support)</td><td>2x GbE (Intel® I226), RJ-45, WOL (optional TSN support)</td></tr><tr><td>USB Ports</td><td>4x USB 3.2, Gen 2 (10 Gbps), OCP, Type A1x Thunderbolt, Type C (optional)</td><td>4x USB 3.2, Gen 2 (10 Gbps), OCP, Type A1x Thunderbolt, Type C (optional)</td><td>4x USB 3.2, Gen 2 (10 Gbps), OCP, Type A1x Thunderbolt, Type C (optional)</td></tr><tr><td>DisplayPort</td><td>1x DisplayPort, DP++, supports DP 1.4, resolutions up to 5120x3200@60Hz 24bpp1x MiniDisplayPort, DP++, supports DP 1.4, resolutions up to 5120x3200@60Hz 24bpp (BOM optional)</td><td>1x DisplayPort, DP++, supports DP 1.4, resolutions up to 5120x3200@60Hz 24bpp1x MiniDisplayPort, DP++, supports DP 1.4, resolutions up to 5120x3200@60Hz 24bpp (BOM optional)</td><td>1x DisplayPort, DP++, supports DP 1.4, resolutions up to 512Ox3200@60Hz 24bpp1x MiniDisplayPort, DP++, supports DP 1.4, resolutions up to 5120x3200@60Hz 24bpp (BOM optional)</td></tr><tr><td colspan="4">Internal I/O with Wire to Board Connectors</td></tr><tr><td>USB Port</td><td>1x USB 2.0 client, wafer</td><td>1x USB 2.0 client, wafer</td><td>1x USB 2.0 client, wafer</td></tr><tr><td>COM Port</td><td>2x RS-232/422/485 programmable, auto flow (wire to connectors)</td><td>2x RS-232/422/485 programmable, auto flow (wire to connectors)</td><td>2x RS-232/422/485 programmable, auto flow (wire to connectors)</td></tr><tr><td>I2C</td><td>2x for I2C client</td><td>2x for I2C client</td><td>2x for I2C client</td></tr><tr><td>Audio (Optional)</td><td>1x for 2x stereo speaker (2 watts)1x Mic-in and Line-out1x buzzer</td><td>1x for 2x stereo speaker (2 watts)1x Mic-in and Line-out1x buzzer</td><td>1x for 2x stereo speaker (2 watts)1x Mic-in and Line-out1x buzzer</td></tr><tr><td>Keys</td><td>1x for 32 physical keys (BOM optional),1x LCD backlight up/down and volume up/down (BOM optional)</td><td>1x for 32 physical keys (BOM optional),1x LCD backlight up/down and volume up/down (BOM optional)</td><td>1x for 32 physical keys (BOM optional),1x LCD backlight up/down and volume up/down (BOM optional)</td></tr><tr><td>GPIO</td><td>1x 8-pin GPIO</td><td>1x 8-pin GPIO</td><td>1x 8-pin GPIO</td></tr><tr><td>mPCIe</td><td>1x full size mPCIe slot</td><td>1x full size mPCIe slot</td><td>1x full size mPCIe slot</td></tr><tr><td>M.2 2230 slot</td><td>1x M.2 2230 E key for wireless (Wi-Fi/Bluetooth)</td><td>1x M.2 2230 E key for wireless (Wi-Fi/Bluetooth)</td><td>1x M.2 2230 E key for wireless (Wi-Fi/Bluetooth)</td></tr><tr><td>Power/Reset</td><td>1x Power (with LED)1x Reset button</td><td>1x Power (with LED)1x Reset button</td><td>1x Power (with LED)1x Reset button</td></tr><tr><td colspan="4">Power</td></tr><tr><td>Power Input</td><td>AT/ATX (default: AT mode)12V ±5%, (optional: 9-36VDC), both with OVP/UVP protection</td><td>AT/ATX (default: AT mode)12V ±5%, (optional: 9-36VDC), both with OVP/UVP protection</td><td>AT/ATX (default: AT mode)12V ±5%, (optional: 9-36VDC), both with OVP/UVP protection</td></tr><tr><td>Power Connector</td><td>1x 6-pin power connector</td><td>1x 6-pin power connector</td><td>1x 6-pin power connector</td></tr><tr><td>Power/Fail Reset</td><td>1x wafer supports system reset, power button and power LED</td><td>1x wafer supports system reset, power button and power LED</td><td>1x wafer supports system reset, power button and power LED</td></tr><tr><td>Backup Battery</td><td>1x wafer for UPS kit to back up data when AC shuts down (optional)</td><td>1x wafer for UPS kit to back up data when AC shuts down (optional)</td><td>1x wafer for UPS kit to back up data when AC shuts down (optional)</td></tr><tr><td colspan="4">Environmental</td></tr><tr><td>Temperature</td><td>Operating: 0°C to 55°CStorage: -20°C to 70°C</td><td>Operating: 0°C to 55°CStorage: -20°C to 70°C</td><td>Operating: 0°C to 55°CStorage: -20°C to 70°C</td></tr><tr><td>Humidity</td><td>Up to 95%</td><td>Up to 95%</td><td>Up to 95%</td></tr><tr><td>Vibration</td><td>OP 1 Grms, 5-500Hz w/ SSD, (IEC60068-2-64)X, Y, Z axes, 60 min/axis</td><td>OP 1 Grms, 5-500Hz w/ SSD, (IEC60068-2-64)X, Y, Z axes, 60 min/axis</td><td>OP 1 Grms, 5-500Hz w/ SSD, (IEC60068-2-64)X, Y, Z axes, 60 min/axis</td></tr><tr><td>Shock</td><td>OP 20G peak acceleration, 11 ms (IEC60068-2-64)±X, ±Y, ±Z, 3 shocks/axis</td><td>OP 20G peak acceleration, 11 ms (IEC60068-2-64)±X, ±Y, ±Z, 3 shocks/axis</td><td>OP 20G peak acceleration, 11 ms (IEC60068-2-64)±X, ±Y, ±Z, 3 shocks/axis</td></tr><tr><td>IP Rating</td><td>IP65 front panel</td><td>IP65 front panel</td><td>IP65 front panel</td></tr><tr><td>ESD</td><td>Air: ±15kV, Contact: ±8kV</td><td>Air: ±15kV, Contact: ±8kV</td><td>Air: ±15kV, Contact: ±8kV</td></tr><tr><td>EMC Certifications</td><td>CE/FCC class BEN 55032:2015 + A11:2020; EN 55035:2017 +A11:2020;BS EN 55032:2015 + A11:2020; BS EN 55035:2017</td><td>CE/FCC class BEN 55032:2015 + A11:2020; EN 55035:2017 +A11:2020;BS EN 55032:2015 + A11:2020; BS EN 55035:2017</td><td>CE/FCC class BEN 55032:215 + A11:2020; EN 55035:2017 +A11:2020;BS EN 55032:2015 + A11:2020; BS EN 55035:2017</td></tr><tr><td></td><td>+ A11:2020;AS/NZS CISPR 32:2015 + A1:2020EN 60601-1-2:2015 + A1:2021; IEC 60601-1-2:2014 + A1:2020BS EN 60601-1-2:2015 + A1:2021IEC/EN 61000-3-2, IEC/EN 61000-3-3</td><td>+ A11:2020;AS/NZS CISPR 32:2015 + A1:2020EN 60601-1-2:2015 + A1:2021; IEC 60601-1-2:2014 + A1:2020BS EN 60601-1-2:2014 + A1:2021IEC/EN 61000-3-2, IEC/EN 61000-3-3</td><td>+ A11:2020;AS/NZS CISPR 32:2015 + A1:2020EN 60601-1-2:2015 + A1:2021; IEC 61000-1-2:2014 + A1:2020BS EN 60601-1-2:2015 + A1:2021IEC/EN 61000-3-2, IEC/EN 61000-3-3</td></tr><tr><td>EMC/Safety Compliance</td><td>EN 62368-1:2014 + A11:2017</td><td>EN 62368-1:2014 + A11:2017</td><td>EN 62368-1:2014 + A11:2017</td></tr><tr><td colspan="4">Software</td></tr><tr><td>Watchdog Timer</td><td>Supported</td><td>Supported</td><td>Supported</td></tr><tr><td>Operating Systems</td><td>Windows® 11 IoT Enterprise x64 bitWindows® 10 IoT Enterprise x64 bitUbuntu Linux 22.04 LTS</td><td>Windows® 11 IoT Enterprise x64 bitWindows® 10 IoT Enterprise x64 bitUbuntu Linux 22.04 LTS</td><td>Windows® 11 IoT Enterprise x64 bitWindows® 10 IoT Enterprise x64 bitUbuntu Linux 22.04 LTS</td></tr><tr><td colspan="4">Mechanical</td></tr><tr><td>Size</td><td>10.1"</td><td>15.6"</td><td>21.5"</td></tr><tr><td>Construction</td><td>SGCC</td><td>SGCC</td><td>SGCC</td></tr><tr><td>Dimensions (LXWXD)</td><td>249.66 ± 2 x 168.3 ± 2 x 64.4± 2</td><td>383.56 ± 2 x 232.99 ± 2 x 65.1± 2</td><td>517.46 ± 2 x 309.19 ± 2 x 67.6 ± 2</td></tr><tr><td>Package dimension</td><td>420 x 176 x 352</td><td>620x176x440</td><td>620 x 176 x 440</td></tr><tr><td>Mounting (Optional)</td><td>Panel MountingVESA mounting (requires optional rear cover)</td><td>Panel MountingVESA mounting (requires optional rear cover)</td><td>Panel MountingVESA mounting (requires optional rear cover)</td></tr></table>

# 4. Mechanical Layout

All dimensions are in millimeters, unless noted.

# 4.1. Mechanical Dimensions

SP2-10WP-MTL

![237.06\n26.53 180 30.53](.sp2-mtl-50m-p1600-1010-11/c0a3b573c818d37609925038d726a0d29e5362a37289fdc1796e557e67f0fba2.jpg)

![249.66±2(W)\n217.96±0.2(CG VA)\n136.6±0.2(CG VA)\n168.3±2(H)](.sp2-mtl-50m-p1600-1010-11/7f4a9b34952cffac862565522b6c515ad741482e5f79622e65a13575d3896663.jpg)

![64.4±2(D)\n4.51\n19.2\n158.4\n7.3](.sp2-mtl-50m-p1600-1010-11/4189daaba02544b0fcc9bd40ed27ad94b244582bce6ba5c6f1bde02df385135b.jpg)

Figure 2 – SP2-10WP-MTL mechanical dimensions

SP2-15WP-MTL
![The image displays technical engineering drawings of a rectangular device with three orthographic projections, annotated with precise measurements.\n\n**Top View (Front Elevation):**\n*   A top horizontal dimension line reads **370.8**.\n*   Below this, segmented dimensions read **61.4**, **180**, and **129.4**.\n*   An illustration of a circuit board or component strip runs horizontally, with the text **0 0** repeated four times along a lower bar.\n\n**Bottom Left View (Top Plan):**\n*   The outer width dimension reads **383.56±2(W)**.\n*   The inner width dimension reads **345.56±0.2(CG VA)**.\n*   The outer height dimension (vertical text) reads **232.99±2(H)**.\n*   The inner height dimension (vertical text) reads **194.99±0.2(CG VA)**.\n\n**Bottom Right View (Side Elevation):**\n*   The depth dimension reads **65.1±2(D)**.\n*   Smaller horizontal dimensions below read **5.2** and **22.5**.\n*   A vertical dimension on the right reads **20.15**.\n*   The total vertical height dimension on the far right reads **220.6**.\n*   A lower vertical dimension reads **68.55**.](.sp2-mtl-50m-p1600-1010-11/5fb9a9933b4e63b2915bae023bee9583112bbffc39b368f2ed245f1341c7934c.jpg)
Figure 3 – SP2-15WP-MTL mechanical dimensions

# SP2-21WP-MTL

![504.6\n∞](.sp2-mtl-50m-p1600-1010-11/7a65953472c87a65b88c88d729f3840ff630d8116457001cf1f8fcf3ff838ba6.jpg)

![517.46±2(W)\n477.46±0.3(CL VA)\n269.19±0.3(CL VA)\n309.19±2(H)](.sp2-mtl-50m-p1600-1010-11/0481e1f623c83e4fcf5b29d98f507b448328eb43a0648ed7b343cbe507b8cdc8.jpg)

![67.6±2(D)\n5.2\n30.2\n74.3\n296.9\n37.4\n90.68](.sp2-mtl-50m-p1600-1010-11/62b8191358c1688b217ff77f4cb4ed95916caa54fec4a36b232f5f44fcdd0167.jpg)

Figure 4 – SP2-21WP-MTL mechanical dimensions

# 4.2. I/O Panel Connector Locations

# Optional Connectors:

• Mini DP, 32 keys for data input, PCIe x8, MDI for external PoE board, Type C Thunderbolt, and MDI.

![mPCIe Mini DP LVDS SPI Power/Reset\nENG reserved USB\nUSB for touch\n2.5' SATA\nDC connector\nM.2 2230 A/E\nFunction Module\nIntel® Core™ Ultra H series (Meteor Lake)\nDDR5 Memory Slots\nBuzzer Fan Backlight/volume\n32 keys for data input\nPCIe x8\nMDI for external PoE board\nType C Thunderbolt USB DP LAN](.sp2-mtl-50m-p1600-1010-11/0f9c7f0d753c044bfab7cbbfb3dbf07e4a5116c311060bdeb0c93e80bcf6da23.jpg)

Figure 5 – I/O panel connector locations

# 4.3. Mainboard Connector Locations

![DB40\nMIC/LINE OUT\nSpeaker\nLED\nSMBUS\nI²C\nI²C\nCOM\nCOM\nBackup Battery\nGPIO\nM.2 2280 SATA/NVME](.sp2-mtl-50m-p1600-1010-11/6d7acbefb4072ee9711389cd3a00e6dfa8010d27aa61d44c6a9bbf5a6f48c8c4.jpg)

Figure 6 – Mainboard connector locations

# 5. Thermal Options

# 5.1. Heatsink Dimensions

![The image displays a technical 3D rendering of a mechanical component, likely a heat sink or electronic enclosure, presented in four distinct views against a white background:\n\n*   **Top Left:** A front elevation view showing a surface composed of vertical parallel fins. Three circular mounting holes are visible: one centered near the top and two spaced horizontally below it.\n*   **Top Right:** A side elevation view showing the profile of the object, revealing a rectangular block shape with a protruding section on the right side.\n*   **Bottom Left:** A top-down perspective view showing a flat top surface with a central rectangular cutout (filled with a light blue rectangle) surrounded by a recessed border. Three small circular screw heads are visible around this central area, and a row of fins runs along the bottom edge.\n*   **Bottom Right:** An angled perspective view focusing on the finned structure, highlighting the parallel vertical fins and internal structural details visible between them.](.sp2-mtl-50m-p1600-1010-11/47e22f682fe27920f20adea887be77d233fb14a6281f185a5221633618ad05bd.jpg)
Figure 7 – Module function diagram

![The image displays a red icon resembling a document or memo. It features a square outline with a folded bottom-right corner (a 'dog-ear'). Inside the outline, there are two thick, horizontal red lines centered within the shape.](.sp2-mtl-50m-p1600-1010-11/48645adbb523513611d7b444b6e5c6265da7abe57cdf5aba3db336e33b628a85.jpg)

Note: All dimensions are in millimeters, unless noted.

![The image displays a yellow triangular warning sign with a black border. Inside the triangle, centered, is a white exclamation mark.](.sp2-mtl-50m-p1600-1010-11/e7fd848cc053ecbc67049eccb854505834a06268a9dab096c5f143c9c81b1f1d.jpg)

Caution: Due to radiant heat from the passive heatsink, make sure the heatsink is positioned at least 10 cm from the nearest wall.

# 5.2. Active Cooling Heatsink

![The image displays four technical renderings of a heatsink assembly with an integrated fan, arranged in a two-by-two grid:\n\n*   **Top Left:** A top-down orthographic view showing a square cooling fan mounted centrally. The fan is secured by four screws at the corners and is flanked by large, vertical heat sink fins on both sides. Smaller fins are visible above and below the fan assembly.\n*   **Top Right:** A side-profile view illustrating the depth and thickness of the heat sink fins and the fan housing. It shows the mounting hardware attached to the side of the unit.\n*   **Bottom Left:** An isometric view of the bottom or side of the assembly, featuring a flat rectangular plate with a central rectangular cutout and screw holes. Small fins run along the bottom edge.\n*   **Bottom Right:** A 3D isometric view showing the fan mounted between the large vertical heat sink fins, providing a clear perspective of the fins' structure and the fan's position within the housing.](.sp2-mtl-50m-p1600-1010-11/6016ba6c48a981484e4948a4eeae2c6da48008d82829f835a19fea863aa4a6d1.jpg)
Figure 8 – Active cooling heatsink

# 6. Pinouts and Connectors

# 6.1. Power Connector

The 6-pin power connector connects to an AC/DC power supply adapter, a DC-to-DC power, module, and a battery. It supports AT and ATX power modes, with AT mode controlled by the BIOS.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>PWR_CONN_IN</td></tr><tr><td>5</td><td>PWR_CONN_IN</td></tr><tr><td>6</td><td>PWR_CONN_IN</td></tr></table>

<table><tr><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>CP3506P1V00-NH</td><td>20-65D0N-2030</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-mtl-50m-p1600-1010-11/1dd1a9b7ad30ff5fc2d7afe008dedfdcac1ee413d1f0bb1d2b40fb0a7a2e6515.jpg)

# 6.2. SATA Power Connector

The SATA power connector provides power to an internal 2.5” HDD.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>P+5V_S0</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>P+3V3_S0</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1170-05S10-01T-3.4-CS01</td><td>20-6520E-1050</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-mtl-50m-p1600-1010-11/e7181abb845b105ed40f0748c3f99d724e6a44ce38545b7454ef8936010a9c3a.jpg)

# 6.3. SATA Data Connector

The SATA data connector provides data connection to an internal 2.5” HDD.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>SATA_TX1_P</td></tr><tr><td>3</td><td>SATA_TX1_N</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>SATA_RX1_N</td></tr><tr><td>6</td><td>SATA_RX1_P</td></tr><tr><td>7</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>WIN WIN</td><td>WATM-07ABN4B3B8UW4</td><td>21-H14A0-0070</td></tr></table>

![Pure architectural floor plan lines without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/fcdd385cf41188e6dcb1f940891040eb833e20eac9c8d66cc06117d408f3f959.jpg)

# 6.4. Capacitive Touch Connector

The internal USB 2.0 connector supports a capacitive touch for panel.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TSC_D+</td></tr><tr><td>3</td><td>TSC_D-</td></tr><tr><td>4</td><td>P5V_U2TOU</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53398-0471</td><td>61-69J03-1040</td></tr></table>

# 6.5. Mini PCIe Connector

The mini PCIe connector supports standard PCIe signals such as PCIe Gen3 and USB2.0.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>PCIE_Wake-L</td><td>2</td><td>P_+3V3_S0_mPCIe</td></tr><tr><td>3</td><td>TP point</td><td>4</td><td>GND</td></tr><tr><td>5</td><td>TP point</td><td>6</td><td>P_+1V5_S0_mPCIe</td></tr><tr><td>7</td><td>PCH_CLK_REQ3-L</td><td>8</td><td>X</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>X</td></tr><tr><td>11</td><td>MPCIE_CLK3_N</td><td>12</td><td>X</td></tr><tr><td>13</td><td>MPCIE_CLK3_P</td><td>14</td><td>X</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>X</td></tr><tr><td>17</td><td>X</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>X</td><td>20</td><td>TP point</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>PLTRST-L_MINIPCIE</td></tr><tr><td>23</td><td>MPCIE_RX6_N</td><td>24</td><td>P_+3V3_S0_mPCIe</td></tr><tr><td>25</td><td>MPCIE_RX6_P</td><td>26</td><td>GND</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>P_+1V5_S0_mPCIe</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>PCH_SMB_CLK_MINI</td></tr><tr><td>31</td><td>MPCIE_TX6_N_C</td><td>32</td><td>PCH_SMB_DAT_MINI</td></tr><tr><td>33</td><td>MPCIE_TX6_P_C</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>USB_MINIPCIE_N</td></tr><tr><td>37</td><td>GND</td><td>38</td><td>USB_MINIPCIE_P</td></tr><tr><td>39</td><td>P_+3V3_S0_pPCIe</td><td>40</td><td>GND</td></tr><tr><td>41</td><td>P_+3V3_S0_pPCIe</td><td>42</td><td>X</td></tr><tr><td>43</td><td>GND</td><td>44</td><td>TP point</td></tr><tr><td>45</td><td>X</td><td>46</td><td>X</td></tr><tr><td>47</td><td>X</td><td>48</td><td>P_+1V5_S0_mPCIe</td></tr><tr><td>49</td><td>X</td><td>50</td><td>GND</td></tr><tr><td>51</td><td>X</td><td>52</td><td>P_+3V3_S0_mPCIe</td></tr></table>

# 6.6. M.2 2230, E Key for Wi-Fi/Bluetooth Modules

The M.2 E Key supports standard PCIe signals such as PCIe Gen3 and USB2.0.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>P_+3V3_NGFF_E</td><td>75</td><td>GND</td></tr><tr><td>3</td><td>M2E_USB_P</td><td>4</td><td>P_+3V3_NGFF_E</td><td></td><td></td></tr><tr><td>5</td><td>M2E_USB_N</td><td>6</td><td>NC</td><td></td><td></td></tr><tr><td>7</td><td>GND</td><td>8</td><td>NC</td><td></td><td></td></tr><tr><td>9</td><td>NC</td><td>10</td><td>NC</td><td></td><td></td></tr><tr><td>11</td><td>NC</td><td>12</td><td>NC</td><td></td><td></td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td><td></td><td></td></tr><tr><td>15</td><td>NC</td><td>16</td><td>NC</td><td></td><td></td></tr><tr><td>17</td><td>NC</td><td>18</td><td>GND</td><td></td><td></td></tr><tr><td>19</td><td>NC</td><td>20</td><td>NC</td><td></td><td></td></tr><tr><td>21</td><td>NC</td><td>22</td><td>NC</td><td></td><td></td></tr><tr><td>23</td><td>NC</td><td>32</td><td>NC</td><td></td><td></td></tr><tr><td>33</td><td>GND</td><td>34</td><td>NC</td><td></td><td></td></tr><tr><td>35</td><td>PCIE2_M2E_TX_P</td><td>36</td><td>NC</td><td></td><td></td></tr><tr><td>37</td><td>PCIE2_M2E_TX_N</td><td>38</td><td>NC</td><td></td><td></td></tr><tr><td>39</td><td>GND</td><td>40</td><td>NC</td><td></td><td></td></tr><tr><td>41</td><td>PCIE2_RX_P</td><td>42</td><td>NC</td><td></td><td></td></tr><tr><td>43</td><td>PCIE2_RX_N</td><td>44</td><td>NC</td><td></td><td></td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td><td></td><td></td></tr><tr><td>47</td><td>PCIECLK1_100M_P</td><td>48</td><td>NC</td><td></td><td></td></tr><tr><td>49</td><td>PCIECLK1_100M_N</td><td>50</td><td>NC</td><td></td><td></td></tr><tr><td>51</td><td>GND</td><td>52</td><td>M2E_PLTRST_BUF-L</td><td></td><td></td></tr><tr><td>53</td><td>PCH_CLK_REQ1-L</td><td>54</td><td>NC</td><td></td><td></td></tr><tr><td>55</td><td>M2_E_PEWAKE_N</td><td>56</td><td>W_DISABLE1</td><td></td><td></td></tr><tr><td>57</td><td>GND</td><td>58</td><td>PCH_SMB_DAT_A</td><td></td><td></td></tr><tr><td>59</td><td>NC</td><td>60</td><td>PCH_SMB_CLK_A</td><td></td><td></td></tr><tr><td>61</td><td>NC</td><td>62</td><td>GP_C02_SMB_ALERT-</td><td></td><td></td></tr><tr><td>63</td><td>GND</td><td>64</td><td>NC</td><td></td><td></td></tr><tr><td>65</td><td>NC</td><td>66</td><td>NC</td><td></td><td></td></tr><tr><td>67</td><td>NC</td><td>68</td><td>NC</td><td></td><td></td></tr><tr><td>69</td><td>GND</td><td>70</td><td>NC</td><td></td><td></td></tr><tr><td>71</td><td>NC</td><td>72</td><td>P_+3V3_NGFF_E</td><td></td><td></td></tr><tr><td>73</td><td>NC</td><td>74</td><td>P_+3V3_NGFF_E</td><td></td><td></td></tr></table>

![H=4.8\nLOTES](.sp2-mtl-50m-p1600-1010-11/e688e8b839137e977c10adea854c3af887706714b05296649f3203fa7723d29a.jpg)

# 6.7. Function Module Board Connector

The function module allows customized expandability of the device. Contact your ADLINK representative for details.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+12V_A</td><td>2</td><td>P_+12V_A</td></tr><tr><td>3</td><td>P_+12V_A</td><td>4</td><td>P_+12V_A</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>P_+5V_A</td><td>10</td><td>P_+5V_A</td></tr><tr><td>11</td><td>P_+5V_A</td><td>12</td><td>P_+5V_A</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>P_+3V3_A</td><td>18</td><td>P_+3V3_A</td></tr><tr><td>19</td><td>P_+3V3_A</td><td>20</td><td>P_+3V3_A</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>GND</td></tr><tr><td>25</td><td>PCH_SLP_S3-L</td><td>26</td><td>PCH_I2C1_DAT_3V3</td></tr><tr><td>27</td><td>PCH_PCIE_FM_WAKE-L</td><td>28</td><td>PCH_I2C1_CLK_3V3</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>FM_PRESET-L</td></tr><tr><td>31</td><td>SOC_FM_PCIECLK2_P</td><td>32</td><td>PLTRST-L_FM</td></tr><tr><td>33</td><td>SOC_FM_PCIECLK2_N</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>PCH_SMB_ALERT_N_3V3</td></tr><tr><td>37</td><td>SOC_FM_PCIE_RX5_P</td><td>38</td><td>PCH_SMB_DAT_A</td></tr><tr><td>39</td><td>SOC_FM_PCIE_RX5_N</td><td>40</td><td>PCH_SMB_CLK_A</td></tr><tr><td>41</td><td>GND</td><td>42</td><td>GND</td></tr><tr><td>43</td><td>SOC_FM_PCIE_TX5_P</td><td>44</td><td>FM_U3_TX1_P</td></tr><tr><td>45</td><td>SOC_FM_PCIE_TX5_N</td><td>46</td><td>FM_U3_TX1_N</td></tr><tr><td>47</td><td>GND</td><td>48</td><td>GND</td></tr><tr><td>49</td><td>SOC_FM_PCIECLK3_P</td><td>50</td><td>FM_U3_RX1_P</td></tr><tr><td>51</td><td>SOC_FM_PCIECLK3_N</td><td>52</td><td>FM_U3_RX1_N</td></tr><tr><td>53</td><td>GND</td><td>54</td><td>GND</td></tr><tr><td>55</td><td>SOC_FM_PCIE_RX6_P</td><td>56</td><td>FM_U2_P1_P</td></tr><tr><td>57</td><td>SOC_FM_PCIE_RX6_N</td><td>58</td><td>FM_U2_P1_N</td></tr><tr><td>59</td><td>GND</td><td>60</td><td>GND</td></tr><tr><td>61</td><td>SOC_FM_PCIE_TX6_P</td><td>62</td><td>FM_U3_TX2_P</td></tr><tr><td>63</td><td>SOC_FM_PCIE_TX6_N</td><td>64</td><td>FM_U3_TX2_N</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr></table>

![Pure technical line drawing of a mechanical component with no text or symbols](.sp2-mtl-50m-p1600-1010-11/931c56c72ad0014efd1a4c4ef7a3244d880234ca58dbcdddb20cc33f9876b4fb.jpg)

<table><tr><td>67</td><td>SOC_FM_PCIECLK4_P</td><td>68</td><td>FM_U3_RX2_P</td></tr><tr><td>69</td><td>SOC_FM_PCIECLK4_N</td><td>70</td><td>FM_U3_RX2_N</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>GND</td></tr><tr><td>73</td><td>SOC_FM_PCIE_RX7_P</td><td>74</td><td>FM_U2_P2_P</td></tr><tr><td>75</td><td>SOC_FM_PCIE_RX7_N</td><td>76</td><td>FM_U2_P2_N</td></tr><tr><td>77</td><td>GND</td><td>78</td><td>GND</td></tr><tr><td>79</td><td>SOC_FM_PCIE_TX7_P</td><td>80</td><td>FM_U2_P3_P</td></tr><tr><td>81</td><td>SOC_FM_PCIE_TX7_N</td><td>82</td><td>FM_U2_P3_N</td></tr><tr><td>83</td><td>GND</td><td>84</td><td>GND</td></tr><tr><td>85</td><td>SOC_FM_PCIECLK5_P</td><td>86</td><td>FM_U2_P4_P</td></tr><tr><td>87</td><td>SOC_FM_PCIECLK5_N</td><td>88</td><td>FM_U2_P4_N</td></tr><tr><td>89</td><td>GND</td><td>90</td><td>GND</td></tr><tr><td>91</td><td>SOC_FM_PCIE_RX8_P</td><td>92</td><td>FM_ESPI_LPC_0</td></tr><tr><td>93</td><td>SOC_FM_PCIE_RX8_N</td><td>94</td><td>FM_ESPI_LPC_1</td></tr><tr><td>95</td><td>GND</td><td>96</td><td>FM_ESPI_LPC_2</td></tr><tr><td>97</td><td>SOC_FM_PCIE_TX8_P</td><td>98</td><td>FM_ESPI_LPC_3</td></tr><tr><td>99</td><td>SOC_FM_PCIE_TX8_N</td><td>100</td><td>FM_ESPI_CS1_LPC_FRAME-L</td></tr><tr><td>101</td><td>GND</td><td>102</td><td>FM_ESPI_CLK_LPC_CLK</td></tr><tr><td>103</td><td>PCH_CLK_REQ_P4_N_3V3</td><td>104</td><td>FM_ESPI_ALERT1-L_LPC_SERIRQ</td></tr><tr><td>105</td><td>PCH_CLK_REQ_P5_N_3V3</td><td>106</td><td>FM_ESPI_RESET-L_LPC_DRQ</td></tr><tr><td>107</td><td>GND</td><td>108</td><td>GND</td></tr><tr><td>109</td><td>FM_TCP2_TX0_P</td><td>110</td><td>I2S1_TXD_TCP2_LSK_TXD</td></tr><tr><td>111</td><td>FM_TCP2_TX0_N</td><td>112</td><td>I2S1_RXD_TCP2_LSK_RXD</td></tr><tr><td>113</td><td>GND</td><td>114</td><td>I2S1_SFRM</td></tr><tr><td>115</td><td>FM_TCP2_TX1_P</td><td>116</td><td>I2S1_SCLK_PCH_SML0_DAT</td></tr><tr><td>117</td><td>FM_TCP2_TX1_N</td><td>118</td><td>I2S1_MCLK_PCH_SML0_CLK</td></tr><tr><td>119</td><td>GND</td><td>120</td><td>GND</td></tr><tr><td>121</td><td>FM_TCP2_TX2_P</td><td>122</td><td>USB_OC1_N</td></tr><tr><td>123</td><td>FM_TCP2_TX2_N</td><td>124</td><td>USB_OC3_N</td></tr><tr><td>125</td><td>GND</td><td>126</td><td>GND</td></tr><tr><td>127</td><td>FM_TCP2_TX3_P</td><td>128</td><td>FM_GPIO0</td></tr><tr><td>129</td><td>FM_TCP2_TX3_N</td><td>130</td><td>FM_GPIO1</td></tr><tr><td>131</td><td>GND</td><td>132</td><td>FM_GPIO2</td></tr><tr><td>133</td><td>FM_TCP2_I2CCLK_AUX_P_CN</td><td>134</td><td>GPIO3_SPICS1_MUX</td></tr><tr><td>135</td><td>FM_TCP2_I2CDAT_AUX_N_CN</td><td>136</td><td>GPIO4_FIN_IN_MUX</td></tr><tr><td>137</td><td>GND</td><td>138</td><td>GPIO3_FIN_OUT_MUX</td></tr><tr><td>139</td><td>FM_TCP2_DDC_AUX_SEL_CN</td><td>140</td><td>FM_SPI_MISO</td></tr><tr><td>141</td><td>FM_TCP2_DDI1_HPD</td><td>142</td><td>FM_SPI_MOSI</td></tr><tr><td>143</td><td>GND</td><td>144</td><td>FM_SPI_CS#</td></tr><tr><td>145</td><td>PCH_I2C2_DAT_3V3</td><td>146</td><td>FM_SPI_CLK</td></tr><tr><td>147</td><td>PCH_I2C2_CLK_3V3</td><td>148</td><td>GND</td></tr><tr><td>149</td><td>FM_I2C2_INT_3V3</td><td>150</td><td>UART_SOC_RI_N</td></tr></table>

# 6.8. LVDS/e-DP Connector

The LVDS/eDP allows internal connection to a display. LVDS/eDP settings are controlled by BOM optional.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>BLWR_12V_5V_CN</td><td>24</td><td>GND</td><td>47</td><td>LVDS_B1N_1</td></tr><tr><td>2</td><td>BLWR_12V_5V_CN</td><td>25</td><td>LVDS_ACKP_1</td><td>48</td><td>GND</td></tr><tr><td>3</td><td>BLWR_12V_5V_CN</td><td>26</td><td>LVDS_ACKN_1</td><td>49</td><td>LVDS_B0P_1</td></tr><tr><td>4</td><td>BLWR_12V_5V_CN</td><td>27</td><td>GND</td><td>50</td><td>LVDS_B0N_1</td></tr><tr><td>5</td><td>CN_LVDS_BKLT_PWM</td><td>28</td><td>LVDS_A2P_1</td><td>51</td><td>GND</td></tr><tr><td>6</td><td>CN2_LVDS_BKLT_EN</td><td>29</td><td>LVDS_A2N_1</td><td></td><td></td></tr><tr><td>7</td><td>GND</td><td>30</td><td>GND</td><td></td><td></td></tr><tr><td>8</td><td>GND</td><td>31</td><td>LVDS_A1P_1</td><td></td><td></td></tr><tr><td>9</td><td>GND</td><td>32</td><td>LVDS_A1N_1</td><td></td><td></td></tr><tr><td>10</td><td>GND</td><td>33</td><td>GND</td><td></td><td></td></tr><tr><td>11</td><td>LCD_V_DET_eDP</td><td>34</td><td>LVDS_A0P_1</td><td></td><td></td></tr><tr><td>12</td><td>G_EDP_HPDA</td><td>35</td><td>LVDS_A0N_1</td><td></td><td></td></tr><tr><td>13</td><td>LCD_SEL68_CN</td><td>36</td><td>GND</td><td></td><td></td></tr><tr><td>14</td><td>G_LVDS_I2C_CLK_CN</td><td>37</td><td>LVDS_B3P_1</td><td></td><td></td></tr><tr><td>15</td><td>G_LVDS_I2C_DAT_CN</td><td>38</td><td>LVDS_B3N_1</td><td></td><td></td></tr><tr><td>16</td><td>LCD_LVDS_12V</td><td>39</td><td>GND</td><td></td><td></td></tr><tr><td>17</td><td>LCD_LVDS_12V</td><td>40</td><td>LVDS_BCKP_1</td><td></td><td></td></tr><tr><td>18</td><td>GND</td><td>41</td><td>LVDS_BCKN_1</td><td></td><td></td></tr><tr><td>19</td><td>LCD_LVDS_3V3-5V</td><td>42</td><td>GND</td><td></td><td></td></tr><tr><td>20</td><td>LCD_LVDS_3V3-5V</td><td>43</td><td>LVDS_B2P_1</td><td></td><td></td></tr><tr><td>21</td><td>GND</td><td>44</td><td>LVDS_B2N_1</td><td></td><td></td></tr><tr><td>22</td><td>LVDS_A3P_1</td><td>45</td><td>GND</td><td></td><td></td></tr><tr><td>23</td><td>LVDS_A3N_1</td><td>46</td><td>LVDS_B1P_1</td><td></td><td></td></tr></table>

![Technical line drawing of an electronic component with pins and connectors (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/ec8fa4716a74b8952ce8cbadceb9921da6e1d39224adb8400e1f625ad0fb5bf9.jpg)

# 6.9. Mini DP Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>11</td><td>CON_DDIB_TX1_N</td></tr><tr><td>2</td><td>CON_DDIB_HPD</td><td>12</td><td>CON_DDIB_TX3_N</td></tr><tr><td>3</td><td>CON_DDIB_TX0_P</td><td>13</td><td>GND</td></tr><tr><td>4</td><td>CON_DDIB_DDC_AUX_SEL</td><td>14</td><td>GND</td></tr><tr><td>5</td><td>CON_DDIB_TX0_N</td><td>15</td><td>CON_DDIB_TX2_P</td></tr><tr><td>6</td><td>GND</td><td>16</td><td>CON_DDIB_I2CCLK_AUX_P</td></tr><tr><td>7</td><td>GND</td><td>17</td><td>CON_DDIB_TX2_N</td></tr><tr><td>8</td><td>GND</td><td>18</td><td>CON_DDIB_I2CCLK_AUX_N</td></tr><tr><td>9</td><td>CON_DDIB_TX1_P</td><td>19</td><td>GND</td></tr><tr><td>10</td><td>CON_DDIB_TX3_P</td><td>20</td><td>P_+3V3_MDP</td></tr></table>

![Technical line drawing of an electronic component housing (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/21333de1999d23be8c56838be0ae1ac7c368f829ee4b257b0a3b98945e2806d4.jpg)

# 6.10. Internal USB2.0 Wafer

This internal USB 2.0 connector facilitates connection of a camera to the device.

\*Manufacturer details TBD

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P5V_U2_CAM</td></tr><tr><td>2</td><td>CN_U2_P9_N</td></tr><tr><td>3</td><td>CN_U2_P9_P</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>NC</td></tr><tr><td>6</td><td>NC</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>CST</td><td>CSI-1181-061R-NH</td><td>61-65520-1060</td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-mtl-50m-p1600-1010-11/fed82eb7fa19fc6b84bee15e083fe20aa142cdcd4c0d7a08af819f3d28675eec.jpg)

# 6.11. GSPI Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GSPI_TOUCH_INT-L_3V3</td></tr><tr><td>2</td><td>PCH_GSPI1_MISO_3V3</td></tr><tr><td>3</td><td>PCH_GSPI1_MOSI_3V3</td></tr><tr><td>4</td><td>PCH_GSPI1_CSO-L_3V3</td></tr><tr><td>5</td><td>PCH_GSPI1_CLK_3V3</td></tr><tr><td>6</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>CST</td><td>CSI-1181-061R-NH</td><td>61-65520-1060</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/32cbbe0d53169ca944258e18a5e60e0517f25080b6ab816a871f63a24c617201.jpg)

# 6.12. PWR/RST Wafer

Connects to power, reset button, and power LED via cable.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_A</td></tr><tr><td>2</td><td>PWRBTN-L_R</td></tr><tr><td>3</td><td>SYS_RESET-L_R</td></tr><tr><td>4</td><td>SIG_PWRLED-L</td></tr><tr><td>5</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53398-0571</td><td>61-69J03-0050</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/c20f5a2af6d7d31d81a765f62b8c02dbeaaf60fc586e7e2a7128571603719132.jpg)

# 6.13. Buzzer Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_S0</td></tr><tr><td>2</td><td>A_SPKR_1V8</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-02M00-01T-1-CF01</td><td>61-6AJ0X-1020</td></tr></table>

![Pure mechanical component outline diagram without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/50558b0c561ff1d89decb78721e3a0e019ac9998ffaead5cb9c3c09352592c79.jpg)

# 6.14. MXM Fan Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>FAN_PWR_IN2 (12V)</td></tr><tr><td>3</td><td>SIO_FANIN2_CN</td></tr><tr><td>4</td><td>SIO_PWM_DAC2_CN</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53398-0471</td><td>61-69J03-1040</td></tr></table>

![This image displays a black-and-white line drawing of a 3D object, resembling a technical schematic of an electronic connector.\n\n**Central Structure:**\nThe main body is a long, vertical rectangular prism. Inside this central block, there are four small, horizontal rectangular shapes arranged in a vertical column.\n\n**Side and Top/Bottom Features:**\n- To the left of the central block, there is a column of four smaller, rectangular protrusions stacked vertically.\n- Above and below the central block, there are larger, irregular rectangular shapes that appear to be housing or mounting tabs extending outwards.\n\n**Text/Label:**\nNear the bottom left corner, below the column of four protruding rectangles, there is a small triangle pointing to the right followed by the letter 'D'.](.sp2-mtl-50m-p1600-1010-11/23187aad93e363ff1709dad9b6a44f049e40284fbf62b3381b4738beb651933c.jpg)

# 6.15. Volume/Backlight Wafer

Controls volume and adjusts display brightness.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_S0</td></tr><tr><td>2</td><td>EC_BTN_33</td></tr><tr><td>3</td><td>EC_BTN_34</td></tr><tr><td>4</td><td>EC_BTN_35</td></tr><tr><td>5</td><td>EC_BTN_36</td></tr><tr><td>6</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-06S10-01T-0.5-CF01</td><td>61-69J0X-1060</td></tr></table>

![Pure architectural floor plan lines without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/f894347516981081250e4786a32950390793c93e4b4420e75a8cd8fb8da401b2.jpg)

# 6.16. 33 Keypad Wafer

The key connector supports 32 physical keys and 5 control keys with the following default values:

Directions: $\uparrow , \downarrow , \left. , \right.$
• Numbers: 0 to 9
• Functions: Enter, ESC, TAB, Backspace, Delete, Clear, Page Up, Page Dwn
• Hot keys: F1 – F10

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>HIROSE</td><td>DF20EF-40DP-1V(52)</td><td>61-61002-2200</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Function Value</td><td>Pin</td><td>Signal</td><td>Function Value</td></tr><tr><td>1</td><td>GND</td><td>N/A</td><td>2</td><td>P_+3V3_S0</td><td>N/A</td></tr><tr><td>3</td><td>EC_BTN_17</td><td>Tab</td><td>4</td><td>EC_BTN_1</td><td>↑</td></tr><tr><td>5</td><td>EC_BTN_18</td><td>Backspace</td><td>6</td><td>EC_BTN_2</td><td>↓</td></tr><tr><td>7</td><td>EC_BTN_19</td><td>Delete</td><td>8</td><td>EC_BTN_3</td><td>→</td></tr><tr><td>9</td><td>EC_BTN_20</td><td>Space</td><td>10</td><td>EC_BTN_4</td><td>←</td></tr><tr><td>11</td><td>EC_BTN_21</td><td>Page Up</td><td>12</td><td>EC_BTN_5</td><td>0</td></tr><tr><td>13</td><td>EC_BTN_22</td><td>Page Down</td><td>14</td><td>EC_BTN_6</td><td>1</td></tr><tr><td>15</td><td>EC_BTN_23</td><td>F1</td><td>16</td><td>EC_BTN_7</td><td>2</td></tr><tr><td>17</td><td>EC_BTN_24</td><td>F2</td><td>18</td><td>EC_BTN_8</td><td>3</td></tr><tr><td>19</td><td>EC_BTN_25</td><td>F3</td><td>20</td><td>EC_BTN_9</td><td>4</td></tr><tr><td>21</td><td>EC_BTN_26</td><td>F4</td><td>22</td><td>EC_BTN_10</td><td>5</td></tr><tr><td>23</td><td>EC_BTN_27</td><td>F5</td><td>24</td><td>EC_BTN_11</td><td>6</td></tr><tr><td>25</td><td>EC_BTN_28</td><td>F6</td><td>26</td><td>EC_BTN_12</td><td>7</td></tr><tr><td>27</td><td>EC_BTN_29</td><td>F7</td><td>28</td><td>EC_BTN_13</td><td>8</td></tr><tr><td>29</td><td>EC_BTN_30</td><td>F8</td><td>30</td><td>EC_BTN_14</td><td>9</td></tr><tr><td>31</td><td>EC_BTN_31</td><td>F9</td><td>32</td><td>EC_BTN_15</td><td>Enter</td></tr><tr><td>33</td><td>EC_BTN_32</td><td>F10</td><td>34</td><td>EC_BTN_16</td><td>Esc</td></tr><tr><td>35</td><td>EC_BTN_37</td><td></td><td>36</td><td>NC</td><td></td></tr><tr><td>37</td><td>NC</td><td></td><td>38</td><td>P_+3V3_A</td><td></td></tr><tr><td>39</td><td>NC</td><td></td><td>40</td><td>P_+3V3_A</td><td></td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-mtl-50m-p1600-1010-11/132e9d3b1cd425ed49ac07b3c15962a24c96853ed616cda424e45f29e702705f.jpg)

6.17. PCIE X8 Gen4 Slot

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>A1</td><td>GF_PRSNT1-L</td><td>B1</td><td>P_+12V_S0</td></tr><tr><td>A2</td><td>P_+12V_S0</td><td>B2</td><td>P_+12V_S0</td></tr><tr><td>A3</td><td>P_+12V_S0</td><td>B3</td><td>P_+12V_S0</td></tr><tr><td>A4</td><td>GND</td><td>B4</td><td>GND</td></tr><tr><td>A5</td><td>EC_PWM_FAN</td><td>B5</td><td>PCH_SMB_CLK_3V3</td></tr><tr><td>A6</td><td>EC_TAC_FAN</td><td>B6</td><td>PCH_SMB_DAT_3V3</td></tr><tr><td>A7</td><td>PCH_SLP_S3_N_3V3</td><td>B7</td><td>GND</td></tr><tr><td>A8</td><td>PCH_I2C4_DAT_3V3</td><td>B8</td><td>P_+3V3_S0</td></tr><tr><td>A9</td><td>P_+3V3_S0</td><td>B9</td><td>PCH_I2C4_CLK_3V3</td></tr><tr><td>A10</td><td>P_+3V3_S0</td><td>B10</td><td>P_+3V3_A</td></tr><tr><td>A11</td><td>PCIEX8GF_PERST-L</td><td>B11</td><td>PCIE_X8_WAKE-L</td></tr><tr><td>A12</td><td>GND</td><td>B12</td><td>NC</td></tr><tr><td>A13</td><td>C_REFCLK_P6_100M_P</td><td>B13</td><td>GND</td></tr><tr><td>A14</td><td>C_REFCLK_P6_100M_N</td><td>B14</td><td>PCIE21_TX_P_C</td></tr><tr><td>A15</td><td>GND</td><td>B15</td><td>PCIE21_TX_N_C</td></tr><tr><td>A16</td><td>PCIE21_RX_P_C</td><td>B16</td><td>GND</td></tr><tr><td>A17</td><td>PCIE21_RX_N_C</td><td>B17</td><td>GF_PRSNT2-L</td></tr><tr><td>A18</td><td>GND</td><td>B18</td><td>GND</td></tr><tr><td>A19</td><td>NC</td><td>B19</td><td>PCIE22_TX_P_C</td></tr><tr><td>A20</td><td>GND</td><td>B20</td><td>PCIE22_TX_N_C</td></tr><tr><td>A21</td><td>PCIE22_RX_P_C</td><td>B21</td><td>GND</td></tr><tr><td>A22</td><td>PCIE22_RX_N_C</td><td>B22</td><td>GND</td></tr><tr><td>A23</td><td>GND</td><td>B23</td><td>PCIE23_TX_P_C</td></tr><tr><td>A24</td><td>GND</td><td>B24</td><td>PCIE23_TX_N_C</td></tr><tr><td>A25</td><td>PCIE23_RX_P_C</td><td>B25</td><td>GND</td></tr><tr><td>A26</td><td>PCIE23_RX_N_C</td><td>B26</td><td>GND</td></tr><tr><td>A27</td><td>GND</td><td>B27</td><td>PCIE24_TX_P_C</td></tr><tr><td>A28</td><td>GND</td><td>B28</td><td>PCIE24_TX_N_C</td></tr><tr><td>A29</td><td>PCIE24_RX_P_C</td><td>B29</td><td>GND</td></tr><tr><td>A30</td><td>PCIE24_RX_N_C</td><td>B30</td><td>NC</td></tr><tr><td>A31</td><td>GND</td><td>B31</td><td>GF_PRSNT2-L</td></tr><tr><td>A32</td><td>PCIEX8_GPIO0_3V3</td><td>B32</td><td>GND</td></tr><tr><td>A33</td><td>PCIEX8_GPIO1_3V3</td><td>B33</td><td>PCIE25_TX_P_C</td></tr><tr><td>A34</td><td>GND</td><td>B34</td><td>PCIE25_TX_N_C</td></tr></table>

![H=4.8\nM\nLOTES](.sp2-mtl-50m-p1600-1010-11/0d541161daf5b7921031fcc4f4c9a6e01c40e4a388752435c3d62b6135de025a.jpg)

<table><tr><td>A35</td><td>PCIE25_RX_P_C</td><td>B35</td><td>GND</td></tr><tr><td>A36</td><td>PCIE25_RX_N_C</td><td>B36</td><td>GND</td></tr><tr><td>A37</td><td>GND</td><td>B37</td><td>PCIE26_TX_P_C</td></tr><tr><td>A38</td><td>GND</td><td>B38</td><td>PCIE26_TX_N_C</td></tr><tr><td>A39</td><td>PCIE26_RX_P_C</td><td>B39</td><td>GND</td></tr><tr><td>A40</td><td>PCIE26_RX_N_C</td><td>B40</td><td>GND</td></tr><tr><td>A41</td><td>GND</td><td>B41</td><td>PCIE27_TX_P_C</td></tr><tr><td>A42</td><td>GND</td><td>B42</td><td>PCIE27_TX_N_C</td></tr><tr><td>A43</td><td>PCIE27_RX_P_C</td><td>B43</td><td>GND</td></tr><tr><td>A44</td><td>PCIE27_RX_N_C</td><td>B44</td><td>GND</td></tr><tr><td>A45</td><td>GND</td><td>B45</td><td>PCIE28_TX_P_C</td></tr><tr><td>A46</td><td>GND</td><td>B46</td><td>PCIE28_TX_N_C</td></tr><tr><td>A47</td><td>PCIE28_RX_P_C</td><td>B47</td><td>GND</td></tr><tr><td>A48</td><td>PCIE28_RX_N_C</td><td>B48</td><td>GF_PRSNT2-L</td></tr><tr><td>A49</td><td>GND</td><td>B49</td><td>GND</td></tr></table>

# 6.18. CPU Fan Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>FAN_PWR_IN (12V)</td></tr><tr><td>3</td><td>SIO_FANIN1_CN</td></tr><tr><td>4</td><td>SIO_PWM_DAC1_CN</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53398-0471</td><td>61-69J03-1040</td></tr></table>

![Pure architectural floor plan lines without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/db651c018dfd4bd5ad01a1526095036423b6220731708a2cd59ffbbf3b669c2d.jpg)

# 6.19. LAN2 PD Wafer

Supports an additional GbE LAN port via cable/dongle to RJ45 connector.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>L_GBE2_MDI2_P_PD</td><td>2</td><td>L_GBE2_MDI0_P_PD</td></tr><tr><td>3</td><td>L_GBE2_MDI2_N_PD</td><td>4</td><td>L_GBE2_MDI0_N_PD</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>L_GBE2_MDI3_P_PD</td><td>8</td><td>L_GBE2_MDI1_P_PD</td></tr><tr><td>9</td><td>L_GBE2_MDI3_N_PD</td><td>10</td><td>L_GBE2_MDI1_N_PD</td></tr><tr><td>11</td><td>GND</td><td>12</td><td>GND</td></tr><tr><td>13</td><td>P_+3V3+I226_B</td><td>14</td><td>P_+3V3+I226_B</td></tr><tr><td>15</td><td>L_GBE2_LED0_1000-L</td><td>16</td><td>L_GBE2_LED1_LINK/ACT-L</td></tr><tr><td>17</td><td>NC</td><td>18</td><td>NC</td></tr><tr><td>19</td><td>GND</td><td>20</td><td>GND</td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-mtl-50m-p1600-1010-11/c38db239e9dccac72bf21c959ca9233890f633e78232a6473fd9b5b2f10db945.jpg)

# 6.20. Line Out/Mic In Wafer

Supports Mic in/line out, connecting to peripherals via cable.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CON_MIC1_IN</td></tr><tr><td>2</td><td>CON_LINE1_OUT_L</td></tr><tr><td>3</td><td>CON_LINE1_OUT_R</td></tr><tr><td>4</td><td>LINE1_OUT_JD</td></tr><tr><td>5</td><td>AGND_AUDIO</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-05M00-01T-1-CF01</td><td>61-6AJ0X-1050</td></tr></table>

![Technical line drawing of an electronic component with multiple pins (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/d21a8cb935aac1cb026d01f8949f63a7d74113bfb6760fefda77302aa755435f.jpg)

# 6.21. Speaker Wafer

Supports 2x 2-watt speakers.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>AMP_L</td></tr><tr><td>2</td><td>AMP_L</td></tr><tr><td>3</td><td>AMP_R</td></tr><tr><td>4</td><td>AMP_R</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-04M00-01T-1-CF01</td><td>61-6AJ0X-1040</td></tr></table>

![Pure electrical component outline diagram without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/7e1a83a3cc05e251bca889f3574146399d37413e04e5a122fe4357f2c1c91983.jpg)

# 6.22. LED Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>STDBY_PWR</td></tr><tr><td>3</td><td>GP3_LED-L</td></tr><tr><td>4</td><td>GP2_LED-L</td></tr><tr><td>5</td><td>GP1_LED-L</td></tr><tr><td>6</td><td>P_+3V3_A</td></tr><tr><td>7</td><td>BIOS_LOAD_DEFAULT_L</td></tr><tr><td>8</td><td>GND</td></tr><tr><td>9</td><td>NC</td></tr><tr><td>10</td><td>NC</td></tr><tr><td>11</td><td>CN_SATA_LED-L_R</td></tr><tr><td>12</td><td>P_+3V3_S0</td></tr><tr><td>13</td><td>CN_WDT_LED-L</td></tr><tr><td>14</td><td>P_+3V3_A</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>CST</td><td>CSI-1182-141R</td><td>61-66500-1140</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-mtl-50m-p1600-1010-11/fcd36be23c14a0cb9a693f266f49ef07c03d21928f3b32fbda41649f29495bcc.jpg)

# 6.23. EC Smbus Wafer for UPS

The Uninterruptible Power Supply connector allows the device to interface with a UPS device for backup power in the event of power failure.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CHG_PWR</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>CHG_SMBCLK</td></tr><tr><td>4</td><td>CHG_SMBDAT</td></tr><tr><td>5</td><td>SMB_ALERT-L_R</td></tr><tr><td>6</td><td>DCIN_DET</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-06M00-01T-1-CF01</td><td>61-6AJ0X-1060</td></tr></table>

![The image displays a black and white technical line drawing of a vertical component. It features a central rectangular body connected to top and bottom sections that have horizontal lines. Inside the central body, the left side shows three horizontal lines, each with a small notch. The right side of the central body contains a grid of eight small squares arranged in two columns of four rows.](.sp2-mtl-50m-p1600-1010-11/a2071b83644c63ca06acd8f6db291b4ae2cb93b6cbb3a8fe06d2ca049e96a956.jpg)

# 6.24. SoC 1st I2C Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_I2C</td></tr><tr><td>2</td><td>P_+3V3_I2C</td></tr><tr><td>3</td><td>PCH_I2C4_DAT_3V3</td></tr><tr><td>4</td><td>PCHI_2C4_CLK_3V3</td></tr><tr><td>5</td><td>DIO_I2C4_INT_3V3</td></tr><tr><td>6</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-06M00-01T-1-CF01</td><td>61-6AJ0X-1060</td></tr></table>

![A black and white line drawing of a connector. The left side consists of a top rectangular section with three horizontal slots, a central vertical channel with three curved cutouts, and a bottom rectangular section with three horizontal slots. The right side consists of a rectangular block containing six vertical slots. Small square notches are located on the outer corners of the assembly.](.sp2-mtl-50m-p1600-1010-11/9f7d3385b09e5a2abda11f89c7cbe7d2d279075aa6f7effc063c1570bb5c8e9a.jpg)

# 6.25. SoC ${ \pmb { 2 } } ^ { \mathsf { n d } }$ I2C Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_I2C2</td></tr><tr><td>2</td><td>P_+3V3_I2C2</td></tr><tr><td>3</td><td> $2^{ND}$ _SDA</td></tr><tr><td>4</td><td>2ND_SCL</td></tr><tr><td>5</td><td>2ND_INT</td></tr><tr><td>6</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-06M00-01T-1-CF01</td><td>61-6AJ0X-1060</td></tr></table>

![The image displays a vertical technical line drawing of a mechanical component, resembling a connector housing.\n\n*   **Top and Bottom Sections:** The very top and very bottom of the drawing feature identical rectangular blocks, each crossed by three horizontal lines.\n*   **Upper Central Section:**\n    *   **Right Side:** Four small, rectangular protrusions are arranged vertically along the right edge.\n    *   **Left Side:** A vertical slot or recess contains three arrowheads pointing downwards.\n*   **Lower Central Section:**\n    *   **Right Side:** Four small, rectangular protrusions are arranged vertically along the right edge, mirroring the section above.\n    *   **Left Side:** A smaller rectangular recess contains two small triangles pointing to the left.](.sp2-mtl-50m-p1600-1010-11/db7c2c31c8ad0db3551ed950ed765493920127b2a1fe73912f669c2addaf0eb3.jpg)

6.26. COM Port 1 Wafer

<table><tr><td>Pin</td><td>Signal</td><td>RS232</td><td>RS422</td><td>RS485</td></tr><tr><td>1</td><td>COM1_DCD-L_CN</td><td>DCD#</td><td>TXD422</td><td>485DATA</td></tr><tr><td>2</td><td>COM1_RXD_CN</td><td>RXD</td><td>TXD422</td><td>485DATA</td></tr><tr><td>3</td><td>COM1_TXD_CN</td><td>TXD</td><td>RXD422</td><td>NC</td></tr><tr><td>4</td><td>COM1_DTR-L_CN</td><td>DTR#</td><td>RXD422</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td></tr><tr><td>6</td><td>COM1_DSR-L_CN</td><td>DSR#</td><td>NC</td><td>NC</td></tr><tr><td>7</td><td>COM1_RTS-L_CN</td><td>RTS#</td><td>NC</td><td>NC</td></tr><tr><td>8</td><td>COM1_CTS-L_CN</td><td>CTS#</td><td>NC</td><td>NC</td></tr><tr><td>9</td><td>COM1_RI-L_CN</td><td>RI#</td><td>NC</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53261-1071</td><td>61-6AJ03-1100</td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-mtl-50m-p1600-1010-11/1cb20787f78e52deb22bc92305b1c4994cc5a058494aae1462e82a7eb5cda8ac.jpg)

6.27. COM Port 2 Wafer

<table><tr><td>Pin</td><td>Signal</td><td>RS232</td><td>RS422</td><td>RS485</td></tr><tr><td>1</td><td>COM2_DCD-L_CN</td><td>DCD#</td><td>TXD422</td><td>485DATA</td></tr><tr><td>2</td><td>COM2_RXD_CN</td><td>RXD</td><td>TXD422</td><td>485DATA</td></tr><tr><td>3</td><td>COM2_TXD_CN</td><td>TXD</td><td>RXD422</td><td>NC</td></tr><tr><td>4</td><td>COM1_DTR-L_CN</td><td>DTR#</td><td>RXD422</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td></tr><tr><td>6</td><td>COM2_DSR-L_CN</td><td>DSR#</td><td>NC</td><td>NC</td></tr><tr><td>7</td><td>COM2_RTS-L_CN</td><td>RTS#</td><td>NC</td><td>NC</td></tr><tr><td>8</td><td>COM2_CTS-L_CN</td><td>CTS#</td><td>NC</td><td>NC</td></tr><tr><td>9</td><td>COM2_RI-L_CN</td><td>RI#</td><td>NC</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53261-1071</td><td>61-6AJ03-1100</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-mtl-50m-p1600-1010-11/64b5cb8c53ba45a9c5bcbd52514a33d7f82e39d4da5edd60be51f91bc526c8dc.jpg)

# 6.28. RTC Battery Wafer

The Real Time Clock battery connector allows connection of a backup battery to sustain the system clock in the event of a power

outage.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+VCC_RTC_CN_A</td></tr><tr><td>2</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>JVE</td><td>24W1125A-02M00-01T-1-CF01</td><td>61-6AJ0X-1020</td></tr></table>

![Pure technical line drawing of a mechanical assembly without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/a71a5f8386e42454b4047f1ec4ca195dc143e23d280675e64317b95db17b741c.jpg)

# 6.29. GPIO Wafer

This device provides 4 channels of non-isolation digital input and 4 channels of non-isolation digital output circuits.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_S0</td></tr><tr><td>2</td><td>CN_DI0</td></tr><tr><td>3</td><td>CN_DI1</td></tr><tr><td>4</td><td>CN_DI2</td></tr><tr><td>5</td><td>CN_DI3</td></tr><tr><td>6</td><td>CN_DO0</td></tr><tr><td>7</td><td>CN_DO1</td></tr><tr><td>8</td><td>CN_DO2</td></tr><tr><td>9</td><td>CN_DO3</td></tr><tr><td>10</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>HIROSE</td><td>DF13-10P-1.25H</td><td>61-66J05-1100</td></tr></table>

![Pure electrical component outline without any text, numbers, or symbols](.sp2-mtl-50m-p1600-1010-11/3a82bc7161d4d716e14b22533edcabddc509638b3602ca1f10e8409faa0830a5.jpg)

# 6.29.1 4-Channel Digital Input

VIH: 2 to 5.25V
• VIL: 0 to 0.8V

# 6.29.2 4-Channel Digital Output

• Output type: open drain N-channel
• MOSFET driver with internal pull-high of 200Ω resistance
• Source/Sink current for all channels: 22mA
VOH: 2.4 to 5V
• VOL: 0 to 0.55V

GPIO Connector Pin Voltage

<table><tr><td>Pin</td><td>Signal</td><td>PCH GPIO</td><td>Default Value</td><td>Input/Output Voltage Range</td></tr><tr><td>1</td><td>P_+3V3_S0</td><td></td><td></td><td></td></tr><tr><td>2</td><td>CN_DI0</td><td>GP_B02</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>3</td><td>CN_DI1</td><td>GP_B03</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>4</td><td>CN_DI2</td><td>GP_B18</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>5</td><td>CN_DI3</td><td>GP_B19</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>6</td><td>CN_DO0</td><td>GP_D05</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>7</td><td>CN_DO1</td><td>GP_D06</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>8</td><td>CN_DO2</td><td>GP_D07</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>9</td><td>CN_DO3</td><td>GP_D08</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>10</td><td>GND</td><td></td><td></td><td></td></tr></table>

![+3.3V\n2.2kΩ\nDI_IN\nDIn\n100kΩ\nG\nMOS\nDI_GND](.sp2-mtl-50m-p1600-1010-11/79d7e6ed426ba3df56dccf1f2c56d55c0ce96e57867205d1ea880e1be1bb2614.jpg)

Figure 9 - Digital input circuit

![+3.3V\n+5.0V\n2.2kΩ\n200Ω\nDO_OUT\nG\nD\nS\nMOS\nDOn](.sp2-mtl-50m-p1600-1010-11/49b6f1fc702cc1d508acf955e455fbdb569079de5c6ad9e5b9d69237798cd0a0.jpg)

Figure 10 - Digital output circuit

GPIO Address

<table><tr><td>Net name</td><td>PCH_GPIO</td><td>Address</td></tr><tr><td>PCH_DO0_1V8</td><td>GPP_D05</td><td>0XE0D507E0</td></tr><tr><td>PCH_DO1_1V8</td><td>GPP_D06</td><td>0XE0D507F0</td></tr><tr><td>PCH_DO2_1V8</td><td>GPP_D07</td><td>0XE0D50800</td></tr><tr><td>PCH_DO3_1V8</td><td>GPP_D08</td><td>0XE0D50810</td></tr><tr><td>PCH_DI0_1V8</td><td>GPP_B02</td><td>0XE0D50620</td></tr><tr><td>PCH_DI1_1V8</td><td>GPP_B03</td><td>0XE0D50630</td></tr><tr><td>PCH_DI2_1V8</td><td>GPP_B18</td><td>0XE0D50720</td></tr><tr><td>PCH_DI3_1V8</td><td>GPP_B19</td><td>0XE0D50730</td></tr></table>

![The flowchart depicts connections between pin function descriptions on the left, pin identifiers in the middle column, and signal names on the right. The connections are as follows:\n\n**Group 1:**\n*   **Left Block:** `GPP_D06/ISH_UART0_TXD/ISH_SPI_CLK/SML0BCLK/USB-C_GPP_D06` connects to **Middle Pin:** `EH20`, which connects to **Right Block:** `PCH_DO1_1V8 (24)`.\n*   **Left Block:** `GPP_D05/ISH_UART0_RXD/ISH_SPI_CS/SML0BDATA/USB-C_GPP_D05` connects to **Middle Pin:** `ER20`, which connects to **Right Block:** `PCH_DO0_1V8 (24)`.\n*   **Left Block:** `GPP_D08/ISH_UART0_CTS/ISH_SPI_MOSI/SML0BALERT/USB-C_GPP_D08` connects to **Middle Pin:** `EN20`, which connects to **Right Block:** `PCH_DO3_1V8 (24)`.\n*   **Left Block:** `GPP_D07/IMGCLKOUT/4/ISH_UART0_RTS/ISH_SPI_MISO/USB-C_GPP_D07` connects to **Middle Pin:** `EK20`, which connects to **Right Block:** `PCH_DO2_1V8 (24)`.\n\n**Group 2:**\n*   **Left Block:** `GPP_H15/ISH_UART1_TXD/UART1A_TXD/ISH_I2C1_SCL/USB-C_GPP_H15` connects to **Middle Pin:** `EH38`.\n*   **Left Block:** `GPP_H14/ISH_UART1_RXD/UART1A_RXD/ISH_I2C1_SDA/USB-C_GPP_H14` connects to **Middle Pin:** `EN38` (marked with a red cross).\n\n**Group 3:**\n*   **Left Block:** `GPP_B03/ISH_I2C0_SCL/ISH_I3C0_SCL/I2C2A_SCL/USB-C_GPP_B03` connects to **Middle Pin:** `EH23`, which connects to **Right Block:** `PCH_DI1_1V8 (24)`.\n*   **Left Block:** `GPP_B02/ISH_I2C0_SDA/ISH_I3C0_SDA/I2C2A_SDA/USB-C_GPP_B02` connects to **Middle Pin:** `EN23`, which connects to **Right Block:** `PCH_DI0_1V8 (24)`.\n\n**Group 4:**\n*   **Left Block:** `GPP_B19/ISH_I2C2_SCL/I2C4A_SCL/USB-C_GPP_B19` connects to **Middle Pin:** `ER25`, which connects to **Right Block:** `PCH_DI3_1V8 (24)`.\n*   **Left Block:** `GPP_B18/ISH_I2C2_SDA/I2C4A_SDA/USB-C_GPP_B18` connects to **Middle Pin:** `ER28`, which connects to **Right Block:** `PCH_DI2_1V8 (24)`.\n\n**Group 5:**\n*   **Left Block:** `GPP_B04/BK0/ISH_GP4/SBK0/USB-C_GPP_B04` connects to **Middle Pin:** `EN31` (labeled with red text `GP_B04_PIN_STRAP`), which connects to **Right Block:** `GP_B04_PIN_STRAP (21)`.\n*   **Left Block:** `GPP_B08/BK4/ISH_GP3/SBK4/USB-C_GPP_B08` connects to **Middle Pin:** `EL28`, which connects to **Right Block:** `LCD_CFG_LVDS_CLR_1V8 (24)`.\n*   **Left Block:** `GPP_B07/BK3/ISH_GP2/SBK3/USB-C_GPP_B07` connects to **Middle Pin:** `EN28`, which connects to **Right Block:** `LCD_CFG_LVDS_FMT_1V8 (24)`.\n*   **Left Block:** `GPP_B06/BK2/ISH_GP1/SBK2/USB-C_GPP_B06` connects to **Middle Pin:** `EF25`, which connects to **Right Block:** `LCD_CFG_LVDS_CNL_1V8 (24)`.\n*   **Left Block:** `GPP_B05/BK1/ISH_GP0/SBK1/USB-C_GPP_B05` connects to **Middle Pin:** `EH25`, which connects to **Right Block:** `A_SPKR_1V8 (24)`.](.sp2-mtl-50m-p1600-1010-11/94c6f74d0c49d4f6c3e794fb75c684faad9615e70786fd9e1044908d54ccf956.jpg)

# [Bit definition]

Bit 1-Rx state, 1/0 represents high/low

Bit -Tx state, set to 1 for output high

6.30. M.2 2280, M Key for SATA/PCIE X4 NVME Modules

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>P_+3V3_NGFF_M</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>P_+3V3_NGFF_M</td></tr><tr><td>5</td><td>PCIE12_RX_N</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>PCIE12_RX_P</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr><tr><td>11</td><td>PCIE12_TX_N</td><td>12</td><td>P_+3V3_NGFF_M</td></tr><tr><td>13</td><td>PCIE12_TX_P</td><td>14</td><td>P_+3V3_NGFF_M</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>P_+3V3_NGFF_M</td></tr><tr><td>17</td><td>PCIE11_RX_N</td><td>18</td><td>P_+3V3_NGFF_M</td></tr><tr><td>19</td><td>PCIE11_RX_P</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>NC</td></tr><tr><td>23</td><td>PCIE11_TX_N</td><td>24</td><td>NC</td></tr><tr><td>25</td><td>PCIE11_TX_P</td><td>26</td><td>NC</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>PCIE10_RX_N</td><td>30</td><td>NC</td></tr><tr><td>31</td><td>PCIE10_RX_P</td><td>32</td><td>NC</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>NC</td></tr><tr><td>35</td><td>PCIE10_TX_N</td><td>36</td><td>NC</td></tr><tr><td>37</td><td>PCIE10_TX_P</td><td>38</td><td>PCH_DEVSLP0</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>NC</td></tr><tr><td>41</td><td>M2_PCIE_SATA_RX_P_R</td><td>42</td><td>NC</td></tr><tr><td>43</td><td>M2_PCIE_SATA_RX_N_R</td><td>44</td><td>NC</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td></tr><tr><td>47</td><td>M2_PCIE_SATA_TX_N_R</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>M2_PCIE_SATA_TX_P_R</td><td>50</td><td>M2M_PLTRST_BUF-L</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>PCH_CLK_REQ_P7_N_3V3</td></tr><tr><td>53</td><td>C_PCIECLK7_100M_N</td><td>54</td><td>PCH_PCIE_M2M_WAKE-L</td></tr><tr><td>55</td><td>C_PCIECLK7_100M_P</td><td>56</td><td>NC</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>NC</td></tr><tr><td>67</td><td>NC</td><td>68</td><td>NC</td></tr><tr><td>69</td><td>MUX1_SEL</td><td>70</td><td>P_+3V3_NGFF_M</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>P_+3V3_NGFF_M</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>P_+3V3_NGFF_M</td></tr><tr><td>75</td><td>GND</td><td></td><td></td></tr></table>

![H=4.8\nLOTES\nM](.sp2-mtl-50m-p1600-1010-11/7420a3464a14af1bd18cbb4d1d6d51ca8d6910e7da5a9ae26b25afbdb240a9e8.jpg)

# 6.31. Thunderbolt Type C Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>A1</td><td>GND</td><td>B1</td><td>GND</td></tr><tr><td>A2</td><td>TBT0_TX0_P</td><td>B2</td><td>TBT0_TX1_P</td></tr><tr><td>A3</td><td>TBT0_TX0_N</td><td>B3</td><td>TBT0_TX1_N</td></tr><tr><td>A4</td><td>P_+5VBUS_PD0_TBT0</td><td>B4</td><td>P_+5VBUS_PD0_TBT0</td></tr><tr><td>A5</td><td>PD0_TBT0_944_CC1_CON</td><td>B5</td><td>PD0_TBT0_944_CC2_CON</td></tr><tr><td>A6</td><td>TBT0_USB2_CMC_P</td><td>B6</td><td>TBT0_USB2_CMC_P</td></tr><tr><td>A7</td><td>TBT0_USB2_CMC_N</td><td>B7</td><td>TBT0_USB2_CMC_N</td></tr><tr><td>A8</td><td>TCP0_SBU1_CON</td><td>B8</td><td>TCP0_SBU2_CON</td></tr><tr><td>A9</td><td>P_+5VBUS_PD0_TBT0</td><td>B9</td><td>P_+5VBUS_PD0_TBT0</td></tr><tr><td>A10</td><td>TBT0_RX1_N</td><td>B10</td><td>TBT0_RX0_N</td></tr><tr><td>A11</td><td>TBT0_RX1_P</td><td>B11</td><td>TBT0_RX0_P</td></tr><tr><td>A12</td><td>GND</td><td>B12</td><td>GND</td></tr></table>

![Technical line drawing of a mechanical component with no visible text or symbols](.sp2-mtl-50m-p1600-1010-11/9cf5ed34227c6493efaaa97b564144293b564cf75bbcee2556cb17ab9a785cd3.jpg)

# 6.32. USB3.2 Gen2 Dual Port 1 Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V0_A_CON_USB3_1</td><td>10</td><td>P_+5V0_A_CON_USB3_2</td></tr><tr><td>2</td><td>CON_USB2_D1_N</td><td>11</td><td>CON_USB2_D2_N</td></tr><tr><td>3</td><td>CON_USB2_D1_P</td><td>12</td><td>CON_USB2_D2_P</td></tr><tr><td>4</td><td>GND</td><td>13</td><td>GND</td></tr><tr><td>5</td><td>CON_USB3_RX1_N</td><td>14</td><td>CON_USB3_RX2_N</td></tr><tr><td>6</td><td>CON_USB3_RX1_P</td><td>15</td><td>CON_USB3_RX2_P</td></tr><tr><td>7</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>8</td><td>CON_USB3_TX1_N</td><td>17</td><td>CON_USB3_TX2_N</td></tr><tr><td>9</td><td>CON_USB3_TX1_P</td><td>18</td><td>CON_USB3_TX2_P</td></tr></table>

![Technical line drawing of a dual-chamber electronic component with no text or symbols](.sp2-mtl-50m-p1600-1010-11/fdd86554ae95faaeea768a04d455ca7b26f518a5e05966d2c511a53989a1b14b.jpg)

# 6.33. USB3.2 Gen2 Dual Port 2 Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V0_A_CON_USB3_3</td><td>10</td><td>P_+5V0_A_CON_USB3_4</td></tr><tr><td>2</td><td>CON_USB2_D3_N</td><td>11</td><td>CON_USB2_D4_N</td></tr><tr><td>3</td><td>CON_USB2_D3_P</td><td>12</td><td>CON_USB2_D4_P</td></tr><tr><td>4</td><td>GND</td><td>13</td><td>GND</td></tr><tr><td>5</td><td>CON_USB3_RX3_N</td><td>14</td><td>CON_USB3_RX4_N</td></tr><tr><td>6</td><td>CON_USB3_RX3_P</td><td>15</td><td>CON_USB3_RX4_P</td></tr><tr><td>7</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>8</td><td>CON_USB3_TX3_N</td><td>17</td><td>CON_USB3_TX4_N</td></tr><tr><td>9</td><td>CON_USB3_TX3_P</td><td>18</td><td>CON_USB3_TX4_P</td></tr></table>

![Technical line drawing of a dual-chamber electronic component with mounting holes (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/ea1b4c0e5d39c36687f7c5da09f597b5cd6f26e954828ee4b6cffb3eaaf4a456.jpg)

# 6.34. DP Connector

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>DP+TCP2_TX0_P</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>DP_TCP2_TX0_N</td></tr><tr><td>4</td><td>DP_TCP2_TX1_P</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>DP_TCP2_TX1_N</td></tr><tr><td>7</td><td>DP_TCP2_TX2_P</td></tr><tr><td>8</td><td>GND</td></tr><tr><td>9</td><td>DP_TCP2_TX2_N</td></tr><tr><td>10</td><td>DP_TCP2_TX3_P</td></tr><tr><td>11</td><td>GND</td></tr><tr><td>12</td><td>DP_TCP2_TX3_N</td></tr><tr><td>13</td><td>CON_TCP2_DDC_AUX_SEL</td></tr><tr><td>14</td><td>CON_TCP2_CONFIG_2</td></tr><tr><td>15</td><td>CON_TCP2_I2CCLK_AUX_P</td></tr><tr><td>16</td><td>GND</td></tr><tr><td>17</td><td>CON_TCP2_I2CDAT_AUX_N</td></tr><tr><td>18</td><td>CON_TCP2_HPD</td></tr><tr><td>19</td><td>GND</td></tr><tr><td>20</td><td>P_+3v3_DP1</td></tr></table>

![Technical line drawing of a mechanical component with no visible text or symbols](.sp2-mtl-50m-p1600-1010-11/5854f4a7b4ad733eaa034513910b3d61ac7674daefec26db005557930797280b.jpg)

# 6.35. LAN1 RJ45 Connector

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>R1</td><td>L_GBE1_MDI0_P</td></tr><tr><td>R2</td><td>L_GBE1_MDI0_N</td></tr><tr><td>R3</td><td>L_GBE1_MDI1_P</td></tr><tr><td>R4</td><td>L_GBE1_MDI1_N</td></tr><tr><td>R5</td><td>Cap to GND</td></tr><tr><td>R6</td><td>Cap to GND</td></tr><tr><td>R7</td><td>L_GBE1_MDI2_P</td></tr><tr><td>R8</td><td>L_GBE1_MDI2_N</td></tr><tr><td>R9</td><td>L_GBE1_MDI3_P</td></tr><tr><td>R10</td><td>L_GBE1_MDI3_N</td></tr><tr><td>L1</td><td>LINK_ACT_LED</td></tr><tr><td>L2</td><td>L_GBE1_LED1_LINK/ACT-L</td></tr><tr><td>L3</td><td>L_GBE1_LINK1000-L</td></tr><tr><td>L4</td><td>L_GBE1_LINK2500-L</td></tr></table>

![Technical line drawing of an electrical connector housing (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/0f08937bd3855df3a2e714fc31305ee1744d1594254202f28d0e17e35fb4eecc.jpg)

# 6.36. LAN2 RJ45 Connector

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>R1</td><td>L_GBE2_MDI0_P_RJ45</td></tr><tr><td>R2</td><td>L_GBE2_MDI0_N_RJ45</td></tr><tr><td>R3</td><td>L_GBE2_MDI1_P_RJ45</td></tr><tr><td>R4</td><td>L_GBE2_MDI1_N_RJ45</td></tr><tr><td>R5</td><td>Cap to GND</td></tr><tr><td>R6</td><td>Cap to GND</td></tr><tr><td>R7</td><td>L_GBE2_MDI2_P_RJ45</td></tr><tr><td>R8</td><td>L_GBE2_MDI2_N_RJ45</td></tr><tr><td>R9</td><td>L_GBE2_MDI3_P_RJ45</td></tr><tr><td>R10</td><td>L_GBE2_MDI3_N_RJ45</td></tr><tr><td>L1</td><td>LINK_ACT_LED2</td></tr><tr><td>L2</td><td>LGBE2_LED1_LINK/ACT-L</td></tr><tr><td>L3</td><td>L_GBE2_LINK1000-L</td></tr><tr><td>L4</td><td>L_GBE2_LINK2500-L</td></tr></table>

![Technical line drawing of an electrical connector housing (no text or symbols)](.sp2-mtl-50m-p1600-1010-11/fc8d0c69b1f6a804a3e0a442e389cd64cdf4e4cdb79f27691d2b1a236a486128.jpg)

# 6.37. LAN (I226) LED Connector Position

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Yellow(Left LED)</td><td>OFF</td><td>Ethernet port is disconnected.</td></tr><tr><td>ON</td><td>Ethernet port is connected with no activity.</td></tr><tr><td>Flashing</td><td>Ethernet port is connected and active.</td></tr></table>

# 6.37.1 LAN1/2 Active/Link LED

LAN1/2 Speed LED (2.5G)

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Yellow(Left LED)</td><td>OFF</td><td>10/100 Mbps</td></tr><tr><td>Yellow</td><td>1000 Mbps</td></tr><tr><td>Yellow</td><td>2500 Mbps</td></tr></table>

LAN1/2 Speed LED (1G)

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Yellow(Left LED)</td><td>OFF</td><td>10 Mbps</td></tr><tr><td>OFF</td><td>100 Mbps</td></tr><tr><td>Yellow</td><td>1000 Mbps</td></tr></table>

![Left LED Right LED](.sp2-mtl-50m-p1600-1010-11/ab46d5b2df0a078dac366d2ac59e5f235cc77c411a61f5041590a4bd4c9fca72.jpg)

# 6.38. Jumper Setting

# Backlight PWR

Backlight PWR option

<table><tr><td colspan="2">JP1 Backlight PWR</td></tr><tr><td>1-2</td><td>+12V (Default)</td></tr><tr><td>2-3</td><td>+5V</td></tr></table>

# Clear CMOS header

Under conditions where the device fails to boot, clearing the BIOS content stored in CMOS and restoring the default settings may be effective. To clear CMOS, short Pin 2 and Pin 3, then wait for 5 seconds. Remove the jumper cap and short Pin 1 and Pin 2.

<table><tr><td colspan="2">Clear COS Pin Header</td></tr><tr><td>CN1</td><td></td></tr><tr><td>(1-2)</td><td>NA (Default)</td></tr><tr><td>(2-3)</td><td>Clear CMOS</td></tr></table>

# 7. Getting Started

Follow the instructions in this chapter to add or change memory; Wi-Fi modules, mounting brackets, and mounting clips.

# 7.1. Adding or Changing Memory

Follow these steps to add or change memory modules.

1. Remove the 3 screws that attach the heatsink to the mainboard, and then remove the heatsink.
2. Install or swap the memory module in the SODIMM socket as necessary.

![Back panel of an electronic device showing internal components including connectors, drive bays, and a central CPU socket (no text or symbols visible)](.sp2-mtl-50m-p1600-1010-11/682fca0afabae2d204c0010a70aaf236eadeaa2be9c624a39e63ef1f40b623a3.jpg)

![Technical diagram of an electronic device rear panel with labeled components including Latches, AFCI, and connector pins.](.sp2-mtl-50m-p1600-1010-11/130c288c33b401616dfd6ce6aeffab4fec906457516133fd4cf15f7842d6343e.jpg)

3. Reattach the heat sink to the mainboard with the previously removed screws.

# 7.2. Installing a Wi-Fi-Module

Follow these steps to add or change a Wi-Fi module.

1. Remove the 3 screws that attach the heatsink to the mainboard, and then remove the heatsink.

![Back view of an electronic device chassis showing internal components and connectors (no text or symbols visible)](.sp2-mtl-50m-p1600-1010-11/422039f7c5b46cfb9f80374537ecdf1c8d8cdcdbc74828feb03812910c59ec28.jpg)

2. Install the Wi-Fi module.

![A1' A2'\nA1 A2\nA1 A2](.sp2-mtl-50m-p1600-1010-11/b2fbe2fb34f7903aca008764c32ac8cec159afdaa55b9b16bc621e930549f929.jpg)

![AUX: A2'\nMain: A1'](.sp2-mtl-50m-p1600-1010-11/8a213eea9a66aba90214dccd2b63a071488cd1e3529141ea20bb94ccff6ddae2.jpg)

3. Reattach the heat sink to the mainboard with the previously removed screws.

4. Install Antennas to rear cover or equipment

![A1\nA2\nRear Cover](.sp2-mtl-50m-p1600-1010-11/bc0e9c36454b9bf39f25ee7cf541102c3947de14df4c66e890ef6511c416c366.jpg)

![The image displays a red icon of a document. It features a red outline of a piece of paper with a folded bottom-right corner. Inside the document, there are two horizontal red lines symbolizing text.](.sp2-mtl-50m-p1600-1010-11/86ca3318f0b16181081a1a295313493dee67981c8bf36a43fb7d52e3e4783ac0.jpg)

Note: Wi-Fi antennas must be installed on the SP2-MTL Series housing in order for Wi-Fi to function properly.

# 7.3. Installing an LTE Module

Follow these steps to add or change a Wi-Fi module.

1. Remove the 3 screws that attach the heatsink to the mainboard, and then remove the heatsink.

![Back panel of an electronic device showing internal components including connectors, RAM slots, and a AFC connector (no text or symbols present)](.sp2-mtl-50m-p1600-1010-11/00efc34967ffed52362218ec28bc487afadf84ad0596944caf104554038edc23.jpg)

2. Install the LTE module.

![Main: A1' DIV: A2'\n\nA1' A1 A2 A2\n\nA1' A2'](.sp2-mtl-50m-p1600-1010-11/48fd4e7d39bcbd720aca5a33d2bfe8098b176f274163e2ff788de9dc6a6c0fbe.jpg)

3. Reattach the heat sink to the mainboard with the previously removed screws.

4. Install Antennas to rear cover or equipment

![Rear Cover](.sp2-mtl-50m-p1600-1010-11/d48cb8b49be5d9610f8921cfc7add67d274da64d5c8ff9f550b38ea458d032e1.jpg)

![The image displays a simple icon of a document or memo. It features a red outline of a page with the top right corner folded down. Inside the shape, there are three horizontal red lines centered horizontally, resembling text. The background is white.](.sp2-mtl-50m-p1600-1010-11/756ce03fcfd523d0b24ccca0e33541e7767d9618b52180b48691cf8406ec0120.jpg)

Note: LTE antennas must be installed on the SP2-MTL Series housing in order for LTE to function properly.

# 7.4. Mounting

This section includes details for panel and VESA mounting options.

![A red icon depicting a document or page with a folded bottom-right corner. Inside the red outline, three horizontal red lines are centered.](.sp2-mtl-50m-p1600-1010-11/dbc0e9a96e9b9b0585a6cbeeb542c1b5d6d9fce7692bdd3d271d5ca148a64ea4.jpg)

Note: All dimensions are in millimeters, unless noted.

![A red triangular warning sign containing a white exclamation point in the center.](.sp2-mtl-50m-p1600-1010-11/15faa7085ab86dbeb430ffad14727914420d1a6e1683de23540b25f16d923f02.jpg)

Warning: Risk of physical injuries and / or property damage:

When mounting the device, use the screws to mount the VESA bracket to the rear of the device. Tighten all four screws firmly to support the weight of the device. Make sure that the suspension system is capable of carrying the device.

![A yellow triangular warning sign with a black border and a black exclamation point in the center.](.sp2-mtl-50m-p1600-1010-11/49b1697f32d4bedfd35e9b6c3ff2d860d9ffca7960101450bc97b9e2feb3d53b.jpg)

Caution: Risk of burns to the user caused by hot surfaces:

Turn off power and allow the device to cool down prior to performing any mounting or demounting operations. Do not touch the enclosure for over 10 seconds when the device is in operations or is still hot from previous use.

# 7.4.1 Panel Mounting

The SP2-MTL Series can be panel mounted with 14 mounting clips (optional items sold separately). Make sure there is adequate space behind the panel for ventilation, and that the panel material and thickness can support the weight of the device.

Step 1: Cut the panel opening using the appropriate cutout dimensions.

SP2-10WP cutout

![238.06±0.5\nCUT OUT\n159.4±0.5](.sp2-mtl-50m-p1600-1010-11/9ac6fa432f235fc78aefbcd1d95bb9586066fcb64d53a3ae91b08bfb5a4987c5.jpg)

Figure 11 - SP2-10WP cutout dimensions

SP2-15WP cutout
![371.8±0.5\nCUT OUT\n221.6±0.5](.sp2-mtl-50m-p1600-1010-11/586bfc29919fd044589bf61ecaf95044c7b0f856af95e5b503b416e20c878a98.jpg)

Figure 12 - SP2-15WP cutout dimensions

# SP2-21WP cutout

![505.6±0.5\nCUT OUT\n297.9±0.5](.sp2-mtl-50m-p1600-1010-11/d59f1f2bb3c5a7ba0fbc033bf16295e82cf32830954ba28525ef6384dc9d035b.jpg)

Figure 13 - SP2-21WP cutout dimensions

Step 2: Attach I/O cables to the device before installing into the panel if rear access will be limited after installation.

Step 3: Place the device into the panel cutout.
![Diagram showing two rectangular panels with a red arrow indicating direction, no text or symbols present](.sp2-mtl-50m-p1600-1010-11/b9b0ff0e5cf38e511226b5c8aecbc8d71a3b53b64f102d96a36b713b2830a37f.jpg)

Step 4: Insert the mounting clips into the slots on the sides of the device as shown. Hand-tighten the mounting clips with a Phillips- head screwdriver to secure it to the panel. Do not overtighten the clips to avoid damaging the device enclosure.

![1.5\n1.5\n1.5\nPOWER\nLED\nLED DOT\n+\n-\nDD-N 10\nHDD 10A\nCLIP](.sp2-mtl-50m-p1600-1010-11/1d3c60c526974494360c7accbbf212e7dafae243e26349a7f7a5e7817bc3fb1b.jpg)

![14.2⁺⁰·³₋₀·₁\n5.7\n16.7 ± 0.3\n12\n26.5⁺⁰·¹₋₀·⁵\n12\n1.2\nTAP M4\nCROSS_P_NI_M4\n5\n3\n1.3](.sp2-mtl-50m-p1600-1010-11/d406f2838b2b58a5d0d2aa9f642749f12fc21ff00bc65bffacfdbd08369f7da4.jpg)

Figure 14 - Mounting clip dimensions

![The image displays a red outline of a square document with a folded bottom-right corner. Inside the outline are two horizontal red lines centered vertically.](.sp2-mtl-50m-p1600-1010-11/7c69f9a0ecc0fa1dfe7df15d6f159cb61d9c17666086600d2e2806e395686455.jpg)

Note: Optional mounting clips sold separately. Contact your ADLINK reseller for details.

# 7.4.2 VESA Mounting

The SP2-MTL Series can be VESA mounted with a rear cover and VESA bracket. (Optional items sold separately.)

![The image displays a red icon on a white background. It features a thick red outline of a document or piece of paper with a curled bottom-right corner. Inside the outline, there are two horizontal red lines centered vertically, resembling text or a list.](.sp2-mtl-50m-p1600-1010-11/7101c71fb6d1303eb409fd66992f597d9f59df3b64523787e1a9828998fd2465.jpg)

Note: 1. All I/O ports must face down. 2. Optional VESA bracket and M3 screws sold separately. Contact your ADLINK reseller for details. 3. Mounting bracket provides 100 mm x 100 mm VESA mounting and requires 4x M4 screws.

Attach the rear cover to the panel PC with the screws supplied in the kit, then secure the VESA bracket to the rear cover with 4x M3 screws.

![VESA bracket\n100x 100\nRear cover](.sp2-mtl-50m-p1600-1010-11/f581488c6e107e29c9b770179914f704e8d96fbd3ca7a3527d4d3e0b4faa5854.jpg)

# 8. Driver and Application Installation

After installing the operating system, all related drivers must be installed for the system to function properly. This section describes the drivers needed for Windows operating systems and the procedures to install them. For other operating system support, contact ADLINK for further information.

Visit the ADLINK web site to download drivers:

https://www.adlinktech.com/Products/Panel\_PCs\_Monitors/Panel\_PCs\_Monitors/SP2-MTL\_Series

# 9. BIOS Setup

# 9.1. Menu Structure

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right-hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS InformationSystem InformationSystem DateSystem Time</td><td>CPU Configuration▶Power Management▶Graphics Configuration▶Super I/O Configuration▶BIOS Watchdog Timer▶Serial Port Console Redirection▶Hardware Monitor▶NVME Configuration▶Trusted Computing▶Miscellaneous▶Network Stack Configuration▶</td><td>System Agent (SA) Configuration▶PCH-IO Configuration▶</td><td>PasswordDescriptionSecure BootMenu▶</td><td>BootConfiguration</td><td>Save OptionsDefault OptionsBoot Override</td></tr></table>

# Notes:

► Indicates a submenu

Gray text indicates info only

# 9.2. Main

The Main Menu provides read-only information about your system and allows you to set the System Date and Time. Refer to the tables below for details about the submenus and settings.

9.2.1 BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vender</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display Core version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Display Compliancy Information</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display compliancy Information</td></tr><tr><td>GOP Driver Version</td><td>Info only</td><td>Display Intel Graphic Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display Intel CSME Version</td></tr></table>

9.2.2 System Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU Signature</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display CPU Brand Name</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed Memory Size</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory Frequency</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH Information</td></tr><tr><td>FM Board</td><td>Info only</td><td></td></tr></table>

# 9.2.3 Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SMC Serial Number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SMC Manufacturing Date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SMC Last Repair Date.</td></tr></table>

# 9.2.4 System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# 9.3. Advanced

This menu contains the settings for most of the user interfaces in the system.

9.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Turbo Mode</td><td>Disabled, Enabled</td><td>Enable/Disable processor Turbo Mode (requires EMTTM enabled too). AUTO means enabled.</td></tr><tr><td>C States</td><td>Disabled, Enabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it&#x27;s not 100% utilized.</td></tr><tr><td>Intel Trusted Execution Technology</td><td>Disabled, Enabled</td><td>Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect.</td></tr><tr><td>X2APIC Enable</td><td>Disabled, Enabled</td><td>Enable/Disable X2APIC Operating Mode.</td></tr></table>

# 9.3.2 Power Management

9.3.2.1. Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto Configuration</td><td>Disabled, Enabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>Disabled, Enabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disabled, S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>ERP</td><td>Disabled, Enabled</td><td>Energy-Related Products</td></tr><tr><td>State After G3</td><td>S0 State, S5 State</td><td>Specify what state to go to when power is re-applied after a power failure (G3 state).</td></tr></table>

9.3.3 Graphic Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nxp configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>AutoVESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>AutoDual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polarity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>DDI port 1</td><td>No Device,Display Port,HDMI,DisplayPort withHDMI/DVI Compatible</td><td>Select LVDS Backlight control function.</td></tr></table>

9.3.4 Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td colspan="2">Info only</td></tr><tr><td>NCT5525D Super IO Configuration</td><td>submenu</td><td></td></tr><tr><td>NCT5104S Super IO Configuration</td><td>submenu</td><td></td></tr></table>

9.3.4.1. Super I/O Configuration > NCT5525D Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5525D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>submenu</td><td></td></tr></table>

9.3.4.1.1. Super I/O Configuration > NCT5525D Super I/O Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>Device Mode</td><td>RS232RS485RS422</td><td>Change the Serial Port mode</td></tr></table>

9.3.4.1.2. Super I/O Configuration > NCT5525D Super I/O Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>Device Mode</td><td>RS232RS485RS422</td><td>Change the Serial Port mode</td></tr></table>

9.3.4.2. Super I/O Configuration > NCT5104D Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5104D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>submenu</td><td></td></tr></table>

9.3.4.2.1. Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>COM1 Control</td><td>RS232RS485RS422</td><td>Select COM1 mode, RS232, RS422 or RS485</td></tr></table>

9.3.4.2.2. Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>COM2 Control</td><td>RS232RS485RS422</td><td>Select COM2 mode, RS232, RS422 or RS485</td></tr></table>

9.3.4.2.3. Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 3 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 3 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr></table>

9.3.4.2.4. Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 4 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 4 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr></table>

9.3.5 BIOS Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>BIOS POST watchdog</td><td>Disabled,Second Mode,Minute Mode</td><td>1. Disable: Disables Watchdog Timer; 2. Second Mode:Enables Watchdog Timer in second mode; 3. MinuteMode: Enables Watchdog Timer in minute mode.</td></tr></table>

9.3.6 Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>Disabled, Enabled</td><td>To enable or disable console redirection of COMx.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

9.3.6.1. Serial Port Console > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM0</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1&#x27;s in the data bits is even. Odd: parity bit is 0 if num of 1&#x27;s in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr></table>

9.3.7 Hardware Monitor

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System temperature</td><td>Info Only</td><td></td></tr><tr><td>CPU temperature</td><td>Info Only</td><td></td></tr><tr><td>MXM FAN Speed</td><td>Info Only</td><td></td></tr><tr><td>SYSTEM FAN Speed</td><td>Info Only</td><td></td></tr><tr><td>5V_S0</td><td>Info Only</td><td></td></tr><tr><td>VCCCORE</td><td>Info Only</td><td></td></tr><tr><td>VCC3V</td><td>Info Only</td><td></td></tr><tr><td>VSB3V</td><td>Info Only</td><td></td></tr><tr><td>VBAT</td><td>Info Only</td><td></td></tr><tr><td>AVSB</td><td>Info Only</td><td></td></tr><tr><td>Smart Fan Function</td><td>Submenu</td><td>Smart Fan function setting</td></tr></table>

9.3.7.1. Hardware Monitor > Smart Fan Function

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>MXM Fan Setting</td><td>Submenu</td><td></td></tr><tr><td>System Fan Setting</td><td>Submenu</td><td></td></tr></table>

9.3.7.1.1. Hardware Monitor > Smart Fan Function > MXM / System Fan setting

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Fan Mode</td><td>Manual mode, SMART FAN IV</td><td>Fan control mode select</td></tr><tr><td>Manual PWM</td><td>128</td><td>Fan will operate based on the manual PWM value (0 to 255 corresponds to 0% to 100%)</td></tr></table>

9.3.8 NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Seg:Bus:Dev:Func</td><td colspan="2">Info only</td></tr><tr><td>Model Number</td><td colspan="2">Info only</td></tr><tr><td>Total Size</td><td colspan="2">Info only</td></tr><tr><td>Vendor ID</td><td colspan="2">Info only</td></tr><tr><td>Device ID</td><td colspan="2">Info only</td></tr><tr><td>Namespace</td><td colspan="2">Info only</td></tr><tr><td>Self Test Option</td><td>ShortExtended</td><td>Select either Short or Extended Self Test. Short option will take couple of minutes and extended option will take several minutes to complete.</td></tr><tr><td>Self Test Action</td><td>Controller Only TestController andNameSpace Test</td><td>Select either to testcontrolleralone or Controller and NameSpace. Selecting Controller andNamespaceoption will take lot longer to complete the test.</td></tr><tr><td>Run Device Self Test</td><td></td><td>Perform device self test for the corresponding Option and Action selected by user. Pressing &#x27;Esc&#x27; key will abort the test. Result shown below is the recent result logged in the device.</td></tr></table>

# 9.3.9 Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable, Enable</td><td>Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr></table>

# 9.3.10 Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td>Info only</td><td></td></tr><tr><td>BIOS Lock</td><td>DisabledEnabled</td><td>Enables/Disables the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr></table>

# 9.3.11 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enables/Disables UEFI network stack.</td></tr><tr><td>Ipv4 PXE Support</td><td>DisabledEnabled</td><td>Enables/Disables IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>Ipv6 PXE Support</td><td>DisabledEnabled</td><td>Enables/Disables IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>PXE boot wait time</td><td>0</td><td>Wait time in seconds to press ESC key to abort the PXE boot.Use either +/- or numeric keys to set the value.</td></tr></table>

# 9.4. Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA) Configuration</td><td>submenu</td><td></td></tr><tr><td>PCH-IO Configuration</td><td>submenu</td><td></td></tr></table>

# 9.4.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Graphics Configuration</td><td>submenu</td><td>Graphics Configuration</td></tr><tr><td>VT-d setup menu</td><td>submenu</td><td>VT-d Configuration settings</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Enabled, Disabled</td><td>Enables/Disables above 4GB MemoryMappedIO BIOS assignment\n\nThis is enabled automatically when Aperture Size is set to 2048MB.</td></tr></table>

# 9.4.1.1. System Agent (SA) Configuration > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Primary Display</td><td>Auto, IGFX, HG</td><td>Select AUTO set IGD to be Primary Display if no external Graphics Device connected otherwise external Graphics Device detected on first PCIe port will be Primary Display or Select IGFX</td></tr><tr><td>Internal Graphics</td><td>Disabled, Enabled</td><td>Keep IGFX enabled based on the setup options.</td></tr></table>

# 9.4.2 PCH-I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td></td></tr><tr><td>USB Configuration</td><td>Submenu</td><td></td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td></td></tr></table>

9.4.2.1. PCH-I/O Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPA3</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPA4</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPB1</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPB2</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPB3</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port PXPB4</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr></table>

9.4.2.1.1. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port PXPA3

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPA3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot.SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled,L0s,L1,L0sL1,Auto</td><td>Set the ASPM Level:Force L0s - Force all links to L0s StateAUTO - BIOS auto configureDISABLE - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>Disabled,L1.1,L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Hot Plug</td><td>Disabled,Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto,Gen1,Gen2,Gen3,Gen4</td><td>Configure PCIe Speed</td></tr></table>

9.4.2.1.2. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port PXPA4

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPA4</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot.SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled,L0s,L1,L0sL1,Auto</td><td>Set the ASPM Level:Force L0s - Force all links to L0s StateAUTO - BIOS auto configureDISABLE - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>Disabled,L1.1,L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Hot Plug</td><td>Disabled,Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto,Gen1,Gen2,Gen3,Gen4</td><td>Configure PCIe Speed</td></tr></table>

9.4.2.1.3. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port PXPB1

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPB1</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot.SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled,L0s,L1,L0sL1,Auto</td><td>Set the ASPM Level:Force L0s - Force all links to L0s StateAUTO - BIOS auto configureDISABLE - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>Disabled,L1.1,L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Hot Plug</td><td>Disabled,Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto,Gen1,Gen2,Gen3,Gen4</td><td>Configure PCIe Speed</td></tr></table>

9.4.2.1.4. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port PXPB2

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXB2</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot.SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled, L0s, L1,L0sL1, Auto</td><td>Set the ASPM Level:Force L0s - Force all links to L0s StateAUTO - BIOS auto configureDISABLE - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>Disabled,L1.1,L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr></table>

9.4.2.1.5. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port PXPB3

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXB3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot.SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled,L0s,L1,L0sL1,Auto</td><td>Set the ASPM Level:Force L0s - Force all links to L0s StateAUTO - BIOS auto configureDISABLE - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>Disabled,L1.1,L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Hot Plug</td><td>Disabled,Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto,Gen1,Gen2,Gen3, Gen4</td><td>Configure PCIe Speed</td></tr></table>

9.4.2.1.6. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port PXPB4

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port PXPB4</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>Connection Type</td><td>Built-in, Slot</td><td>Built-In: a built-in device is connected to this rootport. SlotImplemented bit will be clear. Slot: this rootport connects to user-accessible slot.SlotImplemented bit will be set.</td></tr><tr><td>ASPM</td><td>Disabled,L0s,L1,L0sL1,Auto</td><td>Set the ASPM Level:Force L0s - Force all links to L0s StateAUTO - BIOS auto configureDISABLE - Disables ASPM</td></tr><tr><td>L1 Substates</td><td>Disabled,L1.1,L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Hot Plug</td><td>Disabled,Enabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>Auto,Gen1,Gen2,Gen3,Gen4</td><td>Configure PCIe Speed</td></tr></table>

9.4.2.2. PCHI-I/O Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Port 0</td><td>Disabled, Enabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>Disabled, Enabled</td><td>Designates this port as Hot Pluggable.</td></tr></table>

9.4.2.3. PCHI-I/O Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Port Disable Override</td><td>Disabled, Enabled</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB SW Device Mode Port #0</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #1</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #2</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #3</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #4</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #5</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #6</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #7</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #8</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr><tr><td>USB SW Device Mode Port #9</td><td>Disabled, Enabled</td><td>Enable Connector Event for device subscription.</td></tr></table>

# 9.4.2.4. PCHI-I/O Configuration > Security Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Lock</td><td>Disabled, Enabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr></table>

# 9.4.2.5. PCHI-I/O Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>Disabled,Enabled</td><td>Control Detection of the HD-Audio device.Disabled = HDA will be unconditionally disabledEnabled = HDA will be unconditionally enabled.</td></tr></table>

# 9.5. Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Set Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Set User Password</td></tr><tr><td>HDD Security Configuration</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>submenu</td><td></td></tr></table>

9.5.1 Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>DisabledEnabled</td><td>Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode,The mode change requires platform reset</td></tr><tr><td>Secure Boot Mode</td><td>StandardCustom</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full</td></tr><tr><td>Restore Factory Keys</td><td>Info only</td><td>Force System to User Mode. Install factory default Secure Boot key databases</td></tr><tr><td>Reset To Setup Mode</td><td>Info only</td><td></td></tr><tr><td>Expert Key Management</td><td></td><td>Enables expert users to modify Secure Boot Policy variables without full authentication</td></tr></table>

# 9.6. Boot

9.6.1 Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>OnOff</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll Sata Devices</td><td>If Last Boot SATA Devices Only, Only last boot SATA device will be available in Post. If All Sata Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>NVME Support</td><td>DisabledEnabled</td><td>If Disabled, NVMe device will be skipped.</td></tr><tr><td>VGA Support</td><td>AutoEFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. Efi driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>DisabledFull InitialPartial Initial</td><td>If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Devices Support</td><td>DisabledEnabled</td><td>If Disabled, PS2 devices will be skipped.</td></tr><tr><td>NetWork Stack Driver Support</td><td>DisabledEnabled</td><td>If Disabled, NetWork Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>DisabledEnabled</td><td>If disable, Redirection function will be disabled.</td></tr></table>

# 9.7. Save & Exit

# 9.7.1 Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr></table>
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