# SP2-TWL Series

User’s Guide

intel

![Exploded view of a computer monitor showing internal components including circuit boards, heat sinks, and a fan (no text or symbols visible)](.sp2-twl-50m-p1700-1000-10-0529/2835e1903e50a4d03f2e95285cfe2349b0143d3051bb2c755c6787bb258eaff5.jpg)

Revision: Rev. 1.0

Date: 2026-05-28

CopyrighPart Number: 2026 ADLINK Tech50M-P1700-1000

Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>Author</td></tr><tr><td>1.0</td><td>Initial release</td><td>2026-05-28</td><td>AL</td></tr></table>

# Preface

# Disclaimer

Information in this document is provided in connection with ADLINK products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in ADLINK´s Terms and Conditions of Sale for such products, ADLINK assumes no liability whatsoever, and ADLINK disclaims any express or implied warranty, relating to sale and/or use of ADLINK products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. If you intend to use ADLINK products in or as medical devices, you are solely responsible for all required regulatory compliance, including, without limitation, Title 21 of the CFR (US), Directive 2007/47/EC (EU), and ISO 13485 & 14971, if any. ADLINK may make changes to specifications and product descriptions at any time, without notice.

# Environmental Responsibility

ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![The image shows a yellow triangular warning sign with a thick black border. Inside the triangle is a large, black exclamation point centered vertically and horizontally.](.sp2-twl-50m-p1700-1000-10-0529/ff12212d78b606308d2807c8adb85306e5851558017ecbd9fe1e67d62d14e2ca.jpg)

California Proposition 65 Warning: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3- dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

![The image displays a black-and-white line drawing of a wheeled trash bin. A large 'X' is superimposed over the bin, indicating prohibition. Below the symbol is a solid black rectangular block. There is no text visible in the image.](.sp2-twl-50m-p1700-1000-10-0529/89bb61d185c2a49d18b4c7065ffb3725e5b19b6ec096b6bf94ca13c6f8696d73.jpg)

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies.

# Copyright © 2026 ADLINK Technology Incorporated

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Safety Instructions

For user safety, please read and follow all Instructions, WARNINGs, CAUTIONs, and NOTEs marked in this manual and on the associated equipment before handling/operating the equipment.

Read these safety instructions carefully:

• Keep the User’s Manual for future reference.
• Read the Specifications section of this manual for detailed information on the recommended operating environment.
It is recommended that the device be installed in Information
• Technology Rooms that are in accordance with Article 645 of the National Electrical Code and NFPA 75.
• When installing/mounting or uninstalling/removing device is required:

o Turn off power and unplug any power cords/cables.
o Reinstall all chassis covers before restoring power.

• To avoid electrical shock and/or damage to device:

o Keep device away from water or liquid sources.
o Keep device away from high heat or humidity.
o Keep device properly ventilated (do not block or cover ventilation openings).
o Always use recommended voltage and power source settings.
o Always install and operate device near an easily accessible electrical outlet.
o Secure the power cord (do not place any object on/over the power cord).
o Only install/attach and operate device on stable surfaces and/or recommended mountings.

o The device is powered by an adapter or DC source. Ensure that the adapter or DC source is properly grounded.

• If the device will not be used for long periods of time, turn off and unplug from its power source.

• Never attempt to repair the device, which should only be serviced by qualified technical personnel using suitable tools.

• A Lithium-type battery may be provided for uninterrupted backup or emergency power.

• The device must be serviced by authorized technicians when:

o The power cord or plug is damaged.
o Liquid has entered the device interior.
o The device has been exposed to high humidity and/or moisture.
o The device is not functioning or does not function according to the User’s Manual.
o The device has been dropped and/or damaged and/or shows obvious signs of breakage.

• Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up.

• It is recommended that the device be installed only in a server room or computer room where access is:

o Restricted to qualified service personnel or users familiar with restrictions applied to the location, reasons therefor, and any precautions required.
o Only afforded by the use of a tool or lock and key, or other means of security, and controlled by the authority responsible for the location.

![The image displays a yellow, upward-pointing triangle, characteristic of a warning sign. Centered within the triangle is a white exclamation mark. The background is plain white.](.sp2-twl-50m-p1700-1000-10-0529/4147d83669f1bd8915476c0a797d20b4a6c9fa2f8f32c10f3c7584e9eaa9dc4d.jpg)

Caution: Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately.

![The image shows a triangular warning sign with a yellow background and a thick black border. Inside the triangle is a black pictogram featuring three wavy vertical lines rising from a horizontal line at the bottom, which is the standard symbol for a hot surface.](.sp2-twl-50m-p1700-1000-10-0529/11fa7dd5ca712667f325ab441c01ad1939f31d4242cbcf054fd17c76bc459f24.jpg)

# BURN HAZARD

Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching.

# Consignes de Sécurité Importante

Pour la sécurité de l'utilisateur, veuillez lire et suivre toutes les instructions, avertissements, mises en garde et notes marqués dans ce manuel et sur l'appareil associé avant de manipuler/d'utiliser l'appareil, afin d'éviter toute blessure ou tout dommage.

• Lisez attentivement ces consignes de sécurité
• Conservez le manuel de l'utilisateur pour pouvoir le consulter Ultérieurement
• Lisez la section Spécifications de ce manuel pour des informations détaillées sur l'environnement d'exploitation recommandé
Il est recommandé d'installer l'appareil dans Information Salles technologiques conformes à l'article 645 du Code national de l'électricité et NFPA 75.

• Lorsque l'installation/le montage ou la désinstallation/le retrait du périphérique est requis:

o Mettez l'appareil hors tension et débranchez tous les cordons/câbles d'alimentation
o Réinstallez tous les couvercles de châssis avant de rétablir l'alimentation

• Pour éviter les chocs électriques et/ou d’endommager l’appareil:

o Tenez l'appareil à l'écart de toute source d'eau ou de liquide.
o Tenez l'appareil à l'écart d'une forte chaleur ou d'une humidité élevée.
o Maintenez l'appareil correctement ventilé (n'obstruer ou ne couvrez pas les ouvertures de ventilation).
o Utilisez toujours les réglages de tension et de source d'alimentation recommandés.
o Installez et utilisez toujours l'appareil près d'une prise de courant facilement accessible.
o Fixez le cordon d'alimentation (ne placez aucun objet sur le cordon d'alimentation).
o Installez/fixez et utilisez l'appareil uniquement sur des surfaces stables et/ou sur les fixations recommandées.

o L'ordinateur Smart Touch est alimenté par un adaptateur ou une source CC. Veuillez vous assurer que l'adaptateur ou la source CC doit conserver la connexion à la terre s'il est doté d'une protection.

• Si l'appareil ne doit pas être utilisé pendant de longues périodes, éteignez-le et débranchez-le de sa source d'alimentation
• N'essayez jamais de réparer l'appareil, qui ne doit être réparé que par un personnel technique qualifié à l'aide d'outils appropriés
• Une batterie de type Lithium peut être fournie pour une alimentation de secours ininterrompue ou d'urgence.
L'appareil doit être entretenu par des techniciens agrees lorsque:

o Le cordon d’alimentation ou la prise est endommagé(e)
o Un liquide a pénétré à l'intérieur de l'appareil.
o L'appareil a été exposé à une forte humidité et/ou de la buée.
o L'appareil ne fonctionne pas ou ne fonctionne pas selon le manuel de l'utilisateur.
o L'appareil est tombé et/ou a été endommagé et/ou présente des signes évidents de dommage.

• Débranchez le cordon d'alimentation avant de desserrer les vis à oreilles et serrez toujours les vis à oreilles avec un tournevis avant de mettre le système en marche.
• Il est recommandé d'installer l'appareil uniquement dans une salle de serveurs ou une salle informatique où l'accès est:

o Réservé au personnel de service qualifié ou aux utilisateurs familiarisés avec les restrictions appliquées à l'emplacement, aux raisons de ces restrictions et toutes les précautions requises
o Uniquement autorisé par l'utilisation d'un outil, d'une serrure et d'une clé, ou d'un autre moyen de sécurité, et contrôlé par l'autorité responsable de l'emplacement.

![A yellow triangular warning sign with a thick black border. Inside the triangle is a black symbol showing three wavy vertical lines rising above a horizontal line, indicating a hot surface.](.sp2-twl-50m-p1700-1000-10-0529/bdfb0b9f8209f99e58d83dff68165228b9efa34be985996aabaa78a7175a410f.jpg)

# RISQUE DE BRÛLURES

Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir avant de la toucher.

# EMC Compliance

# CE Warning

This is a Class B product. In a domestic environment, this product may cause radio interference, in which case the user may be required to take adequate measures.

# FCC warning

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy. If not installed and used in accordance with the instructions, it may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.

If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try one or more of the following measures to correct the interference:

Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and the receiver.
• Connect the equipment to an outlet on a circuit different from the one to which the receiver is connected.
. Consult the dealer or an experienced radio/TV technician for assistance.

# Conventions

The following conventions may be used throughout this manual, denoting special levels of information.

![The image features a red icon resembling a document or note with a folded bottom-right corner. Inside the red outline, there are two horizontal red lines centered in the upper portion, representing text.](.sp2-twl-50m-p1700-1000-10-0529/30a90547d978a85630c8958958d3d9d7d85c4ad56cdeb0a172e9706b08bca4f0.jpg)

Note: This information adds clarity or specifics to text and illustrations.

![The image displays a yellow, equilateral triangle pointing upward, serving as a warning sign. Centered inside the triangle is a white exclamation point. The graphic is low-resolution and pixelated.](.sp2-twl-50m-p1700-1000-10-0529/7487cb9876b1d87d3b5f43a0a09b3c1a368e3e286ba0a5aa1e56d33261b644b2.jpg)

Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption.

![The image displays a standard red warning triangle with a white exclamation point centered inside it.](.sp2-twl-50m-p1700-1000-10-0529/8632664614e9da9c00eec561b3543ca0f6fb70c508929feffbe5007323bb54b7.jpg)

Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan District, Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai, 201203, China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 8-10, 68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.

# Table of Contents

Revision History ..

Preface ..

List of Figures .. .12

1. Introduction .. .13

1.1. Overview... ... 13
1.2. Features .. .... 13
1.3. Package Contents... .. 13
1.4. Optional Accessories... .. 14

2. Block Diagram .. 17

3. Specifications.. .18

4. Mechanical Layout........ ...21

4.1. Mechanical Dimensions. . 21
4.1.1 SP2-10WP-TWL. . 21
4.1.2 SP2-15WP-TWL.. . 22
4.1.3 SP2-21WP-TWL.. . 23

4.2. I/O Panel Connector Locations.. .. 24

4.2.1 Main Board Locations – Top Side .. . 24

4.2.2 Mainboard Connector Locations – Bottom Side . . 25

5. Thermal Options... ..26

5.1. Heatsink Dimensions .. ... 26
5.2. Active Cooling Heatsink... . 27

6. Pinouts and Connectors... ..28

6.1. LAN (I226) LED Status.. . 29

6.2. USB 2.0/CAN.. .. 30

6.3. PCAP ... .. 30

6.4. DC Input Connector ... .. 31

6.5. M.2 A/E Key (for Wireless Module) .. ... 32

6.6. M.2 B Key (for LTE Module or SATA SSD) .. . 33

6.7. MIPI CSI ... ... 34

6.8. Buzzer.. ... 35

6.9. Mic In/Line Out Wafer .. . 35

6.10. Speaker Wafer... .. 36

6.11. Power/Reset/LED Wafer . ..... 36

6.12. Volume/Backlight Wafer ... . 37

6.13. 33 Key Signal.. ... 37

6.14. Fan Wafer... ... 39

6.15. 2nd I2C/SMBus from EC Wafer . . 39

6.16. 1st I2C from SoC Wafer... .. 40

6.17. Back Battery Wafer.. .. 40

6.18. LED Wafer .. .... 41

6.19. COM 1/COM 2... ... 42

6.20. GPIO .... ... 42

6.21. Function Module Board Connector .. ... 47

6.22. Clear CMOS header .. ... 49

7. Getting Started .. ..50

7.1. Adding or Changing Memory ... . 50

7.2. Installing a Wi-Fi-Module .. ... 51

7.3. Installing an LTE Module .. ... 53

7.4. Mounting ... ... 55

7.4.1 Panel Mounting .. ... 56

7.4.2 VESA Mounting.. . 61

8. Driver and Application Installation .... ..62

9. BIOS Setup... ..63

9.1. Main .... ... 64

9.1.1 Menu > BIOS Information.. .. 64

9.1.2 Menu > System Information. .... 64

9.1.3 Menu > Board Information.. ... 65

9.1.4 Menu > System Date and Time.. ... 65

9.2. Advanced .. .... 66

9.2.1 Advanced > CPU Configuration .. .... 66

9.2.2 Advanced > Power Management ... .... 67

9.2.3 Advanced > Graphics Configuration ...... .... 67

9.2.4 Advanced > Super I/O Configuration .. .. 69

9.2.5 Advanced > BIOS Watchdog Timer ... . 72

9.2.6 Advanced > Serial Console Redirection.. . 73

9.2.7 Advanced > Trusted Computing. . 74

9.2.8 Advanced > Hardware Monitor.... ... 74

9.2.9 Advanced > NVMe Configuration... . 75

9.2.10 Advanced > Network Stack Configuration .. ... 76

9.2.11 Advanced > Miscellaneous.. ... 76

9.3. Chipset .. . 77

9.3.1 Chipset > System Agent (SA) Configuration... . 77

9.3.2 Chipset > PCH-I/O Configuration... .. 82

9.4. Security .... ... 85

9.4.1 Security > Secure Boot Menu... . 85

9.5. Boot... .. 86

9.5.1 Boot Configuration.. . 86

9.6. Save & Exit... ... 87

9.6.1 Save Options.. . 87

# List of Figures

Figure 1 – Module function diagram.. .17

Figure 2 – SP2-10WP-TWL mechanical dimensions . ..21

Figure 3 – SP2-15WP-TWL mechanical dimensions .. .22

Figure 4 – SP2-21WP-TWL mechanical dimensions. .23

Figure 5 – I/O panel connector locations (Top) ... ...24

Figure 6 – Mainboard connector locations (Bottom)...... ...25

Figure 7 – Module function diagram......... ...26

Figure 8 – Active cooling heatsink... .27

Figure 11 – SP2-10WP cutout dimensions...... ...56

Figure 12 – SP2-15WP cutout dimensions...... ..57

Figure 13 – SP2-21WP cutout dimensions... .58

Figure 14 – Mounting clip dimensions ...... ..60

# 1. Introduction

# 1.1. Overview

The SP2-TWL Series open-frame panel PC is based on Intel® Core™ Ultra processors, providing flexible I/O options. The SP2-TWL Series is a compactsized solution that offers efficient capabilities, making it easy to integrate into kiosks and panel PC applications.

# 1.2. Features

Intel® Processor N-Series (code name Twin Lake)
• Extensive I/O and function expansion through wire-to-board connectors and custom function modules.
• Comprehensive expansion and customization options for fast and easy integration with all form factors, kiosks, and all-in-one panel PC applications.
• Enhanced protection in case of sudden power outage with support for back-up battery (Optional).
• Pre-compliance EMC testing and high ESD tolerance.
• High reliability in case of power fluctuation, with an optional 9V-36V DC voltage range.
Simple cabling with optional Power Over Ethernet (60W).
• Supports up to 3 displays, including integrated panel, DisplayPort, and USB Type-C (Optional).

# 1.3. Package Contents

Before unpacking, check the shipping carton for any damage. If the shipping carton and/or contents are damaged, inform your dealer immediately. Retain the shipping carton and packing materials for inspection. Obtain authorization from your dealer before returning any products to ADLINK.

Ensure that the following items are included in the package.

1x SP2-TWL Series Smart Panel

# 1.4. Optional Accessories

Adapter and Power Cables

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>60W (12V 5A)</td><td>31-62156-0000-A0</td><td></td></tr><tr><td>84W (12V 7A)</td><td>31-62157-0000-A0</td><td></td></tr><tr><td>Power cable</td><td>30-21863-0000-A0</td><td>Connecting between adapter and mainboard</td></tr></table>

![1\nAdapter\n2\nPower cable](.sp2-twl-50m-p1700-1000-10-0529/105c29cda9fa86bbe2a0265e9d63c539382d2cfc3e580b08f16c8e576c9b6783.jpg)

Panel Mounting Clips

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>SP2/OM-215_Clip_Kits</td><td>91-95337-0010</td><td>With 17 pcs clips</td></tr><tr><td>SP2/OM-156_Clip_Kits</td><td>91-95337-1010</td><td>With 14 pcs clips</td></tr><tr><td>SP2/OM-101_Clip_Kits</td><td>91-95337-2010</td><td>With 8 pcs clips</td></tr></table>

Rear Cover

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>SP2-TWL_215 Rear cover</td><td>91-95394-100E</td><td></td></tr><tr><td>SP2-TWL_101/156 Rear cover</td><td>91-95394-100E</td><td></td></tr><tr><td>VESA bracket</td><td>91-95240-0010</td><td>The VESA bracket screws on rear cover</td></tr></table>

![VESA bracket\nRear cover](.sp2-twl-50m-p1700-1000-10-0529/47f276ebc3a2dafb988df1a58d7e2e4c16d82f77bb9d635932d0a41b5837ca10.jpg)

Wireless Modules

<table><tr><td>Item</td><td>Part Number</td></tr><tr><td>Wi-Fi kit – ENL-R8852BE</td><td>91-95266-400E</td></tr><tr><td>LTE module</td><td>TBD</td></tr></table>

Cables

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>USB 2.0 cable</td><td>30-21348-0000-A0</td><td>Wafer to wafer</td></tr><tr><td>USB 2.0 dongle</td><td>30-21401-0000-A0</td><td>Wafer to USB type A female</td></tr><tr><td>Audio Mic/Line Out Jack cable</td><td>30-22087-0000-A0</td><td>Wafer to 2x 3.5φ phone Jack</td></tr><tr><td>Power/Reset buttons,LED notification</td><td>30-21350-0000-A0</td><td>Wafer to 2x buttons and 1x LED</td></tr><tr><td>GSPI</td><td>30-22282-0000-A0</td><td>Wafer to open end cables</td></tr><tr><td>Power switch</td><td>30-21429-0020-A0</td><td>Wafer to power switch</td></tr><tr><td>LED cable</td><td>30-22249-0000-A0</td><td>Wafer to LEDs</td></tr><tr><td>GPIO cable</td><td>30-21352-0000-A0</td><td>Wafer to open cables</td></tr><tr><td>I2C cable</td><td>30-21353-0000-A0</td><td>Wafer to open cables</td></tr><tr><td>COM port</td><td>30-21862-0010-A0</td><td>Wafer to 1x DB9</td></tr><tr><td>MIPI CSI cable</td><td>TBD</td><td>Coaxial cable</td></tr><tr><td>Buzzer</td><td>23-52111-0A00</td><td>Wafer to 1x buzzer</td></tr><tr><td>Fan</td><td>32-00086-3000-A0</td><td>Wafer to 1x 12V fan</td></tr></table>

Thermal Parts

<table><tr><td>Item</td><td>PN</td><td>Remark</td></tr><tr><td>Fan</td><td>32-00086-3000-A0</td><td>Wafer to 1x 12V fan</td></tr><tr><td>Fan with heatsink</td><td>TBD</td><td>1x heatsink, 1x bracket, 1x fan, 4x screws</td></tr></table>

# 2. Block Diagram

![This block diagram, titled 'SP2-TWL Block diagram' with the ADLINK logo, centers around a blue vertical block labeled **'Intel® Twin lake Processor 6~15W'**.\n\n**Connections from the Processor (Right Side):**\n*   **DDR5 SO-DIMM** (via DDR_CH1)\n*   **MIPI CSI** (via MIPI CSI)\n*   **PCIe x2** (via PCIe #9)\n*   **M.2 E Key** (via USB2 #7)\n*   **PCIe1 / SATA** (via PCIe #11)\n*   **PCIe1 / SATA** (via PCIe #12)\n*   **USB2** (via USB2 #6)\n*   **USB2/USB3** (via USB2 #1 / USB3 #1)\n*   **USB2/USB3** (via USB2 #2 / USB3 #2)\n*   **USB2** (via USB2 #3)\n*   **USB2** (via USB2 #4)\n*   **USB2/TCP1** (via USB2 #5 TCP1)\n*   **USB2** (via USB2 #8)\n*   **I2C** (via I2C5)\n\n**Right-Side Components & Logic:**\n*   **M.2 M Key For NVME or SSD** connects to **PCIe2 / SATA**.\n*   **PCIe1 / SATA** lines connect to a purple **MUX** block.\n*   **M.2 B Key** connects to **Nano USIM** and receives **SATA** from the MUX.\n*   **USB2** connects to a purple **U2 MUX**.\n*   **U2 MUX** connects to **BOM Opt.** and **USB To CAN**, which leads to **Wafer for CAM or CAN**.\n*   **USB2/USB3** lines connect to orange **BOM Opt.** blocks.\n*   **Dual USB3.2 Type A** connects via a green **B2B** block.\n*   **Dual USB2 Type A** connects via a green **B2B** block.\n*   **Type C** block connects via **USB2/TCP1**.\n*   **Wafer for CAP touch** connects via **USB2**.\n*   **Wafer for DIO board** connects via **I2C**.\n*   **SIO NCT5525D** (purple block) connects via **eSPI**.\n    *   It connects to two **SP339E** blocks leading to **Full COM Wafer**.\n    *   It connects to an **80 port** block (purple).\n    *   It connects to a **Fan wafer** block.\n*   **eSPI to LPC Bridge F85227N** connects via **eSPI**.\n*   **EC IT5121** (purple block) connects via **LPC**.\n    *   It connects to **32 KeyPad Wafer**, **UPS Wafer**, **BL/Volume Wafer**, and **Ambient sensor**.\n    *   It connects to a purple **DB40** block.\n\n**Connections from the Processor (Left Side):**\n*   **DDIA** connects to an orange **BOM Opt.** block.\n*   **DDIB** connects to a blue **DP CN** block.\n*   **GPI_A/B** (top right of processor block) - *Correction: Looking closely, it says 'CSI_A/B' near the top right processor output, pointing towards MIPI CSI.*\n*   **GSPI2** connects to an orange **BOM Opt.** block.\n*   **TCP0** connects to a **TCP0** block.\n*   **PCIe #7** connects to a **PCIe** label.\n*   **PCIe #4** connects to an orange **BOM Opt.** block.\n\n**Left-Side Components & Logic:**\n*   **eDP (optional) inside LVDS CN** (eDP 1.4b) connects via **BOM Opt.** and **eDP to LVDS PTN3460**.\n*   **DP CN** (DP 1.4(HBR2)).\n*   **B2B CONN** (Large green vertical block).\n    *   Connected lines: **SPI**, **TCP0 (DP1.4; DP1.4 over USB-C)**, **GPO0*6**, **SML0/I2S**, **I2C**, **SMBUS**.\n    *   Contains **RJ45** and **Wafer for PoE** connected via **BOM Opt.** and **I226** to **PCIe**.\n    *   Contains a purple **PCIe Switch PI7C9X2G4045V** block connected to **PCIe** lines and an orange **BOM Opt.** block.\n*   **Stacked Blocks (Middle Left):**\n    *   **TPM SLB9672**\n    *   **BIOS**\n    *   **DB40**\n    *   These connect via **SPI** and **GPI** (Default) to an orange **BOM Opt.** block.\n*   **Bottom Left Area:**\n    *   **92HD91** (white block) connects via **HDA**.\n    *   **Wafer** (connected to **SPK**) and **Wafer** (connected to **Line Out / MIC IN**) connect to the audio section.\n    *   **EEPROM** connects via **I2C** (**I2C0**).\n    *   **Coin Batt.** (blue circle) connects to a **Wafer** block connected to **RTC**.\n    *   **Wafer** blocks connect to **4DO** and **4DI**.](.sp2-twl-50m-p1700-1000-10-0529/8af757c28548f240a6ef94a74cee16567d54b92cd89ee7293b2a6bcc04210c52.jpg)

Figure 1 – Module function diagram

3. Specifications

<table><tr><td colspan="2" rowspan="2">Model</td><td>93-P1700-20XX</td><td>93-P1700-60XX</td><td>93-P1700-B0XX</td></tr><tr><td>SP2-10WP-TWL</td><td>SP2-15WP-TWL</td><td>SP2-21WP-TWL</td></tr><tr><td>Processor</td><td>Intel® ProcessorN150, 3.6GHz orIntel® CoreTM 3 N355, 3.9GHz</td><td colspan="3">N150</td></tr><tr><td>Memory</td><td>1x SODIMM socket, DDR5 4800 MHzup to 16GB</td><td colspan="3">8GB</td></tr><tr><td rowspan="2">Storage</td><td>1x M.2 SATA M key 2280 slot, support SATA SSD or2280 NVME (PCIe Gen2 x2)</td><td colspan="3">128GB SATA SSD</td></tr><tr><td>1x M.2 B key 2242 SATA SSD</td><td colspan="3"></td></tr><tr><td rowspan="2">Chip</td><td>EC (Optional)</td><td colspan="3"></td></tr><tr><td>TPM 2.0 (Optional)</td><td colspan="3"></td></tr><tr><td rowspan="7">Display</td><td>Size</td><td>10.1"</td><td>15.6"</td><td>21.5"</td></tr><tr><td>Interface</td><td>LVDS</td><td>LVDS</td><td>LVDS</td></tr><tr><td>Resolution</td><td>1280 x 800</td><td>1920 x 1080</td><td>1920 x1080</td></tr><tr><td>Contrast Ratio</td><td>800:1</td><td>1000:1</td><td>1000:1</td></tr><tr><td>Brightness (Nits)</td><td>400</td><td>400</td><td>400</td></tr><tr><td>Backlight Life (Hrs)</td><td>50000</td><td>50000</td><td>50000</td></tr><tr><td>Viewing Angle (U/D/R/L)</td><td>89/89/89/89</td><td>89/89/89/89</td><td>89/89/89/89</td></tr><tr><td rowspan="3">Touch</td><td>Touchscreen</td><td colspan="3">PCAP</td></tr><tr><td>Surface Hardness</td><td colspan="3">7H</td></tr><tr><td>Surface Treatment</td><td colspan="3">Anti-Fingerprint</td></tr><tr><td>Ethernet</td><td>2x GbE (Intel® I226), RJ-45, WOLLAN 1 up to 2.5GBLAN 2, 1GbE</td><td colspan="3">2x 1 GbE LAN</td></tr><tr><td rowspan="3">USB Ports</td><td>2x USB 3.2, Gen 1 (5 Gbps), OCP, Type A</td><td colspan="3">2</td></tr><tr><td>2x USB 2.0, OCP, Type A</td><td colspan="3">2</td></tr><tr><td>1x USB 3.2 Gen 1, Type C (optional)</td><td colspan="3"></td></tr><tr><td rowspan="2">DisplayPort</td><td>1x DisplayPort, DisplayPort++up to 4096x2304@60Hz</td><td colspan="3">1</td></tr><tr><td>1x USB Type C, up to 4096x2304@60Hz</td><td colspan="3"></td></tr><tr><td>USB / CAN</td><td>1x wafer USB 2.0 client or CAN bus</td><td colspan="3">1x USB waferCAN bus (by BOM option)</td></tr><tr><td>COM</td><td>2x wafers RS-232/422/485 programmable, auto flow</td><td colspan="3">2</td></tr><tr><td>MIPI-CSI</td><td>1x connector to support MIPI-CSI 1.8V/3.3V/5V support 1x4 lane or 2x2 lane camera</td><td colspan="3">1</td></tr><tr><td>I2C Wafer</td><td>2x wafers for I2C client</td><td colspan="3">1</td></tr><tr><td rowspan="3">Audio (Optional)</td><td>1x wafer for buzzer</td><td colspan="3">1</td></tr><tr><td>1x wafer for 2x stereo speaker (2 watts)</td><td colspan="3"></td></tr><tr><td>1x wafer for Mic-in and Line-out</td><td colspan="3"></td></tr><tr><td>LED</td><td>1x wafer for Watch dog/SATA LED, 1x load reset button, 3x user define LED</td><td colspan="3">1</td></tr><tr><td rowspan="2">Expansion</td><td>1x M.2 2230 E key for wireless (Wi-Fi/Bluetooth)</td><td colspan="3">1</td></tr><tr><td>1x M.2 3042 B key for 4G module or SSD</td><td colspan="3">1</td></tr><tr><td rowspan="2">Keys Wafer</td><td>1x for 32 physical keys (Optional)</td><td colspan="3"></td></tr><tr><td>1x LCD backlight up/down and volume up/down</td><td colspan="3"></td></tr><tr><td>GPIO</td><td>1x wafer 8-pin GPIO</td><td colspan="3">1</td></tr><tr><td>SPI</td><td>1x wafer for general SPI</td><td colspan="3">1</td></tr><tr><td>Buttons</td><td>1x wafer for Power/Reset button and 1x LED</td><td colspan="3">1</td></tr><tr><td>Fan</td><td>1x wafer for 12V system fan</td><td colspan="3">1</td></tr><tr><td rowspan="3">Power Input</td><td>AT/ATX mode (switch by BIOS)</td><td colspan="3">AT mode</td></tr><tr><td>12V ±5% / 9-36V, both with OVP/UVP protection</td><td colspan="3">12V</td></tr><tr><td>Power saving (power consumption &lt;1W in S5)</td><td colspan="3">Yes</td></tr><tr><td>Power Connector</td><td>1x 6-pin power connector</td><td colspan="3">1</td></tr><tr><td>Backup Batter</td><td>1x wafer to support backup battery to remind power (Optional)</td><td colspan="3"></td></tr><tr><td rowspan="7">Environmental</td><td>Operating Temperature for system</td><td colspan="3">0°C to 60°C</td></tr><tr><td>Storage Temperature</td><td colspan="3">-20°C to 70°C</td></tr><tr><td>Operating Humidity</td><td colspan="3">Up to 95%</td></tr><tr><td>Vibration</td><td colspan="3">5 ~ 500 Hz, 1 Grms for X,Y,Z axes</td></tr><tr><td>Shock</td><td colspan="3">Half sine, 20G, 11ms Refer to IEC 60068-2-27</td></tr><tr><td>IP Rating</td><td colspan="3">Front side IP65</td></tr><tr><td>ESD</td><td colspan="3">Air: ±15kV, Contact: ±8kV, screwing grounding</td></tr><tr><td></td><td>Certifications &amp; Compliance</td><td colspan="3">CE/FCC class BFCC CFR Title 47 Part 15 Subpart BEN 55032:2015 + A11:2020; EN 55035:2017 + A11:2020;BS EN 55032:2015 + A11:2020; BS EN 55035:2017 + A11:2020;AS/NZS CISPR 32:2015 + A1:2020EN 60601-1-2:2015 + A1:2021; IEC 60601-1-2:2014 + A1:2020BS EN 60601-1-2:2015 + A1:2021EN IEC 61000-3-2:2019+A1:2021BS EN IEC 61000-3-2:2019+A1:2021EN 61000-3-3:2013+A1:2019+A2:2021BS EN 61000-3-3:2013+A1:2019+A2:2021EN IEC 61000-6-4:2019 ; EN IEC 61000-6-2:2019BS EN IEC 61000-6-4:2019 ; BS EN IEC 61000-6-2:2019EN 50121-3-2:2016+A1:2019BS EN 50121-3-2:2016+A1:2019</td></tr><tr><td rowspan="2">Software</td><td>WDT</td><td colspan="3">Watch Dog Timer supported</td></tr><tr><td>Operating System</td><td colspan="3">Windows® 11/10, Linux</td></tr><tr><td rowspan="4">Mechanical</td><td>Construction</td><td colspan="3">SGCC</td></tr><tr><td>Dimension (W x L x D)</td><td>249.66 x 168.3 x 64.4 ± 2mm</td><td>383.15 x 232.79 x 65.1 ± 2 mm</td><td>517.46 x 309.19 x 67.6 ± 2 mm</td></tr><tr><td>Weight</td><td>2.06 ± 0.2 kg</td><td>3.02 ± 0.2 kg</td><td>4.85 ± 0.2 kg</td></tr><tr><td>Mounting</td><td colspan="3">1) Panel Mounting2) VESA mounting, support by a rear cover</td></tr></table>

# 4. Mechanical Layout

All dimensions are in millimetres, unless noted.

# 4.1. Mechanical Dimensions

# 4.1.1 SP2-10WP-TWL

![(237.06)](.sp2-twl-50m-p1700-1000-10-0529/af03237a46f46639eab95e62b95b4631328668e7a2e22bdac0c486c5366f5229.jpg)

![249,66 ±2(W)\n168,30 ±2(H)](.sp2-twl-50m-p1700-1000-10-0529/04e1410ad40784311205f25995d9d6192e1fdc509cfd9fa3a2aa89f91f231722.jpg)

![(4.51)\n(58.40)\n64.46 ±2(D)](.sp2-twl-50m-p1700-1000-10-0529/2efe491ea9f6e7882d08756f38941baf7c7f052a04876fdfe2b4e05c5130c297.jpg)

![Top-down view of a computer motherboard showing slots, connectors, and ports (no text or labels visible)](.sp2-twl-50m-p1700-1000-10-0529/f89c15710f20b2d7bb100eb15b5e7420a73836ac48c98a9114c256c72401ddfa.jpg)

![Technical line drawing of a mechanical assembly with multiple components and mounting holes (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/5cef694534eeb5d645a6348b89ef756baa4d0cc74fdaf5c699b818d07dc968b2.jpg)

Figure 2 – SP2-10WP-TWL mechanical dimensions

# 4.1.2 SP2-15WP-TWL

![(370.80)](.sp2-twl-50m-p1700-1000-10-0529/086f91709ec712a636cc1785078eb6dea0d4d1c9271f84c83c92dbfb2e5ad2da.jpg)

![383.56 ±2(W)\n232.99 ±2(H)](.sp2-twl-50m-p1700-1000-10-0529/8eb7e5d14f9b8d3c3fb7f80f81605b2a59ed9b92f915f5094937ea9f000ad841.jpg)

![(5.20)\n65.16 ±2(D)\n(220.60)](.sp2-twl-50m-p1700-1000-10-0529/113ef600494839871dc5a2f950486e6840826ef99a8a883d814a19ca2b0f8848.jpg)

![Top-down schematic of a computer motherboard showing CPU socket, RAM slots, and drive bays (no text or labels)](.sp2-twl-50m-p1700-1000-10-0529/fdb6c5fa1583f519ba55cde37a0edfa647eedc75dce96773ff87047e6716d9ec.jpg)

![Technical line drawing of a mechanical assembly with no visible text or symbols](.sp2-twl-50m-p1700-1000-10-0529/4458bbd53813054cb42ab501590dad647fe5af66aac4f221bd4e491c8fde2872.jpg)

Figure 3 – SP2-15WP-TWL mechanical dimensions

# 4.1.3 SP2-21WP-TWL

![The image displays a technical engineering drawing of an electronic device, presenting five orthographic views with dimensional annotations.\n\n**Views and Dimensions:**\n\n*   **Top View (Top Center):** A horizontal strip showing the top edge of the device with various ports and a row of vertical heat sink fins. A dimension line above it reads **`(504.60)`**.\n*   **Front View (Left):** A large rectangle representing the front face of the device.\n    *   Width dimension above: **`517.46 ±2(W)`**\n    *   Height dimension to the right: **`309.19 ±2(H)`**\n*   **Side View (Center):** A vertical strip showing the side profile with ports.\n    *   Depth dimension at the top: **`67.65 ±2(D)`**\n    *   Height dimension to the right: **`(296.90)`**\n*   **Rear View (Right):** A large rectangle showing the back panel, revealing a motherboard with a large vertical heatsink and mounting points. No text dimensions are present.\n*   **Bottom View (Bottom Right):** A horizontal strip showing the bottom edge with heat sink fins, similar to the top view. No text dimensions are present.](.sp2-twl-50m-p1700-1000-10-0529/a75fb4af60b213425ea546523e9f0d252531ca0631e1e7c5c77ed953e859d858.jpg)
Figure 4 – SP2-21WP-TWL mechanical dimensions

# 4.2. I/O Panel Connector Locations

SP2-TWL provides comprehensive features that can be extended from internal I/O.

# 4.2.1 Main Board Locations – Top Side

Features marked in green are optional. Contact ADLINK sales for more information.

![Backlight\nM.2 B key\nMIPI CSI\nLVDS\nGSPI\nUSB 2.0/CAN\nPCAP\nNano SIM\nSoC\nDDR5 slot\nFunction Module\nBuzzer\nMic in/Line out\nSpeaker\nPower/Reset/LED\nVolume/Backlight\n33 keys signal\nFan\nMDI (for external PoE module)\nType C\nUSB 3.2 Gen 2\nUSB 2.0 dual\nDisplay port\nEthernet](.sp2-twl-50m-p1700-1000-10-0529/3ce12e89bdfd554451f827faefba51e39ad9472ef6457008115367c349789628.jpg)

Figure 5 – I/O panel connector locations (Top)

# 4.2.2 Mainboard Connector Locations – Bottom Side

Features marked in green are optional features. Contact ADLINK sales for more information

![DB40\nGPIO\nI2C (SoC/EC)\nBackup battery\nI2C (SoC)\nLED\nCOM\nCOM\nM.2 M key 2280](.sp2-twl-50m-p1700-1000-10-0529/7595c52d24699d0af32a0c5c1ffbc379ad6efad571dfc56c730bb904f3481ac1.jpg)

Figure 6 – Mainboard connector locations (Bottom)

# 5. Thermal Options

# 5.1. Heatsink Dimensions

![VESA Mount\nRear cover](.sp2-twl-50m-p1700-1000-10-0529/0238c38944e53e858626dc8ec3a4b51e238ab0c1c425818adbf097eb01dd6123.jpg)

Figure 7 – Module function diagram

![A red outline icon of a document or page with the bottom right corner folded. Inside the white space are two horizontal red lines representing text.](.sp2-twl-50m-p1700-1000-10-0529/be5af19fdc7234e72d97b32bc565811e856d09a921209d54c21c8f44710d1d02.jpg)

Note: All dimensions are in millimeters, unless noted. For compact-size panel PCs or space-constrained applications/equipment, the heatsink will need to be redesigned based on the application requirements.

![A yellow triangular warning sign containing a white exclamation mark in the center.](.sp2-twl-50m-p1700-1000-10-0529/ba820cfcbb6ed93dba04b84f928bf418a478dd351f7dee20712bfe5e2b11b12a.jpg)

Caution: Due to radiant heat from the passive heatsink, make sure the heatsink is positioned at least 10 cm from the nearest wall.

# 5.2. Active Cooling Heatsink

SP2-TWL reserves a fan for extreme environments. The optional fan bracket can be assembled on top of the standard heatsink.

![Diagram of a CPU fan with cooling fins and mounting holes, shown in 3D rendering (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/f24ac6fbd4138e7e4e311a94c0ea239ee48279246cdafacb33672d193b9c415d.jpg)

![Technical diagram of a mechanical assembly with mounting flanges and a central component (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/5d772eb220221f2c4ea287caef175535905f43e62f6f1a09079df240df40e4a0.jpg)

Figure 8 – Active cooling heatsink

# 6. Pinouts and Connectors

![USB 3.2\nType C\nUSB 3.2\nType C\nUSB 2.0\nType C\nDisplay port\nLAN\nLAN](.sp2-twl-50m-p1700-1000-10-0529/182c5db47a07d56c7cee992faad130cf94492bbb19e5eb944d6c2f1676424cde.jpg)

<table><tr><td>Connector</td><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>USB 3.2 Type C</td><td>FOXCONN</td><td>UT12113-116B2-7H</td></tr><tr><td>USB 3.2 Type A dual port</td><td>FOXCONN</td><td>UAA111C-84161-4H</td></tr><tr><td>USB 2.0 Type A dual port</td><td>FOXCONN</td><td>UB1112C-8FDE-4F</td></tr><tr><td>DisplayPort</td><td>FOXCONN</td><td>3VD51203-3D6A-7H</td></tr><tr><td>LAN</td><td>UDE</td><td>S22-CL-0057</td></tr><tr><td>LAN</td><td>UDE</td><td>RT7-ZZ-0034</td></tr></table>

# 6.1. LAN (I226) LED Status

The right LED indicates the connection status.

LAN(I226) LED Position on Connector

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Yellow(right LED)</td><td>OFF</td><td>Ethernet port is disconnected.</td></tr><tr><td>ON</td><td>Ethernet port is connected with no activity.</td></tr><tr><td>Flashing</td><td>Ethernet port is connected and active.</td></tr></table>

LAN1/2 Active/Link LED

The Left LED indicates the working speed.

LAN port supports up to 2.5GbE, the default setting is 1GbE.

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Yellow(left LED)</td><td>OFF</td><td>10/100 Mbps</td></tr><tr><td>Green</td><td>1000 Mbps</td></tr><tr><td>Yellow</td><td>2500 Mbps</td></tr></table>

LAN1/2 Speed LED (2.5G)

<table><tr><td>LED Color</td><td>Status</td><td>Description</td></tr><tr><td rowspan="3">Yellow(left LED)</td><td>OFF</td><td>10 Mbps</td></tr><tr><td>Green</td><td>100 Mbps</td></tr><tr><td>Yellow</td><td>1000 Mbps</td></tr></table>

LAN1/2 Speed LED (1G)

Left LED Right LED
![Technical diagram of an electrical connector with internal components and red arrows indicating direction (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/f570dc0c1f0a395a557664a5ca58aca1bd84289b8f59ccad78054d632c80e331.jpg)

# 6.2. USB 2.0/CAN

The internal wafer supports USB 2.0 or CAN bus. The default setting is USB. Contact ADLINK sales if CAN bus support is required.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P5V_U2_CAM</td></tr><tr><td>2</td><td>CN_U2_CAM_N</td></tr><tr><td>3</td><td>CN_U2_CAM_P</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>CON_CAN1_H</td></tr><tr><td>6</td><td>CON_CAN1_L</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.sp2-twl-50m-p1700-1000-10-0529/72a753ed5f65d784d7a3e1af5f241f7120484be6a3e80f1ce2228b593707aa94.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>CST</td><td>CSI-1181-061R-NH</td></tr></table>

# 6.3. PCAP

The internal USB 2.0 connector supports a capacitive touch for panel.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TSC_D+</td></tr><tr><td>3</td><td>TSC_D-</td></tr><tr><td>4</td><td>P5V_U2_TOU</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.sp2-twl-50m-p1700-1000-10-0529/34eb417c09d2331d524f2c60f2f4eae22cfb55c618bd169e1e49e34ab53538e1.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>MOLEX</td><td>53398-0471</td></tr></table>

# 6.4. DC Input Connector

The internal USB 2.0 connector supports a capacitive touch for panel.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>GND</td></tr><tr><td>4</td><td>PWR_CONN_IN</td></tr><tr><td>5</td><td>PWR_CONN_IN</td></tr><tr><td>6</td><td>PWR_CONN_IN</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>CViLux</td><td>CP3506P1V00-NH</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-twl-50m-p1700-1000-10-0529/51d9a6f21438c1a861504d0669bd9a7833630cab2b2e0edcb2b5294d6d4f39ad.jpg)

# 6.5. M.2 A/E Key (for Wireless Module)

The M.2 A/E key with gen3 x2 signal

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>P_+3V3_NGFF_E</td></tr><tr><td>3</td><td>M2E_USB_P</td><td>4</td><td>P_+3V3_NGFF_E</td></tr><tr><td>5</td><td>M2E_USB_N</td><td>6</td><td>NC</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>NC</td><td>10</td><td>NC</td></tr><tr><td>11</td><td>NC</td><td>12</td><td>NC</td></tr><tr><td>13</td><td>NC</td><td>14</td><td>NC</td></tr><tr><td>15</td><td>NC</td><td>16</td><td>NC</td></tr><tr><td>17</td><td>NC</td><td>18</td><td>GND</td></tr><tr><td>19</td><td>NC</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>NC</td><td>22</td><td>NC</td></tr><tr><td>23</td><td>NC</td><td>32</td><td>NC</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>NC</td></tr><tr><td>35</td><td>PCIE9_M2E_TX_P</td><td>36</td><td>NC</td></tr><tr><td>37</td><td>PCIE9_M2E_TX_N</td><td>38</td><td>TEST POINT</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>TEST POINT</td></tr><tr><td>41</td><td>PCH_PCIE9_RX_P</td><td>42</td><td>TEST POINT</td></tr><tr><td>43</td><td>PCH_PCIE9_RX_N</td><td>44</td><td>NC</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td></tr><tr><td>47</td><td>C_PCIECLK3_100M_P</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>C_PCIECLK3_100M_N</td><td>50</td><td>NC</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>M2E_PLTRST_BUF-L</td></tr><tr><td>53</td><td>PCH_CLK_REQ_P3_N</td><td>54</td><td>Pull up 10K ohm to P_+3V3_NGFF_E</td></tr><tr><td>55</td><td>PCH_PCIE_M2E_WAKE-L</td><td>56</td><td>Pull up 10K ohm to P_+3V3_NGFF_E</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>PCH_SMB_DAT_A</td></tr><tr><td>59</td><td>PCIE10_M2E_TX_P</td><td>60</td><td>PCH_SMB_CLK_A</td></tr><tr><td>61</td><td>PCIE10_M2E_TX_N</td><td>62</td><td>PCH_SMB_ALERT_N_3V3</td></tr><tr><td>63</td><td>GND</td><td>64</td><td>NC</td></tr><tr><td>65</td><td>PCH_PCIE10_RX_P</td><td>66</td><td>NC</td></tr><tr><td>67</td><td>PCH_PCIE10_RX_N</td><td>68</td><td>NC</td></tr><tr><td>69</td><td>GND</td><td>70</td><td>NC</td></tr><tr><td>71</td><td>NC</td><td>72</td><td>P_+3V3_NGFF_E</td></tr></table>

<table><tr><td>73</td><td>NC</td><td>74</td><td>P_+3V3_NGFF_E</td></tr><tr><td>75</td><td>GND</td><td></td><td></td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>FOXCONN</td><td>2E0BC21-S85BE-7H</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-twl-50m-p1700-1000-10-0529/5475bf52b142014198222a06b860c036bbf6325e4e3791c959b7410ba2a1892e.jpg)

# 6.6. M.2 B Key (for LTE Module or SATA SSD)

The M.2 A/E key with gen3 x2 signal

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>M2B_CONFIG_3</td><td>2</td><td>P_+3V3_NGFF_B</td></tr><tr><td>3</td><td>GND</td><td>4</td><td>P_+3V3_NGFF_B</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>Pull up 10K ohm to P_+3V3_NGFF_B</td></tr><tr><td>7</td><td>U2_USB6_P_CN</td><td>8</td><td>Pull up 10K ohm to P_+3V3_NGFF_B</td></tr><tr><td>9</td><td>U2_USB6_N_CN</td><td>10</td><td>M2B_SATALED-L</td></tr><tr><td>11</td><td>GND</td><td>20</td><td>NC</td></tr><tr><td>21</td><td>M2B_CONFIG_0</td><td>22</td><td>NC</td></tr><tr><td>23</td><td>NC</td><td>24</td><td>NC</td></tr><tr><td>25</td><td>NC</td><td>26</td><td>NC</td></tr><tr><td>27</td><td>GND</td><td>28</td><td>NC</td></tr><tr><td>29</td><td>PCIE3_M2B_RX_N</td><td>30</td><td>M2_UIM_RST</td></tr><tr><td>31</td><td>PCIE3_M2B_RX_P</td><td>32</td><td>M2_UIM_CLK</td></tr><tr><td>33</td><td>GND</td><td>34</td><td>M2_UIM_DATA</td></tr><tr><td>35</td><td>PCIE3_M2B_TX_N</td><td>36</td><td>P_+3V3_UIM_M2</td></tr><tr><td>37</td><td>PCIE3_M2B_TX_P</td><td>38</td><td>NC</td></tr><tr><td>39</td><td>GND</td><td>40</td><td>NC</td></tr><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>41</td><td>MUX_SATA1_RX_P_R</td><td>42</td><td>NC</td></tr><tr><td>43</td><td>MUX_SATA1_RX_N_R</td><td>44</td><td>NC</td></tr><tr><td>45</td><td>GND</td><td>46</td><td>NC</td></tr><tr><td>47</td><td>MUX_SATA1_TX_N_R</td><td>48</td><td>NC</td></tr><tr><td>49</td><td>MUX_SATA1_TX_P_R</td><td>50</td><td>M2B_PLTRST_BUF-L</td></tr><tr><td>51</td><td>GND</td><td>52</td><td>PCH_CLK_REQ_P0_N</td></tr><tr><td>53</td><td>C_PCIECLK0_100M_N</td><td>54</td><td>PCH_PCIE_M2B_WAKE-L</td></tr><tr><td>55</td><td>C_PCIECLK0_100M_P</td><td>56</td><td>NC</td></tr><tr><td>57</td><td>GND</td><td>58</td><td>NC</td></tr><tr><td>59</td><td>NC</td><td>60</td><td>NC</td></tr><tr><td>61</td><td>NC</td><td>62</td><td>NC</td></tr><tr><td>63</td><td>NC</td><td>64</td><td>NC</td></tr><tr><td>65</td><td>NC</td><td>66</td><td>M2_UIM1_DET</td></tr><tr><td>67</td><td>WWAN_RESET-L</td><td>68</td><td>NC</td></tr><tr><td>69</td><td>M2B_CONFIG_1</td><td>70</td><td>P_+3V3_NGFF_B</td></tr></table>

<table><tr><td>71</td><td>GND</td><td>72</td><td>P_+3V3_NGFF_B</td></tr><tr><td>73</td><td>GND</td><td>74</td><td>P_+3V3_NGFF_B</td></tr><tr><td>75</td><td>M2B_CONFIG_2</td><td></td><td></td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>FOXCONN</td><td>2E0BC21-S85BB-7H</td></tr></table>

![Simple line drawing of a rectangular container with a small semicircular object inside, placed above a horizontal surface with no text or symbols.](.sp2-twl-50m-p1700-1000-10-0529/95625b38799a56f78307688a9198837a3441bd294f4353155f50b4a99237779a.jpg)

# 6.7. MIPI CSI

The MIPI CSI is only support on Linux.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>21</td><td>MIPI_CSI1_CLK_EN</td></tr><tr><td>2</td><td>MIPI_CSI1_D2_P</td><td>22</td><td>MIPI_CSI1_RST_N_1V8</td></tr><tr><td>3</td><td>MIPI_CSI1_D2_N</td><td>23</td><td>MIPI_CSI1_RST_N</td></tr><tr><td>4</td><td>GND</td><td>24</td><td>GND</td></tr><tr><td>5</td><td>MIPI_CSI1_D0_N</td><td>25</td><td>VDD_1V8_MIPI</td></tr><tr><td>6</td><td>MIPI_CSI1_D0_P</td><td>26</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>27</td><td>P_3V3_A_MIPI</td></tr><tr><td>8</td><td>MIPI_CSI1_CLK_N</td><td>28</td><td>P_3V3_A_MIPI</td></tr><tr><td>9</td><td>MIPI_CSI1_CLK_P</td><td>29</td><td>P_+3V8_A_MIPI</td></tr><tr><td>10</td><td>GND</td><td>30</td><td>GND</td></tr><tr><td>11</td><td>MIPI_CSI1_D1_N</td><td>31</td><td>PCH_I2C2_SDA_1V8</td></tr><tr><td>12</td><td>MIPI_CSI1_D1_P</td><td>32</td><td>GND</td></tr><tr><td>13</td><td>GND</td><td>33</td><td>PCH_I2C2_SCL_1V8</td></tr><tr><td>14</td><td>MIPI_CSI1_D3_N</td><td>34</td><td>GND</td></tr><tr><td>15</td><td>MIPI_CSI1_D3_P</td><td>35</td><td>GND</td></tr><tr><td>16</td><td>GND</td><td>36</td><td>MIPI_CSI1_MCLK</td></tr><tr><td>17</td><td>MIPI_CSIA_CLK_N</td><td>37</td><td>GND</td></tr><tr><td>18</td><td>MIPI_CSIA_CLK_P</td><td>38</td><td>P_5V_A_MIPI</td></tr><tr><td>19</td><td>TEST POINT</td><td>39</td><td>P_5V_A_MIPI</td></tr><tr><td>20</td><td>TEST POINT</td><td>40</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>ACES</td><td>50473-0400M-001</td></tr></table>

![Pure technical line drawing of a mechanical component without any text, numbers, or symbols](.sp2-twl-50m-p1700-1000-10-0529/a436482531f586c2daa962d4632aea1707a81b8b35efe1ac7bd6517dec02f929.jpg)

# 6.8. Buzzer

The internal USB 2.0 connector supports a capacitive touch for panel.

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GSPI_TOUCH_INT-L</td></tr><tr><td>2</td><td>PCH_GSPI1_MISO_3V3</td></tr><tr><td>3</td><td>PCH_GSPI1_MOSI_3V3</td></tr><tr><td>4</td><td>PCH_GSPI1_CS0-L_3V3</td></tr><tr><td>5</td><td>PCH_GSPI1_CLK_3V3</td></tr><tr><td>6</td><td>GND</td></tr></table>

![Pure mechanical component diagram without any text, numbers, or symbols](.sp2-twl-50m-p1700-1000-10-0529/52ac55756dc3a95b2654beaabcbe551ded30d3d3fe500e737119a9a0c7208f5f.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>JVE</td><td>24W1125A-02M00-01T-1-CF01</td></tr></table>

# 6.9. Mic In/Line Out Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CON_MIC1_IN</td></tr><tr><td>2</td><td>CON_LINE1_OUT_L</td></tr><tr><td>3</td><td>CON_LINE1_OUT_R</td></tr><tr><td>4</td><td>LINE1_OUT_JD</td></tr><tr><td>5</td><td>AGND_AUDIO</td></tr></table>

![Pure electrical connector diagram without any text, numbers, or symbols](.sp2-twl-50m-p1700-1000-10-0529/3f1cafbd1943a2e8e21fce7cfd8b37698e36d570c0cdd49d1329b65823992a07.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>MOLEX</td><td>53398-0571</td></tr></table>

# 6.10. Speaker Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>AMP_L+</td></tr><tr><td>2</td><td>AMP_L-</td></tr><tr><td>3</td><td>AMP_L-</td></tr><tr><td>4</td><td>AMP_R-</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>MOLEX</td><td>53398-0471</td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-twl-50m-p1700-1000-10-0529/0c7442d2c218abffba44dabd08c6b395cc04040844f55b8b56fbd22a58254fc4.jpg)

# 6.11. Power/Reset/LED Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_A</td></tr><tr><td>2</td><td>PWRBTN-L_R</td></tr><tr><td>3</td><td>RSTBTN-L_R</td></tr><tr><td>4</td><td>SIG_PWRLED-L</td></tr><tr><td>5</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>MOLEX</td><td>53398-0571</td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-twl-50m-p1700-1000-10-0529/b468bc2d035d0cf6a6f0b6bfc6fe52557d77337e8a38d1aecc063097827dcac2.jpg)

# 6.12. Volume/Backlight Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_S0</td></tr><tr><td>2</td><td>EC_BTN_33</td></tr><tr><td>3</td><td>EC_BTN_34</td></tr><tr><td>4</td><td>EC_BTN_35</td></tr><tr><td>5</td><td>EC_BTN_36</td></tr><tr><td>6</td><td>GND</td></tr></table>

![The image is a black-and-white line drawing of a technical diagram, likely representing an electronic connector or integrated circuit package. It is oriented vertically.\n\nThe central part of the drawing is a long, vertical rectangular block. Along the left edge of this block is a single vertical column of ten small square shapes, representing pins or contacts. Along the right edge of the central block are two vertical columns of ten small rectangular shapes each.\n\nAt the top and bottom of the drawing are larger rectangular blocks that appear to be part of the connector's shell or housing. Small square notches or alignment features are visible near the corners of the central block, adjacent to the top and bottom housing sections.\n\nThere is no visible text, numbers, or legends in the image.](.sp2-twl-50m-p1700-1000-10-0529/a52da2b29365e646a6cf1dfa34460f75fc9bc8505a9f9a778caca7f775633d42.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>JVE</td><td>24W1125A-06S10-01T-0.5-CF01</td></tr></table>

# 6.13. 33 Key Signal

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>2</td><td>P_+3V3_S0</td></tr><tr><td>3</td><td>EC_BTN_17</td><td>4</td><td>EC_BTN_1</td></tr><tr><td>5</td><td>EC_BTN_18</td><td>6</td><td>EC_BTN_2</td></tr><tr><td>7</td><td>EC_BTN_19</td><td>8</td><td>EC_BTN_3</td></tr><tr><td>9</td><td>EC_BTN_20</td><td>10</td><td>EC_BTN_4</td></tr><tr><td>11</td><td>EC_BTN_21</td><td>12</td><td>EC_BTN_5</td></tr><tr><td>13</td><td>EC_BTN_22</td><td>14</td><td>EC_BTN_6</td></tr><tr><td>15</td><td>EC_BTN_23</td><td>16</td><td>EC_BTN_7</td></tr><tr><td>17</td><td>EC_BTN_24</td><td>18</td><td>EC_BTN_8</td></tr><tr><td>19</td><td>EC_BTN_25</td><td>20</td><td>EC_BTN_9</td></tr><tr><td>21</td><td>EC_BTN_26</td><td>22</td><td>EC_BTN_10</td></tr><tr><td>23</td><td>EC_BTN_27</td><td>24</td><td>EC_BTN_11</td></tr><tr><td>25</td><td>EC_BTN_28</td><td>26</td><td>EC_BTN_12</td></tr><tr><td>27</td><td>EC_BTN_29</td><td>28</td><td>EC_BTN_13</td></tr><tr><td>29</td><td>EC_BTN_30</td><td>30</td><td>EC_BTN_14</td></tr><tr><td>31</td><td>EC_BTN_31</td><td>32</td><td>EC_BTN_15</td></tr></table>

![Pure electrical connector pinout diagram without any text or symbols](.sp2-twl-50m-p1700-1000-10-0529/3854f9bed0df34206b784b3292641660e311488ccba90db3f7a5ecb45e544aee.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>HIROSE</td><td>DF20EF-40DP-1V(52)</td></tr></table>

<table><tr><td>Pin</td><td>Signal</td><td>Function Value</td><td>Pin</td><td>Signal</td><td>Function Value</td></tr><tr><td>1</td><td>GND</td><td>N/A</td><td>2</td><td>P_+3V3_S0</td><td>N/A</td></tr><tr><td>3</td><td>EC_BTN_17</td><td>Tab</td><td>4</td><td>EC_BTN_1</td><td>↑</td></tr><tr><td>5</td><td>EC_BTN_18</td><td>Backspace</td><td>6</td><td>EC_BTN_2</td><td>↓</td></tr><tr><td>7</td><td>EC_BTN_19</td><td>Delete</td><td>8</td><td>EC_BTN_3</td><td>→</td></tr><tr><td>9</td><td>EC_BTN_20</td><td>Space</td><td>10</td><td>EC_BTN_4</td><td>←</td></tr><tr><td>11</td><td>EC_BTN_21</td><td>Page Up</td><td>12</td><td>EC_BTN_5</td><td>0</td></tr><tr><td>13</td><td>EC_BTN_22</td><td>Page Down</td><td>14</td><td>EC_BTN_6</td><td>1</td></tr><tr><td>15</td><td>EC_BTN_23</td><td>F1</td><td>16</td><td>EC_BTN_7</td><td>2</td></tr><tr><td>17</td><td>EC_BTN_24</td><td>F2</td><td>18</td><td>EC_BTN_8</td><td>3</td></tr><tr><td>19</td><td>EC_BTN_25</td><td>F3</td><td>20</td><td>EC_BTN_9</td><td>4</td></tr><tr><td>21</td><td>EC_BTN_26</td><td>F4</td><td>22</td><td>EC_BTN_10</td><td>5</td></tr><tr><td>23</td><td>EC_BTN_27</td><td>F5</td><td>24</td><td>EC_BTN_11</td><td>6</td></tr><tr><td>25</td><td>EC_BTN_28</td><td>F6</td><td>26</td><td>EC_BTN_12</td><td>7</td></tr><tr><td>27</td><td>EC_BTN_29</td><td>F7</td><td>28</td><td>EC_BTN_13</td><td>8</td></tr><tr><td>29</td><td>EC_BTN_30</td><td>F8</td><td>30</td><td>EC_BTN_14</td><td>9</td></tr><tr><td>31</td><td>EC_BTN_31</td><td>F9</td><td>32</td><td>EC_BTN_15</td><td>Enter</td></tr><tr><td>33</td><td>EC_BTN_32</td><td>F10</td><td>34</td><td>EC_BTN_16</td><td>Esc</td></tr><tr><td>35</td><td>EC_BTN_37</td><td></td><td>36</td><td>NC</td><td></td></tr><tr><td>37</td><td>NC</td><td></td><td>38</td><td>P_+3V3_A</td><td></td></tr><tr><td>39</td><td>NC</td><td></td><td>40</td><td>P_+3V3_A</td><td></td></tr></table>

# 6.14. Fan Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>FAN_PWR_IN</td></tr><tr><td>3</td><td>SIO_FANIN1_CN</td></tr><tr><td>4</td><td>SIO_PWM_DAC1_CN</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>MOLEX</td><td>53398-0471</td></tr></table>

# 6.15. 2nd I2C/SMBus from EC Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_I2C2</td></tr><tr><td>2</td><td>P_+3V3_I2C2</td></tr><tr><td>3</td><td>2ND_SDA</td></tr><tr><td>4</td><td>2ND_SCL</td></tr><tr><td>5</td><td>2ND_INT</td></tr><tr><td>6</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>JVE</td><td>24W1125A-06M00-01T-1-CF01</td></tr></table>

![Technical line drawing of an integrated circuit chip with multiple pins (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/70f89e9f6af7ae90534d59bba1c40633306ba1a2a44f9674aeaa01092813ef00.jpg)

# 6.16. 1st I2C from SoC Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+5V_I2C2</td></tr><tr><td>2</td><td>P_+3V3_I2C2</td></tr><tr><td>3</td><td>2ND_SDA</td></tr><tr><td>4</td><td>2ND_SCL</td></tr><tr><td>5</td><td>2ND_INT</td></tr><tr><td>6</td><td>GND</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>JVE</td><td>24W1125A-06M00-01T-1-CF01</td></tr></table>

![Technical line drawing of an integrated circuit package with multiple pins (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/24a69d909c62d0e0e4eecb0304d7eab79a02d56031dd62584ab9600a0fa610e5.jpg)

# 6.17. Back Battery Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>CHG_PWR</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>CHG_SMBCLK</td></tr><tr><td>4</td><td>CHG_SMBDAT</td></tr><tr><td>5</td><td>SMB_ALERT-L_R</td></tr><tr><td>6</td><td>DCIN_DET</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>JVE</td><td>24W1125A-06M00-01T-1-CF01</td></tr></table>

![The image displays a technical line drawing of a rectangular electronic component, resembling a connector housing. On the left vertical face, there is a column of eight curved, vertical slots. On the right vertical face, there is a corresponding column of eight small, rectangular tabs or contacts. The top and bottom ends of the component feature cylindrical shapes. There is no text present in the image.](.sp2-twl-50m-p1700-1000-10-0529/db08072d8d90390287394b8f062ef0aa473f56c3cc8f6c33739048fd347637fd.jpg)

# 6.18. LED Wafer

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>STDBY_PWR</td></tr><tr><td>3</td><td>GP3_LED-L</td></tr><tr><td>4</td><td>GP2_LED-L</td></tr><tr><td>5</td><td>GP1_LED-L</td></tr><tr><td>6</td><td>P_+3V3_A</td></tr><tr><td>7</td><td>BIOS_LOAD_DEFAULT_L</td></tr><tr><td>8</td><td>GND</td></tr><tr><td>9</td><td>NC</td></tr><tr><td>10</td><td>NC</td></tr><tr><td>11</td><td>CN_SATA_LED-L_R</td></tr><tr><td>12</td><td>P_+3V3_S0</td></tr><tr><td>13</td><td>CN_WDT_LED-L</td></tr><tr><td>14</td><td>P_+3V3_A</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-twl-50m-p1700-1000-10-0529/1a39ab8b7e5eabf770493e08be67868450d00b0c0ecf68bbc454c0bdc473e0fb.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td></tr><tr><td>CST</td><td>CSI-1182-141R-NH</td></tr></table>

# 6.19. COM 1/COM 2

<table><tr><td>Pin</td><td>Signal</td><td>RS232</td><td>RS422</td><td>RS485</td></tr><tr><td>1</td><td>COM1_DCD-L_CN</td><td>DCD#</td><td>TXD422-</td><td>485DATA-</td></tr><tr><td>2</td><td>COM1_RXD_CN</td><td>RXD</td><td>TXD422+</td><td>485DATA+</td></tr><tr><td>3</td><td>COM1_TXD_CN</td><td>TXD</td><td>RXD422+</td><td>NC</td></tr><tr><td>4</td><td>COM1_DTR-L_CN</td><td>DTR#</td><td>RXD422-</td><td>NC</td></tr><tr><td>5</td><td>GND</td><td>GND</td><td>NC</td><td>NC</td></tr><tr><td>6</td><td>COM1_DSR-L_CN</td><td>DSR#</td><td>NC</td><td>NC</td></tr><tr><td>7</td><td>COM1_RTS-L_CN</td><td>RTS#</td><td>NC</td><td>NC</td></tr><tr><td>8</td><td>COM1_CTS-L_CN</td><td>CTS#</td><td>NC</td><td>NC</td></tr><tr><td>9</td><td>COM1_RI-L_CN</td><td>RI#</td><td>NC</td><td>NC</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr></table>

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>MOLEX</td><td>53261-1071</td><td>61-6AJ03-1100</td></tr></table>

![Technical line drawing of a mechanical component with multiple pins (no text or symbols)](.sp2-twl-50m-p1700-1000-10-0529/4a260eda3e16f3c34d2329fbe1820babaec5f9451d66cafe9460e6c2a7bf62fc.jpg)

# 6.20. GPIO

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+3V3_S0</td></tr><tr><td>2</td><td>CN_DI0</td></tr><tr><td>3</td><td>CN_DI1</td></tr><tr><td>4</td><td>CN_DI2</td></tr><tr><td>5</td><td>CN_DI3</td></tr><tr><td>6</td><td>CN_DO0</td></tr><tr><td>7</td><td>CN_DO1</td></tr><tr><td>8</td><td>CN_DO2</td></tr><tr><td>9</td><td>CN_DO3</td></tr><tr><td>10</td><td>GND</td></tr></table>

![Pure electrical component diagram without any text, numbers, or symbols](.sp2-twl-50m-p1700-1000-10-0529/fe65dd9c23bcd6768dfbd066e1bbb05683635a47a72460c609bbcee713186882.jpg)

<table><tr><td>Manufacturer</td><td>MAFG P/N</td><td>ADLINK P/N</td></tr><tr><td>HIROSE</td><td>DF13-10P-1.25H</td><td>61-66J05-1100</td></tr></table>

This device provides 4 channels of non-isolation digital input and 4 channels of non-isolation digital output circuits.

# 4-channel Digital Input

VIH: 2 to 5.25V
VIL: 0 to 0.8V

# 4-channel Digital Output

• Output type: open drain N-channel
• MOSFET driver with internal pull-high of 200Ω resistance
• Source/Sink current for all channels: 22mA
VOH: 2.4 to 5V
• VOL: 0 to 0.55V

GPIO Connector Pin Voltage

<table><tr><td>Pin</td><td>Signal</td><td>PCH GPIO</td><td>Default Value</td><td>Input/Output Voltage Range</td></tr><tr><td>1</td><td>P_+3V3_S0</td><td></td><td></td><td></td></tr><tr><td>2</td><td>CN_DI0</td><td>GP_B02</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>3</td><td>CN_DI1</td><td>GP_B03</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>4</td><td>CN_DI2</td><td>GP_B18</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>5</td><td>CN_DI3</td><td>GP_B19</td><td>Input</td><td>VIH: 2 VVIL: 0.8V</td></tr><tr><td>6</td><td>CN_DO0</td><td>GP_D05</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>7</td><td>CN_DO1</td><td>GP_D06</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>8</td><td>CN_DO2</td><td>GP_D07</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>9</td><td>CN_DO3</td><td>GP_D08</td><td>Output</td><td>VOH: 2.4VVOL: 0.55V</td></tr><tr><td>10</td><td>GND</td><td></td><td></td><td></td></tr></table>

Digital Circuit
![Digital Input Circuit\n| Circuit | Power (V) |\n| :--- | :--- |\n| DI_IN | +3.3V |\n| DI_GND | 100kΩ |\n| DI_IN_GND | G |\n| DI_IN_GND_GND | S |\n| DI_IN_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GN |\n| DI_IN_GND | 2.2kΩ |\n| DI_IN_GND_GND | G |\n| DI_IN_GND_GND | S |\n| DI_IN_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GN |\n| DI_IN_GND | +3.3V |\n| DI_IN_GND_GND | 2.2kΩ |\n| DI_IN_GND_GND | 200Ω |\n| DI_IN_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GND_GN |\n| DI_IN_GND_GDIN | +3.3V |\n| DI_IN_GDIN | 2.2kΩ |\n| DI_IN_GDIN | 200Ω |\n| DI_IN_GDIN | G |\n| DI_IN_GDIN | S |\n| DI_IN_GDIN_GDIN | S |\n| DI_IN_GDIN_GDIN | S |\n| DI_IN_GDIN_GDIN_GDIN | S |\n| DI_IN_SOLED | +3.3V |\n| DI_IN_SOLED | 2.2kΩ |\n| DI_IN_SOLED | 200Ω |\n| DI_IN_SOLED | G |\n| DI_IN_SOLED | S |\n| DI_IN_SOLED_GDIN | +3.3V |\n| DI_IN_SOLED_GDIN | 2.2kΩ |\n| DI_IN_SOLED_GDIN | 200Ω |\n| DI_IN_SOLED_GDIN | G |\n| DI_IN_SOLED_DON | +3.3V |\n| DI_IN_SOLED_DON | 2.2kΩ |\n| DI_IN_SOLED_DON | 200Ω |\n| DI_IN_SOLED_DON | G |\n| DI_IN_SOLED_DON | S |\n| DI_IN_SOLED_DON-GDIN | +3.3V |\n| DI_IN_SOLED_DON-GDIN | 2.2kΩ |\n| DI_IN_SOLED_DON-GDIN | 200Ω |\n| DI_IN_SOLED_DON-GDIN | G |\n| DI_IN_SOLED_DON-GDIN | S |\n| DI_IN_SOLED_DON-GDIN_GDIN | S |\n| DI_IN_SOLED_DON-GDIN_DON-GDIN | S |\n| DI_IN_SOLED_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GD100kΩ | +3.3V |\n| DI_IN_SOLED | +3.3V |\n| DI_IN_SOLED_GDIN | +3.3V |\n| DI_IN_SOLED_DGIND | +3.3V |\n| DI_IN_SOLED_MOS | +3.3V |\n| DI_IN_SOLED_DON | +3.3V |\n| DI_IN_SOLED_DON-GDIN | +3.3V |\n| DI_IN_SOLED_DON_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIN_DON-GDIDN | +3.3V |\n| DI_IN_SOLED | +3.3V |\n| DI_IN_SOLED_GDIN | +3.3V |\n| DI_IN_SOLED_DGIND | +3.3V |\n| DI_IN_SOLED_MOS | +3.3V |\n| DI_IN_SOLED_DON | +3.3V |\n| DI_IN_SOLED_DON-GDIN | +3.3V |](.sp2-twl-50m-p1700-1000-10-0529/338e6d3eb5feb015b6e64c557a578eb0ae241f714fb00305129c160d1e004554.jpg)

GPIO Address

<table><tr><td>Net name</td><td>PCH_GPIO</td><td>Address</td></tr><tr><td>PCH_DO0_1V8</td><td>GPP_D05</td><td>0XE0D507E0</td></tr><tr><td>PCH_DO1_1V8</td><td>GPP_D06</td><td>0XE0D507F0</td></tr><tr><td>PCH_DO2_1V8</td><td>GPP_D07</td><td>0XE0D50800</td></tr><tr><td>PCH_DO3_1V8</td><td>GPP_D08</td><td>0XE0D50810</td></tr><tr><td>PCH_DI0_1V8</td><td>GPP_B02</td><td>0XE0D50620</td></tr><tr><td>PCH_DI1_1V8</td><td>GPP_B03</td><td>0XE0D50630</td></tr><tr><td>PCH_DI2_1V8</td><td>GPP_B18</td><td>0XE0D50720</td></tr><tr><td>PCH_DI3_1V8</td><td>GPP_B19</td><td>0XE0D50730</td></tr></table>

![The diagram displays a pin mapping list with three columns of text connected by red lines and arrows. The text is organized into five distinct sections.\n\n**Section 1**\n*   **Left Block:** `GPP_D06/ISH_UART0_TXD/ISH_SPI_CLK/SML0BCLK/USB-C_GPP_D06` connects via middle label **EH20** to right block **PCH_DO1_1V8 (24)**.\n*   **Left Block:** `GPP_D05/ISH_UART0_RXD/ISH_SPI_CS/SML0BDATA/USB-C_GPP_D05` connects via middle label **ER20** to right block **PCH_DO0_1V8 (24)**.\n*   **Left Block:** `GPP_D08/ISH_UART0_CTS/ISH_SPI_MOSI/SML0BALERT/USB-C_GPP_D08` connects via middle label **EN20** to right block **PCH_DO3_1V8 (24)**.\n*   **Left Block:** `GPP_D07/IMGCLKOUT4/ISH_UART0_RTS/ISH_SPI_MISO/USB-C_GPP_D07` connects via middle label **EK20** to right block **PCH_DO2_1V8 (24)**.\n\n**Section 2**\n*   **Left Block:** `GPP_H15/ISH_UART1_TXD/UART1A_TXD/ISH_I2C1_SCL/USB-C_GPP_H15` connects via middle label **EH38**.\n*   **Left Block:** `GPP_H14/ISH_UART1_RXD/UART1A_RXD/ISH_I2C1_SDA/USB-C_GPP_H14` connects via middle label **EN38** (marked with a red 'x'). No right-side connections are shown for this section.\n\n**Section 3**\n*   **Left Block:** `GPP_B03/ISH_I2C0_SCL/ISH_I3C0_SCL/I2C2A_SCL/USB-C_GPP_B03` connects via middle label **EH23** to right block **PCH_DI1_1V8 (24)**.\n*   **Left Block:** `GPP_B02/ISH_I2C0_SDA/ISH_I3C0_SDA/I2C2A_SDA/USB-C_GPP_B02` connects via middle label **EN23** to right block **PCH_DI0_1V8 (24)**.\n\n**Section 4**\n*   **Left Block:** `GPP_B19/ISH_I2C2_SCL/I2C4A_SCL/USB-C_GPP_B19` connects via middle label **ER25** to right block **PCH_DI3_1V8 (24)**.\n*   **Left Block:** `GPP_B18/ISH_I2C2_SDA/I2C4A_SDA/USB-C_GPP_B18` connects via middle label **ER28** to right block **PCH_DI2_1V8 (24)**.\n\n**Section 5**\n*   **Left Block:** `GPP_B04/BK0/ISH_GP4/SBK0/USB-C_GPP_B04` connects via middle label **EN31** (labeled with floating text **GP_B04_PIN_STRAP**) to right block **GP_B04_PIN_STRAP (21)**.\n*   **Left Block:** `GPP_B08/BK4/ISH_GP3/SBK4/USB-C_GPP_B08` connects via middle label **EL28** to right block **LCD_CFG_LVDS_CLR_1V8 (24)**.\n*   **Left Block:** `GPP_B07/BK3/ISH_GP2/SBK3/USB-C_GPP_B07` connects via middle label **EN28** to right block **LCD_CFG_LVDS_FMT_1V8 (24)**.\n*   **Left Block:** `GPP_B06/BK2/ISH_GP1/SBK2/USB-C_GPP_B06` connects via middle label **EF25** to right block **LCD_CFG_LVDS_CNL_1V8 (24)**.\n*   **Left Block:** `GPP_B05/BK1/ISH_GP0/SBK1/USB-C_GPP_B05` connects via middle label **EH25** to right block **A_SPKR_1V8 (24)**.](.sp2-twl-50m-p1700-1000-10-0529/409f9b385686a7e29ae82bf433fe923e12ef386b670419f260bce16c6a1fdd95.jpg)

# [Bit definition]

Bit 1-Rx state, 1/0 represents high/low

Bit -Tx state, set to 1 for output high

# 6.21. Function Module Board Connector

The function module allows customized expandability of the device. Contact your ADLINK representative for details.

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>P_+12V_A</td><td>2</td><td>P_+12V_A</td></tr><tr><td>3</td><td>P_+12V_A</td><td>4</td><td>P_+12V_A</td></tr><tr><td>5</td><td>GND</td><td>6</td><td>GND</td></tr><tr><td>7</td><td>GND</td><td>8</td><td>GND</td></tr><tr><td>9</td><td>P_+5V_A</td><td>10</td><td>P_+5V_A</td></tr><tr><td>11</td><td>P_+5V_A</td><td>12</td><td>P_+5V_A</td></tr><tr><td>13</td><td>GND</td><td>14</td><td>GND</td></tr><tr><td>15</td><td>GND</td><td>16</td><td>GND</td></tr><tr><td>17</td><td>P_+3V3_A</td><td>18</td><td>P_+3V3_A</td></tr><tr><td>19</td><td>P_+3V3_A</td><td>20</td><td>P_+3V3_A</td></tr><tr><td>21</td><td>GND</td><td>22</td><td>GND</td></tr><tr><td>23</td><td>GND</td><td>24</td><td>GND</td></tr><tr><td>25</td><td>PCH_SLP_S3-L</td><td>26</td><td>PCH_I2C1_DAT_3V3</td></tr><tr><td>27</td><td>PCH_PCIE_FM_WAKE-L</td><td>28</td><td>PCH_I2C1_CLK_3V3</td></tr><tr><td>29</td><td>GND</td><td>30</td><td>FM_PRESET-L</td></tr><tr><td>31</td><td>SOC_FM_PCIECLK2_P</td><td>32</td><td>PLTRST-L_FM</td></tr><tr><td>33</td><td>SOC_FM_PCIECLK2_N</td><td>34</td><td>GND</td></tr><tr><td>35</td><td>GND</td><td>36</td><td>PCH_SMB_ALERT_N_3V3</td></tr><tr><td>37</td><td>SOC_FM_PCIE_RX5_P</td><td>38</td><td>PCH_SMB_DAT_A</td></tr><tr><td>39</td><td>SOC_FM_PCIE_RX5_N</td><td>40</td><td>PCH_SMB_CLK_A</td></tr><tr><td>41</td><td>GND</td><td>42</td><td>GND</td></tr><tr><td>43</td><td>SOC_FM_PCIE_TX5_P</td><td>44</td><td>FM_U3_TX1_P</td></tr><tr><td>45</td><td>SOC_FM_PCIE_TX5_N</td><td>46</td><td>FM_U3_TX1_N</td></tr><tr><td>47</td><td>GND</td><td>48</td><td>GND</td></tr><tr><td>49</td><td>SOC_FM_PCIECLK3_P</td><td>50</td><td>FM_U3_RX1_P</td></tr><tr><td>51</td><td>SOC_FM_PCIECLK3_N</td><td>52</td><td>FM_U3_RX1_N</td></tr><tr><td>53</td><td>GND</td><td>54</td><td>GND</td></tr><tr><td>55</td><td>SOC_FM_PCIE_RX6_P</td><td>56</td><td>FM_U2_P1_P</td></tr><tr><td>57</td><td>SOC_FM_PCIE_RX6_N</td><td>58</td><td>FM_U2_P1_N</td></tr><tr><td>59</td><td>GND</td><td>60</td><td>GND</td></tr><tr><td>61</td><td>SOC_FM_PCIE_TX6_P</td><td>62</td><td>FM_U3_TX2_P</td></tr><tr><td>63</td><td>SOC_FM_PCIE_TX6_N</td><td>64</td><td>FM_U3_TX2_N</td></tr><tr><td>65</td><td>GND</td><td>66</td><td>GND</td></tr></table>

![Pure electrical circuit lines without any symbols](.sp2-twl-50m-p1700-1000-10-0529/5b5f12b9be6f48748dd382cd40031a5e2f311c31de83fd5f82df157364c4c02e.jpg)

<table><tr><td>67</td><td>SOC_FM_PCIECLK4_P</td><td>68</td><td>FM_U3_RX2_P</td></tr><tr><td>69</td><td>SOC_FM_PCIECLK4_N</td><td>70</td><td>FM_U3_RX2_N</td></tr><tr><td>71</td><td>GND</td><td>72</td><td>GND</td></tr><tr><td>73</td><td>SOC_FM_PCIE_RX7_P</td><td>74</td><td>FM_U2_P2_P</td></tr><tr><td>75</td><td>SOC_FM_PCIE_RX7_N</td><td>76</td><td>FM_U2_P2_N</td></tr><tr><td>77</td><td>GND</td><td>78</td><td>GND</td></tr><tr><td>79</td><td>SOC_FM_PCIE_TX7_P</td><td>80</td><td>FM_U2_P3_P</td></tr><tr><td>81</td><td>SOC_FM_PCIE_TX7_N</td><td>82</td><td>FM_U2_P3_N</td></tr><tr><td>83</td><td>GND</td><td>84</td><td>GND</td></tr><tr><td>85</td><td>SOC_FM_PCIECLK5_P</td><td>86</td><td>FM_U2_P4_P</td></tr><tr><td>87</td><td>SOC_FM_PCIECLK5_N</td><td>88</td><td>FM_U2_P4_N</td></tr><tr><td>89</td><td>GND</td><td>90</td><td>GND</td></tr><tr><td>91</td><td>SOC_FM_PCIE_RX8_P</td><td>92</td><td>FM_ESPI_LPC_0</td></tr><tr><td>93</td><td>SOC_FM_PCIE_RX8_N</td><td>94</td><td>FM_ESPI_LPC_1</td></tr><tr><td>95</td><td>GND</td><td>96</td><td>FM_ESPI_LPC_2</td></tr><tr><td>97</td><td>SOC_FM_PCIE_TX8_P</td><td>98</td><td>FM_ESPI_LPC_3</td></tr><tr><td>99</td><td>SOC_FM_PCIE_TX8_N</td><td>100</td><td>FM_ESPI_CS1_LPC_FRAME-L</td></tr><tr><td>101</td><td>GND</td><td>102</td><td>FM_ESPI_CLK_LPC_CLK</td></tr><tr><td>103</td><td>PCH_CLK_REQ_P4_N_3V3</td><td>104</td><td>FM_ESPI_ALERT1-L_LPC_SERIRQ</td></tr><tr><td>105</td><td>PCH_CLK_REQ_P5_N_3V3</td><td>106</td><td>FM_ESPI_RESET-L_LPC_DRQ</td></tr><tr><td>107</td><td>GND</td><td>108</td><td>GND</td></tr><tr><td>109</td><td>FM_TCP2_TX0_P</td><td>110</td><td>I2S1_TXD_TCP2_LSK_TXD</td></tr><tr><td>111</td><td>FM_TCP2_TX0_N</td><td>112</td><td>I2S1_RXD_TCP2_LSK_RXD</td></tr><tr><td>113</td><td>GND</td><td>114</td><td>I2S1_SFRM</td></tr><tr><td>115</td><td>FM_TCP2_TX1_P</td><td>116</td><td>I2S1_SCLK_PCH_SML0_DAT</td></tr><tr><td>117</td><td>FM_TCP2_TX1_N</td><td>118</td><td>I2S1_MCLK_PCH_SML0_CLK</td></tr><tr><td>119</td><td>GND</td><td>120</td><td>GND</td></tr><tr><td>121</td><td>FM_TCP2_TX2_P</td><td>122</td><td>USB_OC1_N</td></tr><tr><td>123</td><td>FM_TCP2_TX2_N</td><td>124</td><td>USB_OC3_N</td></tr><tr><td>125</td><td>GND</td><td>126</td><td>GND</td></tr><tr><td>127</td><td>FM_TCP2_TX3_P</td><td>128</td><td>FM_GPIO0</td></tr><tr><td>129</td><td>FM_TCP2_TX3_N</td><td>130</td><td>FM_GPIO1</td></tr><tr><td>131</td><td>GND</td><td>132</td><td>FM_GPIO2</td></tr><tr><td>133</td><td>FM_TCP2_I2CCLK_AUX_P_CN</td><td>134</td><td>GPIO3_SPICS1_MUX</td></tr><tr><td>135</td><td>FM_TCP2_I2CDAT_AUX_N_CN</td><td>136</td><td>GPIO4_FIN_IN_MUX</td></tr><tr><td>137</td><td>GND</td><td>138</td><td>GPIO3_FIN_OUT_MUX</td></tr><tr><td>139</td><td>FM_TCP2_DDC_AUX_SEL_CN</td><td>140</td><td>FM_SPI_MISO</td></tr><tr><td>141</td><td>FM_TCP2_DDI1_HPD</td><td>142</td><td>FM_SPI_MOSI</td></tr><tr><td>143</td><td>GND</td><td>144</td><td>FM_SPI_CS#</td></tr><tr><td>145</td><td>PCH_I2C2_DAT_3V3</td><td>146</td><td>FM_SPI_CLK</td></tr><tr><td>147</td><td>PCH_I2C2_CLK_3V3</td><td>148</td><td>GND</td></tr><tr><td>149</td><td>FM_I2C2_INT_3V3</td><td>150</td><td>UART_SOC_RI_N</td></tr></table>

# 6.22. Clear CMOS header

Under conditions where the device fails to boot, clearing the BIOS contents stored in CMOS and restoring the default settings may be effective. To clear the CMOS, short pins 2 and 3, then wait for 5 seconds. Remove the jumper cap and short pins 1 and 2.

<table><tr><td colspan="2">Clear COS Pin Header</td></tr><tr><td>CN1</td><td></td></tr><tr><td>(1-2)</td><td>NA (Default)</td></tr><tr><td>(2-3)</td><td>Clear CMOS</td></tr></table>

# 7. Getting Started

Follow the instructions in this chapter to add or change memory; Wi-Fi modules, mounting brackets, and mounting clips.

# 7.1. Adding or Changing Memory

Follow these steps to add or change memory modules.

1. Remove the 3 screws that attach the heatsink to the mainboard, and then remove the heatsink.
2. Install or swap the memory module in the SODIMM socket as necessary.

![Diagram of a computer motherboard with labeled ports and connectors, showing internal structure and mounting points.](.sp2-twl-50m-p1700-1000-10-0529/87c1fccaf9607bb74679eef53ee46d9ef159ed1bf64bd64e63d9afde6da4db7c.jpg)

![Diagram of an internal computer motherboard with labeled ports and connectors, highlighting specific areas marked with red circles.](.sp2-twl-50m-p1700-1000-10-0529/a5bb94b737576b35c5b083017fc475ff21e2c213252363f8f2795c44d491ba8f.jpg)

3. Reattach the heat sink to the mainboard with the previously removed screws.

# 7.2. Installing a Wi-Fi-Module

Follow these steps to add or change a Wi-Fi module.

1. Remove the 3 screws that attach the heatsink to the mainboard, and then remove the heatsink.

![Diagram of an electronic device rear panel with labeled ports and connectors, showing internal structure and wiring layout.](.sp2-twl-50m-p1700-1000-10-0529/e335e9a4e5af24459e0bc29cc5f87df258f434197a4249ec69d24badde7e23b4.jpg)

2. Install the Wi-Fi module.

![A1' A2'\nA1 A2\nAUX:A2'\nMain:A1'](.sp2-twl-50m-p1700-1000-10-0529/0aaf610fb42471ddc5d4974d9fd5cc91722650cb9dc72b8a696d90fa3b41a491.jpg)

3. Reattach the heat sink to the mainboard with the previously removed screws.
4. Install Antennas to rear cover or equipment

![A1\nA2\nRear Cover](.sp2-twl-50m-p1700-1000-10-0529/1697cd52e146e0a51307eac2a906a023239c251c9263de8da9f5561642b4b1f9.jpg)

![The image displays a red icon on a white background. The icon is shaped like a document or a piece of paper with a folded top-right corner. Inside the document shape, there are two horizontal lines representing text.](.sp2-twl-50m-p1700-1000-10-0529/463356afe2232f82cdf980c3cadb79e827f750ac2b88dd831c83c63ecd597135.jpg)

Note: Wi-Fi antennas must be installed on the SP2-TWL Series housing in order for Wi-Fi to function properly.

# 7.3. Installing an LTE Module

Follow these steps to add or change a Wi-Fi module.

1. Remove the 3 screws that attach the heatsink to the mainboard, and then remove the heatsink.

![Back view of an electronic device chassis showing internal components and connectors (no text or symbols visible)](.sp2-twl-50m-p1700-1000-10-0529/3f871573a9780d3cdd91e8aacdb67a334eb52c4c5d222b4d72e31e66afd60e92.jpg)

2. Install the LTE module.

![A1' A2'\nA1 A2\nA1 A2\nAUX: A2'\nMain: A1'\nAFCI](.sp2-twl-50m-p1700-1000-10-0529/e3e6bf98bc647e4f6fffd24f97bf69c11fb3c5c26332fad643a488a0d8e08293.jpg)

3. Reattach the heat sink to the mainboard with the previously removed screws.
4. Install Antennas to rear cover or equipment.

![Rear Cover](.sp2-twl-50m-p1700-1000-10-0529/2bedf53ea43cff31c37c1a52a3fbb23723d0857f18f43b93c03a79220871a731.jpg)

![The image displays a red icon resembling a piece of paper or a document with the top-right corner folded down. Inside the outline, there are two thick horizontal lines centered vertically, representing text or content.](.sp2-twl-50m-p1700-1000-10-0529/ed9de66965c70d63f1bcd56940796971275afc3d3b664e9dff78c8acbfa9559c.jpg)

Note: LTE antennas must be installed on the SP2-TWL Series housing in order for LTE to function properly.

# 7.4. Mounting

This section includes details for panel and VESA mounting options.

![The image displays a red outline icon of a document with a folded top-right corner. Inside the outline are two horizontal red lines.](.sp2-twl-50m-p1700-1000-10-0529/8b592fe228d706ba2e3163c7d5aa98c1943e3885dc29505941be4d3f852c9db2.jpg)

Note: All dimensions are in millimeters, unless noted.

![The image displays a standard red triangular warning sign containing a white exclamation point in its center.](.sp2-twl-50m-p1700-1000-10-0529/eb2c9c2e76d677bf2bfa4059938548606cf2e615d6706b38663df771639c34ba.jpg)

Warning: Risk of physical injuries and / or property damage:

When mounting the device, use the screws to mount the VESA bracket to the rear of the device. Tighten all four screws firmly to support the weight of the device. Make sure that the suspension system is capable of carrying the device.

![The image displays a yellow triangular warning sign containing a white exclamation point in the center. There is no other text present.](.sp2-twl-50m-p1700-1000-10-0529/46c2b1837ed90201d1edc11cf666a19b5852fc7ce38d1cfeca9afca5b456a013.jpg)

Caution: Risk of burns to the user caused by hot surfaces:

Turn off power and allow the device to cool down prior to performing any mounting or demounting operations. Do not touch the enclosure for over 10 seconds when the device is in operations or is still hot from previous use.

# 7.4.1 Panel Mounting

The SP2-TWL Series can be panel mounted with 14 mounting clips (optional items sold separately). Make sure there is adequate space behind the panel for ventilation, and that the panel material and thickness can support the weight of the device.

Step 1: Cut the panel opening using the appropriate cutout dimensions.

SP2-10WP cutout

![238.06 ±0.50\n±0.50\n159.40 CUT OUT](.sp2-twl-50m-p1700-1000-10-0529/33be1e234923606faedb362b1083f5e91f69554b33b8605eca931f27aa272dcb.jpg)

Figure 9 – SP2-10WP cutout dimensions

SP2-15WP cutout
![371.80 ±0.50\n221.60 ±0.50\nCUT OUT](.sp2-twl-50m-p1700-1000-10-0529/59cfd241c414e272cf9f08b27d6019a6d80b1bcd0134e9980de37c27aacce5b9.jpg)

Figure 10 – SP2-15WP cutout dimensions

SP2-21WP cutout
![505.60 ±0.50\n297.90 ±0.50\nCUT OUT](.sp2-twl-50m-p1700-1000-10-0529/50d75c12cedf8d2b308509ea226f85adcc0961d8f37d73c3e2a87f9ae133063a.jpg)

Figure 11 – SP2-21WP cutout dimensions

Step 2: Attach I/O cables to the device before installing into the panel if rear access will be limited after installation.
Step 3: Place the device into the panel cutout.

![Diagram showing two rectangular panels with a red arrow pointing to one panel, no text or symbols present](.sp2-twl-50m-p1700-1000-10-0529/5e0f7cce4baec8811cc6f8b8017a828c8091399a87b88eaabaa52e9a923bad90.jpg)

Step 4: Insert the mounting clips into the slots on the sides of the device as shown. Hand-tighten the mounting clips with a Phillips- head screwdriver to secure it to the panel. Do not overtighten the clips to avoid damaging the device enclosure.

![14.2⁺⁰·³₋₀·₁\n5.7\n16.7 ± 0.3\n12\n26.5⁺⁰·¹₋₀·⁵\n12\n1.2\nTAP M4\nCROSS_P_NI_M4\n3\n5\n1.3\nCLIP](.sp2-twl-50m-p1700-1000-10-0529/c31ceed5e05b38ade72a453a3e47d30206466bb93bc95ce0b12384838e6c8a8b.jpg)

Figure 12 – Mounting clip dimensions

![The image displays a red icon resembling a document or page with a rounded bottom-right corner. Inside the shape, three horizontal red lines are centered vertically.](.sp2-twl-50m-p1700-1000-10-0529/8e8775716dfcffc750831ad7e26f08509d090c3398760e37c352e5ad44ea59bd.jpg)

Note: Optional mounting clips sold separately. Contact your ADLINK reseller for details.

# 7.4.2 VESA Mounting

The SP2-TWL Series can be VESA mounted with a rear cover and VESA bracket. (Optional items sold separately.)

![The image displays a digital icon of a document. It features a thick red outline shaped like a piece of paper with the top-right corner folded down. Inside the red border, there are two horizontal red lines centered vertically.](.sp2-twl-50m-p1700-1000-10-0529/6db49fcd6973251854fb24631941d9b69d6189752965c42a644a1d08b4942a97.jpg)

Note: 1. All I/O ports must face down. 2. Optional VESA bracket and M3 screws sold separately. Contact your ADLINK reseller for details. 3. Mounting bracket provides 100 mm x 100 mm VESA mounting and requires 4x M4 screws.

Attach the rear cover to the panel PC with the screws supplied in the kit, then secure the VESA bracket to the rear cover with 4x M3 screws.

![VESA bracket\n100x 100\nRear cover](.sp2-twl-50m-p1700-1000-10-0529/4674fbfb212a54b39342c49fab8003601115dc8a61a9cfd295df38ce458bd8c9.jpg)

# 8. Driver and Application Installation

After installing the operating system, all related drivers must be installed for the system to function properly. This section describes the drivers needed for Windows operating systems and the procedures to install them. For other operating system support, contact ADLINK for further information.

Visit the ADLINK web site to download drivers:

https://www.adlinktech.com/Products/Panel\_PCs\_Monitors/Panel\_PCs\_Monitors/SP2-TWL\_Series

# 9. BIOS Setup

This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right-hand column of the respective table.

<table><tr><td>Main</td><td>Advanced</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>BIOS InformationSystem InformationBoard InformationSystem DateSystem Time</td><td>CPU Configuration ▶Power Management ▶Graphics Configuration ▶Super IO Configuration ▶BIOS Watchdog Timer ▶Serial Port Console Redirection ▶Trusted Computing ▶Hardware Monitor ▶NVME Configuration ▶Network Stack Configuration ▶Miscellaneous ▶</td><td>System Agent (SA) Configuration ▶PCH-IO Configuration ▶</td><td>PasswordDescriptionSecure BootMenu ▶</td><td>BootConfiguration</td><td>Save OptionsDefault OptionsBoot Override</td></tr></table>

# Notes:

► Indicates a submenu

Gray text indicates info only

# 9.1. Main

The Main Menu provides read-only information about your system and allows you to set the System Date and Time. Refer to the tables below for details about the submenus and settings.

9.1.1 Menu > BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vender</td><td>Info only</td><td>American Megatrends</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display Core version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Display compliancy information</td></tr><tr><td>MRC Version</td><td>Info only</td><td>Display compliancy information</td></tr><tr><td>GOP Driver Version</td><td>Info only</td><td>Display Intel Graphic Version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display Intel CSME Version</td></tr><tr><td>EC Version</td><td>Info only</td><td>Display EC version</td></tr></table>

9.1.2 Menu > System Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Project Name</td><td>Info only</td><td>Display Project Name.</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU Signature.</td></tr><tr><td>CPU Brand String</td><td>Info only</td><td>Display CPU Brand Name.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency.</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display PCH Information.</td></tr><tr><td>FM Board</td><td>Info only</td><td>Display FM SKUY</td></tr></table>

9.1.3 Menu > Board Information

<table><tr><td>Board Information</td><td>Info only</td><td>Description</td></tr><tr><td>Serial Number</td><td>Read only</td><td>Display SMC serial Number</td></tr><tr><td>Manufacturing Date</td><td>Read only</td><td>Display SMC manufacturing date.</td></tr><tr><td>Last Repair Date</td><td>Read only</td><td>Display SMC last repair date.</td></tr></table>

9.1.4 Menu > System Date and Time

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Date</td><td>Weekday, MM/DD/YYYY</td><td>Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)</td></tr><tr><td>System Time</td><td>HH/MM/SS</td><td>Presented as a 24-hour clock setting in hours, minutes, and seconds</td></tr><tr><td>Access Level</td><td>Info only</td><td></td></tr></table>

# 9.2. Advanced

This menu contains the settings for most of the user interfaces in the system.

9.2.1 Advanced > CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>ID</td><td>Info only</td><td></td></tr><tr><td>Brand String</td><td>Info only</td><td></td></tr><tr><td>Microcode Revision</td><td>Info only</td><td></td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td></td></tr><tr><td>L1 Instruction Cache</td><td>Info only</td><td></td></tr><tr><td>L2 Cache</td><td>Info only</td><td></td></tr><tr><td>L3 Cache</td><td>Info only</td><td></td></tr><tr><td>VMX</td><td>Info only</td><td></td></tr><tr><td>SMX/TXT</td><td>Info only</td><td></td></tr><tr><td>Turbo Mode</td><td>Disabled, Enabled</td><td>Enable/Disable processor Turbo Mode (requires EMTTM enabled too). AUTO means enabled.</td></tr><tr><td>C States</td><td>Disabled, Enabled</td><td>Enable/Disable CPU Power Management. Allows CPU to go to C states when it&#x27;s not 100% utilized.</td></tr><tr><td>Intel Trusted Execution Technology</td><td>Disabled, Enabled</td><td>Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect.</td></tr></table>

9.2.2 Advanced > Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable Hibernation</td><td>Disabled, Enabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disabled, S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr><tr><td>ERP</td><td>Disabled, Enabled</td><td>Energy-Related Products</td></tr><tr><td>State After G3</td><td>S0 State, S5 State</td><td>Specify what state to go to when power is re-applied after a power failure (G3 state).</td></tr></table>

9.2.3 Advanced > Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Nxp configuration</td><td>Info Only</td><td></td></tr><tr><td>Data format and Color Depth</td><td>AutoVESA 24 bppJEIDA 24 bppJEIDA/vesa 18 bpp</td><td>Data format and Color Depth select</td></tr><tr><td>LVDS Output Mode</td><td>AutoDual LVDS busSingle LVDS bus</td><td>Single/Dual mode select</td></tr><tr><td>DE Polarity</td><td>Active HighActive Low</td><td>DE Polarity select</td></tr><tr><td>Vsync Polarity</td><td>Active HighActive Low</td><td>Vsync Polaity select</td></tr><tr><td>Hsync Polarity</td><td>Active HighActive Low</td><td>Hsync Polaity select</td></tr><tr><td>Spreading depth</td><td>No Spreading0.5%1.0%1.5%2.0%2.5%</td><td>Clock frequency center spreading depth.</td></tr><tr><td>Integrated Display Configuration</td><td>Info only</td><td></td></tr><tr><td>eDP/LVDS</td><td>DisabledEnabled</td><td>Enable/Disable eDP/LVDS</td></tr><tr><td>LFP Panel Type</td><td>VBIOS Default640x480800x6001024x7681280x10241400x1050 LVDS11400x1050 LVDS21600x12001366x7681680x10501920x12001440x9001600x9001024x7681280x8001920x10802048x1536</td><td>Select LFP panel used by Internal Graphics Device by selecting the appropriate setup item.</td></tr><tr><td>DDI port 1</td><td>No Device,Display Port,HDMI,DisplayPort with HDMI/DVI Compatible</td><td>Select LVDS Backlight control function.</td></tr></table>

9.2.4 Advanced > Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Super IO Configuration</td><td colspan="2">Info only</td></tr><tr><td>NCT5525D Super IO Configuration</td><td>submenu</td><td></td></tr><tr><td>NCT5104S Super IO Configuration</td><td>submenu</td><td></td></tr></table>

9.2.4.1. Advanced > Super I/O Configuration > NCT5525D Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5525D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>submenu</td><td></td></tr></table>

9.2.4.1.1. Advanced > Super I/O Configuration > NCT5525D Super I/O Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>Device Mode</td><td>RS232RS485RS422</td><td>Change the Serial Port mode</td></tr></table>

9.2.4.1.2. Advanced > Super I/O Configuration > NCT5525D Super I/O Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>Device Mode</td><td>RS232RS485RS422</td><td>Change the Serial Port mode</td></tr></table>

9.2.4.2. Advanced > Super I/O Configuration > NCT5104D Super I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5104D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Super IO Chip</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1 Configuration</td><td>submenu</td><td></td></tr><tr><td>Serial Port 2 Configuration</td><td>submenu</td><td></td></tr></table>

9.2.4.2.1. Advanced > Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 1 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 1 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>COM1 Control</td><td>RS232RS485RS422</td><td>Select COM1 mode, RS232, RS422 or RS485</td></tr></table>

9.2.4.2.2. Advanced > Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 2 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 2 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr><tr><td>COM2 Control</td><td>RS232RS485RS422</td><td>Select COM2 mode, RS232, RS422 or RS485</td></tr></table>

9.2.4.2.3. Advanced > Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 3 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 3 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr></table>

9.2.4.2.4. Advanced > Super I/O Configuration > NCT5104D Super I/O Configuration > Serial Port 4 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Port 4 Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port</td><td>DisabledEnabled</td><td>Enable or Disable Serial Port (COM).</td></tr><tr><td>Device Settings</td><td>Info only</td><td></td></tr></table>

9.2.5 Advanced > BIOS Watchdog Timer

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Watchdog Timer</td><td>Info only</td><td></td></tr><tr><td>BIOS POST watchdog</td><td>Disabled,Second Mode,Minute Mode</td><td>1. Disable: Disable WatchDog Timer; 2. Second Mode: Enable Watchdog Timer in second mode; 3. Minute Mode: Enable Watchdog Timer in minute mode.</td></tr></table>

9.2.6 Advanced > Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection</td><td>Disabled, Enabled</td><td>To enable or disable console redirection of COMx.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td>The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.</td></tr></table>

9.2.6.1. Advanced > Serial Port Console > Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM0</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed. The speed must be matched on the other side. Long or noisy lines may require lower speeds.</td></tr><tr><td>Data Bits</td><td>78</td><td>Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and Space Parity do not allow for error detection.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.</td></tr></table>

9.2.7 Advanced > Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device Support</td><td>Disable, Enable</td><td>Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available.</td></tr></table>

9.2.8 Advanced > Hardware Monitor

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System temperature</td><td>Info Only</td><td></td></tr><tr><td>CPU temperature</td><td>Info Only</td><td></td></tr><tr><td>SYSTEM FAN Speed</td><td>Info Only</td><td></td></tr><tr><td>5V_S0</td><td>Info Only</td><td></td></tr><tr><td>VCCORE</td><td>Info Only</td><td></td></tr><tr><td>VCC3V</td><td>Info Only</td><td></td></tr><tr><td>VSB3V</td><td>Info Only</td><td></td></tr><tr><td>VBAT</td><td>Info Only</td><td></td></tr><tr><td>AVSB</td><td>Info Only</td><td></td></tr><tr><td>Smart Fan Function</td><td>Submenu</td><td>Smart Fan function setting</td></tr></table>

9.2.8.1. Advanced > Hardware Monitor > Smart Fan Function

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Fan Setting</td><td>Submenu</td><td></td></tr></table>

9.2.8.1.1. Advanced > Hardware Monitor > Smart Fan Function > MXM / System Fan settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Fan Mode</td><td>Manual mode, SMART FAN IV</td><td>Fan control mode select</td></tr><tr><td>Manual PWM</td><td>128</td><td>Fan will work with this Manual PWM Value(0~255 for 0%~100%)</td></tr></table>

9.2.9 Advanced > NVMe Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Seg:Bus:Dev:Func</td><td colspan="2">Info only</td></tr><tr><td>Model Number</td><td colspan="2">Info only</td></tr><tr><td>Total Size</td><td colspan="2">Info only</td></tr><tr><td>Vendor ID</td><td colspan="2">Info only</td></tr><tr><td>Device ID</td><td colspan="2">Info only</td></tr><tr><td>Namespace</td><td colspan="2">Info only</td></tr><tr><td>Self Test Option</td><td>ShortExtended</td><td>Select either Short or Extended Self Test. Short option will take couple of minutes and extended option will take several minutes to complete.</td></tr><tr><td>Self Test ActionRun Device Self Test</td><td>Controller Only TestController and NameSpace Test</td><td>Select either to test Controller alone or Controller and NameSpace. Selecting Controller and Namespace option will take lot longer to complete the test.Perform device self test for the corresponding Option and Action selected by user.Pressing 'Esc' key will abort the test. Result shown below is the recent result logged in the device.</td></tr></table>

9.2.10 Advanced > Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>DisabledEnabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>Ipv4 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.</td></tr><tr><td>Ipv6 PXE Support</td><td>DisabledEnabled</td><td>Enable/Disable IPv6 PXE boot support. If disabled, IPv6 PXE boot support will not be available.</td></tr><tr><td>PXE boot wait time</td><td>0</td><td>Wait time in seconds to press ESC key to abort the PXE boot.Use either +/- or numeric keys to set the value.</td></tr></table>

9.2.11 Advanced > Miscellaneous

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Miscellaneous</td><td>Info only</td><td></td></tr><tr><td>M.2 Configuration Mode</td><td>NVMe X2 + LTE NVMe X1 + SATA + USB to wafer or CAN SATA + SATA + USB to wafer or CAN</td><td>This setting configures M.2 M-Key + B-Key operation mode. If configured to M.2 M-Key NVMe + M.2 B-Key SATA mode, NVMe bandwidth will be limited to X1. USB will switch between CAN and LTE(M.2 B-Key) accordingly.</td></tr><tr><td>BIOS Lock</td><td>Disabled Enabled</td><td>Enable/Disable the PCH BIOS Lock Enable feature. Required to be enabled to ensure SMM protection of flash.</td></tr></table>

# 9.3. Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>System Agent (SA)Configuration</td><td>submenu</td><td></td></tr><tr><td>PCH-IO Configuration</td><td>submenu</td><td></td></tr></table>

# 9.3.1 Chipset > System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memoru Configuration</td><td>submenu</td><td>Memory Configuration</td></tr><tr><td>MIPI Camera Configuration</td><td>submenu</td><td>MIPI Camera Configuration</td></tr><tr><td>IPU Device (B0:D5:F0)</td><td>Enabled, Disabled</td><td>Enable/Disable SA IPU Device</td></tr><tr><td>VT-d</td><td>Enabled, Disabled</td><td>VT-d capability</td></tr><tr><td>Above 4GB MMIO BIOS assignment</td><td>Enabled, Disabled</td><td>Enable/Disable above 4GB MemoryMappedIO BIOS assignment\n\nThis is enabled automatically when Aperture Size is set to 2048MB.</td></tr></table>

# 9.3.1.1. Chipset > System Agent (SA) Configuration > Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td></td></tr><tr><td>Memory Frequency</td><td>Info only</td><td></td></tr><tr><td>tCL-tRCD-tRP-tRAS</td><td>Info only</td><td></td></tr><tr><td>MC 0 Ch 0 DIMM 0</td><td>Info only</td><td></td></tr><tr><td>Size</td><td>Info only</td><td></td></tr><tr><td>Number of Ranks</td><td>Info only</td><td></td></tr><tr><td>Manufacturer</td><td>Info only</td><td></td></tr></table>

9.3.1.2. Chipset > System Agent (SA) Configuration > MIPI Camera Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CVF Support</td><td>Disabled, Enabled</td><td>Disables/Enables CVF using either Native IOs or USB IOs Expansion.</td></tr><tr><td>CLK_EN Initial Status</td><td>High Low</td><td>Set CLK_EN GPIO(GPP_S4) initial status</td></tr><tr><td>Control Logic 1</td><td>Disabled, Enabled</td><td>Control Logic 1</td></tr><tr><td>Control Logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Control Logic 2</td><td>Disabled, Enabled</td><td>Control logic 2</td></tr><tr><td>Control Logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Control Logic 3</td><td>Disabled, Enabled</td><td>Control Logic 1</td></tr><tr><td>Control Logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Control Logic 4</td><td>Disabled, Enabled</td><td>Control logic 2</td></tr><tr><td>Control Logic options</td><td>submenu</td><td>Control logic options</td></tr><tr><td>Camera1</td><td>Disabled, Enabled</td><td>Camera1</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr><tr><td>Camera2</td><td>Disabled, Enabled</td><td>Camera2</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr><tr><td>Camera3</td><td>Disabled, Enabled</td><td>Camera1</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr><tr><td>Camera4</td><td>Disabled, Enabled</td><td>Camera2</td></tr><tr><td>Link options</td><td>submenu</td><td>Link options</td></tr></table>

9.3.1.2.1. Chipset > System Agent (SA) Configuration > MIPI Camera Configuration > Control Logic Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Control Logic Type</td><td>DiscretePMIC_TPS68470PMIC_UP6641PMIC_HDMI2MIPI_LT6911UXCPMIC_USER0PMIC_USER1</td><td>Control Logic Type</td></tr><tr><td>CRD Version</td><td>PTCCRD-GKilshon-PPVCRD-DCRD-G2LT6911UXC-V1</td><td>CRD Version</td></tr><tr><td>Input Clock</td><td>24 MHz26 MHz20 MHz19.2 MHz</td><td>Input Clock</td></tr><tr><td>PCH Clock Source</td><td>IMGCLKOUT_0IMGCLKOUT_1IMGCLKOUT_2IMGCLKOUT_3IMGCLKOUT_4</td><td>This optionspecifies which IMGCLKOUT is chosen</td></tr><tr><td>Number of GPIO Pins</td><td>1</td><td>Number of GPIO pins</td></tr><tr><td>GPIO n</td><td>Info only</td><td></td></tr><tr><td>GPIO Pad Number</td><td>15</td><td>GPIO Pad Number</td></tr><tr><td>Group Number</td><td>Group B, Group A, Group C, Group D, Group E, Group F, Group H, Group R, Group S, Group T, Group U</td><td>Group Number</td></tr><tr><td>Function</td><td>Reset, Power_En, Clock_En, PLED_En, Strobe_En,</td><td>Function</td></tr><tr><td></td><td>Handshake_En, Ready_Status, HDMI_Detect</td><td></td></tr><tr><td>Active Value</td><td>0, 1</td><td>Active Value</td></tr><tr><td>Initial Value</td><td>0, 1</td><td>Initial Value</td></tr></table>

9.3.1.2.2. Chipset > System Agent (SA) Configuration > MIPI Camera Configuration > Link Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Sensor Model</td><td>IMX135, OV5693, IMX179, OV8858, OV2740, OV9728, IMX188, IMX208, OV5670, OV8865, HM2051, OV2742, OV9234, OV8856,OV16860, IMX362, OVTID858, IMX488, OVTI01AS, OV01A10, OV5678, OV9738, HIMAX11B1, LONTIUM,User Defined Select MIPI Camera Sensor Model.</td><td>Select MIPI Camera</td></tr><tr><td>Custom HID</td><td>APPROISP</td><td>User defined _HID for Link0. Default is "APPROISP" for ADLINK.</td></tr><tr><td>Lanes Clock division</td><td>4 4 2 2, 4 4 3 1, 4 4 4 0, 8 0 2 2, 8 0 3 1, 8 0 4 0</td><td>Select MIPI Camera lanes and clock division.</td></tr><tr><td>CRD Version</td><td>PTC (0x10), CRD-G, Kilshon PPV ,CRD-D, CRD-G2</td><td>CRD Version</td></tr><tr><td>GPIO control</td><td>No Control Logic,Control Logic 1, Control Logic 2, Control Logic 3, Control Logic 4</td><td>GPIO control</td></tr><tr><td>Physical location</td><td>Front,Back</td><td>Camera position</td></tr><tr><td>Flash support</td><td>Driver Default,Disabled, Enabled</td><td>Flash Support</td></tr><tr><td>Privacy LED</td><td>Driver Default, ILEDA 16mA, ILEDB 2mA, 4mA, 8mA, 16mA</td><td>Privacy LED</td></tr><tr><td>Rotation</td><td>0, 90, 180, 270</td><td>Rotation</td></tr><tr><td>PPR Value</td><td>10</td><td>PPR value of sensor</td></tr><tr><td>PPR Unit</td><td>A</td><td>PPR unit of sensor</td></tr><tr><td>Module Name</td><td>appro_isp</td><td>Camera Module Name</td></tr><tr><td>MIPI port</td><td>1</td><td>LinkUsed</td></tr><tr><td>LaneUsed</td><td>x1, x2, x3,x4, x8</td><td>LaneUsed</td></tr><tr><td>PortSpeed</td><td>0,1,2, 3, 4, 5, 6</td><td>PortSpeed: 0:Sensor Default, 1:&lt;416Mbps, 2:&lt;1.5Gbps, 3:&lt;2Gbps, 4:&lt;2.5Gbps, 5:&lt;4Gbps, 6:&gt;4Gbps</td></tr><tr><td>MCLK</td><td>19200000</td><td>MCLK</td></tr><tr><td>EEPROM Type</td><td>ROM_OTPROM_EEPROM_16K_64ROM_EEPROM_16K_16ROM_OTP ACPI ACPIROM ACPIROM_EEPROM_BRCA016GWZROM_EEPROM_24AA32ROM_EEPROM_24C64ROM_EEPROM_DW9806BROM_EEPROM_CAT24C16ROM_EEPROM_CAT24C64ROM_EEPROM_24AA16ROM_NONEROM_EEPROM_CAT24C08</td><td>EEPROM Type0x00: ROM_NONE0x01: ROM_OTP0x02: ROM_EEPROM_16K_640x03: ROM_EEPROM_16K_160x04: ROM_OTP ACPI ACPI0x05: ROM ACPI0x06: ROM_EEPROM_BRCA016GWZ0x07: ROM_EEPROM_24AA320x08: ROM_EEPROM_CAT24C080x09: ROM_M24C640x0A: ROM_DW9806B0x10: ROM_EEPROM_CAT24C160x11: ROM_EEPROM_CAT24C640x12: ROM_EEPROM_24AA16</td></tr><tr><td>VCM Type</td><td>VCM_NONEVCM_AD5823VCM_AD5816VCM_DW9719VCM_DW9718VCM_DW9806BVCM_WV517SVCM_LC898122XAVCM_LC898212AXBVCM_RESERVED1VCM_RESERVED2VCM_BU64297GWZVCM_DW9714VCM_AK7371</td><td>VCM Type0x00: VCM_NONE0x01: VCM_AD58230x02: VCM_DW97140x03: VCM_AD58160x04: VCM_DW97190x05: VCM_DW97180x06: VCM_DW9806B0x07: VCM_WV517S0x08: VCM_LC898122XA0x09: VCM_LC898212AXB0x0F: VCM_AK73710x10: VCM_BU64297GWZ</td></tr><tr><td>Number of I2C Components</td><td>1</td><td>Number of I2C Components</td></tr><tr><td>I2C Channel</td><td>I2C0, I2C1, I2C2, I2C4, I2C3, I2C5, I2C6, I2C7</td><td>I2C Channel</td></tr><tr><td>Device 0</td><td>Info Only</td><td></td></tr><tr><td>I2C Address</td><td>1F</td><td></td></tr><tr><td>Device Type</td><td>Sensor,VCM, EEPROM,EEPROM_EXT1,EEPROM_EXT2,EEPROM_EXT3,EEPROM_EXT4,EEPROM_EXT5,EEPROM_EXT6,EEPROM_EXT7IO ExpanderFlash</td><td>Device Type</td></tr><tr><td>Flash Driver Selection</td><td>Disabled, External, Internal PMIC</td><td>Select the Flash Driver as External of Internal PMIC</td></tr></table>

# 9.3.2 Chipset > PCH-I/O Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA Configuration</td><td>Submenu</td><td></td></tr><tr><td>USB Configuration</td><td>Submenu</td><td></td></tr><tr><td>HD Audio Configuration</td><td>Submenu</td><td></td></tr></table>

# 9.3.2.1. Chipset > PCH-I/O Configuration > PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port P3</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port P4</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port P7</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCI Express Root Port P9</td><td>Submenu</td><td>Control the PCI Express Root Port.</td></tr></table>

# 9.3.2.1.1. Chipset > PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port 3

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>Disabled, Enabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr></table>

9.3.2.1.2. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port 4

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>Disabled, Enabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr></table>

9.3.2.1.3. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port 7

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>Disabled, Enabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr></table>

9.3.2.1.4. PCH-I/O Configuration > PCI Express Configuration > PCI Express Root Port 9

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port 3</td><td>Disabled, Enabled</td><td>Control the PCI Express Root Port.</td></tr><tr><td>PCIe Speed</td><td>Auto, Gen1, Gen2, Gen3, Gen4</td><td>Configure PCIe Speed</td></tr><tr><td>Detect Non-Compliance Device</td><td>Disabled, Enabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr></table>

9.3.2.2. Chipset > PCHI-I/O Configuration > SATA Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>Disabled, Enabled</td><td>Enable/Disable SATA Device</td></tr><tr><td>Serial ATA Port 0</td><td>Info Only</td><td></td></tr><tr><td>Software Preserve</td><td>Info Only</td><td></td></tr><tr><td>Port 0</td><td>Disabled, Enabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Serial ATA Port 1</td><td>Info Only</td><td></td></tr><tr><td>Software Preserve</td><td>Info Only</td><td></td></tr><tr><td>Port 1</td><td>Disabled, Enabled</td><td>Enable or Disable SATA Port</td></tr></table>

9.3.2.3. Chipset > PCHI-I/O Configuration > USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>USB Port Disable Override</td><td>Disabled,Select Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr><tr><td>USB SS Physical Connector #0</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #0</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #3</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #4</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #5</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #6</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr><tr><td>USB HS Physical Connector #7</td><td>Disabled,Enabled</td><td>Enable/Disable this USB Physical Connector (physical port). Once disabled, any USB devices plug into the connector will not be detected by BIOS or OS.</td></tr></table>

9.3.2.4. Chipset > PCHI-I/O Configuration > HD Audio Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HD Audio</td><td>Disabled,Enabled</td><td>Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled.Enabled = HDA will be unconditionally enabled.</td></tr></table>

9.4. Security

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Administrator Password</td><td>Enter password</td><td>Set Administrator Password</td></tr><tr><td>User Password</td><td>Enter password</td><td>Set User Password</td></tr><tr><td>Secure Boot</td><td>submenu</td><td></td></tr></table>

9.4.1 Security > Secure Boot Menu

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Secure Mode</td><td>Info only</td><td></td></tr><tr><td>Secure Boot</td><td>Disabled Enabled</td><td>Secure Boot feature is Active if Secure Boot is Enabled, platform Key (PK) is enrolled and the System is in User mode, The mode change requires platform reset</td></tr><tr><td>Secure Boot Mode</td><td>Standard Custom</td><td>Secure Boot mode options: Standard or Custom. In Custom mode, Secure Boot Policy variables can be configured by a physically present user without full</td></tr><tr><td>Restore Factory Keys</td><td>Info only</td><td>Force System to User Mode. Install factory default Secure Boot key databases</td></tr><tr><td>Reset To Setup Mode</td><td>Info only</td><td></td></tr><tr><td>Expert Key Management</td><td></td><td>Enables expert users to modify Secure Boot Policy variables without full authentication</td></tr></table>

# 9.5. Boot

9.5.1 Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>1</td><td>Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>OnOff</td><td>Select the keyboard NumLock state</td></tr><tr><td>Quiet Boot</td><td>DisabledEnabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>DisabledEnabled</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll Sata Devices</td><td>If Last Boot SATA Devices Only, Only last boot SATA device will be available in Post. If All Sata Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>NVME Support</td><td>DisabledEnabled</td><td>If Disabled, NVMe device will be skipped.</td></tr><tr><td>VGA Support</td><td>AutoEFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. Efi driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>DisabledFull InitialPartial Initial</td><td>If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Devices Support</td><td>DisabledEnabled</td><td>If Disabled, PS2 devices will be skipped.</td></tr><tr><td>NetWork Stack Driver Support</td><td>DisabledEnabled</td><td>If Disabled, NetWork Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>DisabledEnabled</td><td>If disable, Redirection function will be disabled.</td></tr></table>

# 9.6. Save & Exit

9.6.1 Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Exit</td><td></td><td>Exit system setup after saving the changes.</td></tr><tr><td>Discard Changes and Exit</td><td></td><td>Exit system setup without saving any changes.</td></tr><tr><td>Save Changes and Reset</td><td></td><td>Reset the system after saving the changes.</td></tr><tr><td>Discard Changes and Reset</td><td></td><td>Reset system setup without saving any changes.</td></tr><tr><td>Save Options</td><td>Info only</td><td></td></tr><tr><td>Save Changes</td><td></td><td>Save changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr></table>
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