# VPX3-MXM/A4500

# User’s Manual

3U VPX Rugged GPGPU Blade with NVIDIA® RTX™ A4500

![Green printed circuit board with various integrated circuits and connectors (no readable text or symbols)](.vpx3-mxm-a4500-50m-37622-1000-10/1f2bb92e22d0b83bda06e11064a3914b6b092b6ba99628646e7ac72869ed131f.jpg)

Manual Rev.: 1.0

Revision Date: January 6, 2026

Part Number: 50M-37622-1000

# Revision History

<table><tr><td>Revision</td><td>Description</td><td>Date</td><td>By</td></tr><tr><td>1.0</td><td>Initial release</td><td>2026-01-06</td><td>AL</td></tr></table>

# Preface

# Copyright

Copyright 2026 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with no text or labels, representing waste sorting or disposal (no text present)](.vpx3-mxm-a4500-50m-37622-1000-10/e19694dc1f2de5ffb67c5d298d9b097fc0a3e2208ab002b2c788c63d70745c6b.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or labels)](.vpx3-mxm-a4500-50m-37622-1000-10/2348b0727133f4e2afc5f82b929ed6f0760133da29ab2d9546d775d27a8772d5.jpg)

![Li-ion](.vpx3-mxm-a4500-50m-37622-1000-10/fc279e0064101cbf82631f5b5b90ac76063cd1871ec677d4ffe17527eef8dbbf.jpg)

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.vpx3-mxm-a4500-50m-37622-1000-10/9377049725149c2bbed0ef60d6d5d3b3a6f506f45a692f8803103c4b91f6d6b1.jpg)

![廢電池請回收](.vpx3-mxm-a4500-50m-37622-1000-10/dcc71f33183fee31aef2324a308eff7d3a113ff00e1dd56e9ba47e7b0d81d675.jpg)

# California Proposition 65 Warning

![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border. In the center is a black exclamation point. The background surrounding the triangle is white.](.vpx3-mxm-a4500-50m-37622-1000-10/51a59de2723db2a3eb4734930813dd803ccc575ba3e174aa625e573a5614c7f1.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP,

DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![A white document icon featuring a folded top-right corner and faint horizontal gray lines. A large red checkmark is superimposed diagonally across the center of the page.](.vpx3-mxm-a4500-50m-37622-1000-10/c4df150eb313f1f307b422acbab15c5acf910395258af27a02bac77bb14e8954.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign with a thick black border. Inside the triangle is a large black exclamation mark centered vertically and horizontally.](.vpx3-mxm-a4500-50m-37622-1000-10/ad45b3265b8952f0120b7fdbbff6d35dc8a6973ca23010486bca3cf937a130c3.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a standard warning symbol. It consists of a red equilateral triangle with a thin white border. Centered inside the triangle is a large white exclamation point, featuring a vertical bar and a separate circular dot at the bottom.](.vpx3-mxm-a4500-50m-37622-1000-10/65b7a6f66ac69f2c3d4588890d9ec79b5b8306fe50e1b30f386e7bebc702bd62.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

Preface...

List of Figures .... ..vi

List of Tables...... ..vi

1 Introduction....

1.1 Overview..

1.2 Features.. .7

1.3 Package Contents. .7

2 Specifications ...

2.1 Product Specifications.... .9

2.2 GPGPU Specifications.. ..10

2.3 Power Consumption . ..10

3 Block Diagram .. .11

4 Mechanical Layout .. .13

4.1 Mechanical Dimensions . ..13

4.2 Connectors, Switch Locations, and LEDs. ..13

5 Driver Installation .. .17

6 Connector Pinouts and Jumper Settings .... ..19

6.1 VPX Connectors .... .19

RTM Board Interfaces ............ .21

7.1 VPX-RMXM-DP Block Diagram . ..21

7.2 RTM Board Layout.. .22

7.3 RTM Connector Pin Assignments.. .23

Safety Instructions......... .25

Getting Services.......... .26

# List of Figures

Figure 1: VPX3-MXM/A4500 functional block diagram ..... ..11

Figure 2: Mechanical dimensions . ..13

Figure 3: Board layout .. .14

Figure 4: LED locations . ..15

Figure 5: VPX3-RMXM-DP functional block diagram . .21

Figure 6: RTM board layout... .22

# List of Tables

Table 1: Board layout labels . ..14

Table 2: System LED status . ..15

Table 3: RTM board labels .. ..22

# 1 Introduction

# Overview

The VPX3-MXM/A4500 is a 3U VPX general-purpose GPU (GPGPU) blade based on the NVIDIA A4500, supporting 16GB GDDR6 graphics memory with 4x DisplayPort or 4x HDMI output. The VPX3-MXM/A4500 brings a new level of performance to visual graphics and a wide range of computing applications, fully integrating hardware acceleration for both graphics and computing workloads.

The VPX3-MXM/A4500 features rugged, conduction-cooled construction with conformal-coating, making it ideal for mission-critical applications requiring artificial intelligence and machine learning (AI/ML) and parallel computing, as well as SWaP optimization, including radar processing, target tracking, software-defined radio (SDR), intelligence, surveillance and reconnaissance (ISR), degraded visual environments (DVE), digital signal Processing (DSP), electronic warfare (EW), and signals intelligence (SIGINT).

The VPX3-MXM/A4500 is also SOSA-aligned, with SOSA being one of several standards that fall broadly within the Modular Open Systems Approach (MOSA) initiative. SOSA centers on key interfaces and open standards, based on the VPX standard (VITA 46/48/65), and aims to develop a common, modular hardware architecture for next-generation, mission-critical applications.

# Features

• NVIDIA® A4500 embedded graphics based on Ampere architecture
5888 CUDA cores, 17.66 TFLOPS peak FP32 performance
16GB GDDR6 memory, 256-bit, Bandwidth: 512 GB/s
• Four DisplayPort 1.4
• VITA 46/48/65 compliant for quick deployment
• SOSA-aligned

# Package Contents

The VPX3-MXM/A4500 is packaged with the following components. If any items from the contents list are missing or damaged, retain the shipping carton and packing materials, and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the VPX3-MXM/A4500 are non-standard configurations and may vary depending on customer requests.

# GPGU Blade

VPX3-MXM/A4500
o Thermal module is assembled on the board

# Rear Transition Module (optional)

VPX3-RMXM-DP

![The image depicts a white document icon with a folded upper-left corner and horizontal lines. A large, bold red checkmark is superimposed over the paper. The graphic is enclosed within a thin black square border.](.vpx3-mxm-a4500-50m-37622-1000-10/06c4f0018c98dfc1dd95c606c0eb16c1bdcefcfc95b225538756c2c58fe74f08.jpg)
NOTE:

The contents of non-standard VPX3-MXM configurations may vary depending on the customer’s requirements.

![The image shows a yellow triangular warning sign with a black border. Inside the triangle is a large black exclamation mark centered vertically. At the very top edge, there is a thin black horizontal line.](.vpx3-mxm-a4500-50m-37622-1000-10/4f6886a273315aa888308d330203a15e3f29e3e334b54a44c8533660193edd6b.jpg)
CAUTION:

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the antistatic bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

# 2 Specifications

# Product Specifications

<table><tr><td>VITA Standards</td><td>VITA 46.0 VPX Base StandardVITA 46.4 PCI Express on VPX Fabric ConnectorVITA 48.0 Mechanical Specification for Microcomputers using REDI Conduction Cooling Applied to VITA 46VITA 65 OpenVPX Architecture Framework for VPXSOSA aligned w/o PCIe interface from P2</td></tr><tr><td>MXM Module</td><td>EGX-MXM-A4500 (TGP 115W, Standard MXM 3.1 Type B)</td></tr><tr><td>Power Entry</td><td>12V(VS1/VS2) and 3.3V_AUX only (SOSA-aligned)</td></tr><tr><td>Display</td><td>4x DisplayPort 1.4 4K@120HzSupports DP++ (CONFIG1 on P2)</td></tr><tr><td>Mechanical</td><td>3U VPX 0.85&quot; with conduction cooling; secondary side retainerDimensions: 100mm x 160mmSupports MXM 4.1 Type-B+ (110mm)Conformal coating</td></tr><tr><td>Profiles</td><td>Supports SOSA slot profile (PCIe x8) - SLT3-PAY-2F2U-14.2.3 Legacy Payload Slot Profile</td></tr><tr><td>PCIeConfiguration</td><td>PCIe interface over P1PCIe bifurcation 1 x16, 1 x8 (default), 1 x4, 2 x8, 2 x4,1 x8 + 2 x4Support two ports NTB</td></tr><tr><td>ClockConfiguration</td><td>PCIe Clock Mode selection by System Management requestSynchronize mode (default)Unsynchronized mode</td></tr><tr><td>IPMC</td><td>Smart fusion Intelligent A2F200M3F-CSG288 compliant with VITA 46.11</td></tr><tr><td>Reset Button</td><td>Yes (front panel)</td></tr><tr><td>RTM Support</td><td>4x DP display ports from RTM</td></tr><tr><td>Environmental</td><td>Operating Temp: -40°C to 85°C at wedge lock (VITA47.0, ECC4-CC4)Storage Temp: -55°C to 105°CRelative Humidity: 95% non-condensingShock: 40G, 11ms (VITA47.0, ECC4-OS2)Vibration (Random): 12Grms, 5Hz to 2000Hz (VITA47.0, ECC4-V3)Vibration (Sinusoidal): 5G, 20Hz to 2000HzAltitude: 60,000 feet, operating</td></tr><tr><td>EMI</td><td>CE EN55032/55035FCC 47 CFR Part 15 Subpart B, Class A</td></tr></table>

# GPGPU Specifications

<table><tr><td>GPU</td><td>NVIDIA RTX A4500 GA104-955 GPU</td></tr><tr><td>Module TGP</td><td>115W</td></tr><tr><td>Architecture</td><td>Ampere</td></tr><tr><td>Memory</td><td>16GB GDDR6 memory, 256-bit, Bandwidth: 512 GB/s</td></tr><tr><td>CUDA Cores</td><td>5888 CUDA cores</td></tr><tr><td>TFLOPs</td><td>17.66 TFLOPS peak FP32 performance</td></tr><tr><td>Tensor Cores</td><td>184 Tensor Cores</td></tr><tr><td>RT Cores</td><td>46 RT Cores</td></tr><tr><td>Compute API</td><td>CUDA Compute 8.0 and above, OpenCLTM 1.2</td></tr><tr><td>Graphic API</td><td>DirectX® 12, OpenGL 4.6</td></tr></table>

# GDDR6 Memory

GDDR6 (Graphics Double Data Rate 6) synchronous graphics RAM (SGRAM) conforms to the standards set by the JEDEC GDDR6 specification. It is specifically designed for use in graphics devices that demand high memory bandwidth, such as 3D gaming systems and HD video editing platforms. This dedicated memory serves the Graphics Processing Unit (GPU), reducing the display and graphics load on the system’s main memory and significantly improving GPU and overall display performance. As a result, it enables a much richer visual experience than would be possible with integrated graphics alone.

# Display Interfaces

The VPX3-MXM/A4500 provides four digital output channels, all of which can be active simultaneously. The VPX3-MXM/A4500 utilizes the P2 rear I/O connector for DisplayPort outputs via the RTM.

![The image displays a white document icon with a folded top-right corner and faint horizontal lines resembling text. A large, bold red checkmark is superimposed diagonally across the document.](.vpx3-mxm-a4500-50m-37622-1000-10/2db8ea3bbd54bbb54372a78b314b00701908b07820e3293f562c93255277387a.jpg)
NOTE:

Specifications are subject to change without prior notice.

# Power Consumption

<table><tr><td colspan="2">VPX3-MXM/A4500 + DP (SOSA)</td></tr><tr><td colspan="2">Windows Idle mode</td></tr><tr><td>3.3V(A)</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td></tr><tr><td>12V(A)</td><td>2</td></tr><tr><td>3.3 AUX(A)</td><td>2.31</td></tr><tr><td>Power consumption(W)</td><td>28.29</td></tr><tr><td colspan="2">Windows Max mode</td></tr><tr><td>3.3V(A)</td><td>0</td></tr><tr><td>5V(A)</td><td>0</td></tr><tr><td>12V(A)</td><td>11.62</td></tr><tr><td>3.3 AUX(A)</td><td>0.16</td></tr><tr><td>Power consumption(W)</td><td>140.02</td></tr></table>

# 3 Block Diagram

![The diagram depicts a system architecture centered around a large green block labeled **NVIDIA**.\n\n**NVIDIA Block:**\nInside this block are:\n*   Top left: **GDDR6 16GB**\n*   Top right: A stack of four blue boxes labeled **VBIOS**, **5888 CUDA**, **17.66 TFLOPs**, and **Temperature Sensor**.\n\n**Connections from NVIDIA:**\n*   **Left Side:** Four arrows point downward to a white box labeled **Configuration**. From this box, four arrows continue down to the bottom of the diagram. Labels **DP-A**, **DP-B**, **DP-C**, and **DP-D** sit between the Configuration box and the bottom bar. These arrows connect to a section of the bottom bar labeled **P2**.\n*   **Center:** An arrow points upward from a blue box labeled **PCIe Switch** to the NVIDIA block. Text next to this arrow reads **x16 PCIe Gen3 1x16**. Another arrow points downward from the PCIe Switch to the bottom bar with text reading **1x8 (default) PCIe Gen3 1x8 (default)**. This connects to a section labeled **P1**.\n*   **Right Side:** An arrow points rightward to a blue box labeled **IPMC**. Text above this arrow reads **Vol**.\n    *   Above the IPMC is a small grey box labeled **SPI Flash**.\n    *   An arrow points rightward from the IPMC labeled **Sys_Temp.**\n    *   Two arrows point downward from the IPMC to the bottom bar. One is labeled **IPMB_1** and the other **IPMB_0**. Both connect to a section labeled **P0**.\n\n**Bottom Bar:**\nA long orange bar runs across the bottom, divided into three sections labeled **P2**, **P1**, and **P0**.](.vpx3-mxm-a4500-50m-37622-1000-10/03a77688b58750394169812aad1b9d30228af5a7286bec1a72cf8f9a907caecc.jpg)

Figure 1: VPX3-MXM/A4500 functional block diagram

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# 4 Mechanical Layout

# Mechanical Dimensions

![20.10](.vpx3-mxm-a4500-50m-37622-1000-10/0c4b736031f15af5126f1fef1d972599fa9c7a2b330c83d36bce599f3ac6c637.jpg)

![160\n99.85](.vpx3-mxm-a4500-50m-37622-1000-10/21ecef1a47e59f4b1d38ef387d2e4a6add29e791be413c29fe6f777150f12c4a.jpg)

![14.50\n5.60](.vpx3-mxm-a4500-50m-37622-1000-10/1787e3d4b346b20370d8e86f16434f1a0c208029490e1eca78d62082c297df20.jpg)

Figure 2: Mechanical dimensions

# Connectors, Switch Locations, and LEDs

This chapter illustrates the board layouts, connector pin assignments, and jumper settings.

# VPX3-MXM/A4500 Board Layout

![A\nB\nC\nD\nE](.vpx3-mxm-a4500-50m-37622-1000-10/af30ed0afcbc682b229c8a616c0c048eae8d0ce7139dd9dd4395807b7063d6fe.jpg)

Figure 3: Board layout

Table 1: Board layout labels

<table><tr><td>A</td><td>VPX Connector_P0</td><td>D</td><td>MXM Connector</td></tr><tr><td>B</td><td>VPX_Connector_P1</td><td>E</td><td>PCIe Switch PEX8734</td></tr><tr><td>C</td><td>VPX Connector_P2</td><td colspan="2"></td></tr></table>

# System LEDs

![LED5 LED7 LED15 LED12\nLED6 LED8 LED14 LED3 LED4](.vpx3-mxm-a4500-50m-37622-1000-10/99b3ce84f7d9319feb918c083101a5ae645c5baef673c0c65775cb27a9997d6b.jpg)

Figure 4: LED locations

Table 2: System LED status

<table><tr><td>LED</td><td>Function</td><td>Color</td><td>Description</td></tr><tr><td>LED3</td><td>GPU Active</td><td>Green</td><td>On: GPU readyOff: GPU not ready</td></tr><tr><td>LED4</td><td>All Power Good</td><td>Green</td><td>On: All power readyOff: All power not ready</td></tr><tr><td>LED5</td><td>MXM Critical Temperature</td><td>Red</td><td>On: Temperature too highOff: Temperature normal</td></tr><tr><td>LED6</td><td>Input Power Failure</td><td>Red</td><td>On: Input power failOff: Input power pass</td></tr><tr><td>LED7</td><td>Ambient Temperature Alert</td><td>Yellow</td><td>On: temperature too highOff: temperature normal</td></tr><tr><td>LED8</td><td>MXM High Temperature alert</td><td>Yellow</td><td>On: temperature too highOff: temperature normal</td></tr><tr><td>LED12</td><td>IPMC Heartbeat</td><td>Green</td><td>Flashing: IPMC readyOff: IPMC not ready</td></tr><tr><td>LED14</td><td>IPMC WDT</td><td>Red</td><td>On: WDT start upOff: WDT not working</td></tr><tr><td>LED15</td><td>MTN_MODE SEL (RS232/UART)</td><td>Red</td><td>On: RS232Off: UART Mode</td></tr></table>

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# 5 Driver Installation

The VPX3-MXM/A4500 drivers are available on the ADLINK website:

https://www.adlinktech.com/products/vpx/vpxgraphicscards\_xmcmodules/vpx3-mxm\_a4500?lang=n

ADLINK provides validated drivers for Windows & Linux. We recommend using these drivers to ensure compatibility.

Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.

1. Install the chipset driver by extracting the contents of Nvidia-Win10\_x64(551.61) or Nvidia-Linuxx86\_64(550.120).run, running the program setup.exe.
2. The driver package will auto-extract to the default location. Change the path if desired.
3. Continue the driver installation as instructed.

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# 6 Connector Pinouts and Jumper Settings

# VPX Connectors

P0 Connector (SOSA SKU)

<table><tr><td>Pin</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>P12V</td><td>P12V</td><td>P12V</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>2</td><td>P12V</td><td>P12V</td><td>P12V</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>3</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>4</td><td>IPMB_CLK</td><td>IPMB_DAT</td><td>GND</td><td>NC</td><td>GND</td><td>SYSTEM RESET</td><td>NVMRO</td></tr><tr><td>5</td><td>GAP</td><td>GA4</td><td>GND</td><td>P3V3_AUX</td><td>GND</td><td>IPMA_CLK</td><td>IPMA_DAT</td></tr><tr><td>6</td><td>GA3</td><td>GA2</td><td>GND</td><td>NC</td><td>GND</td><td>GA1</td><td>GA0</td></tr><tr><td>7</td><td>JTAG_TCK</td><td>GND</td><td>JTAG_TDO</td><td>JTAG_TDI</td><td>GND</td><td>JTAG_TMS</td><td>JTAG_TRST</td></tr><tr><td>8</td><td>GND</td><td>REF_CLK-</td><td>REF_CLK+</td><td>GND</td><td>RES_BUS-</td><td>RES_BUS+</td><td>GND</td></tr></table>

P1 Connector

<table><tr><td>Pin</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>GDiscrete1#</td><td>GND</td><td>EP00_T-</td><td>EP00_T+</td><td>GND</td><td>EP00_R-</td><td>EP00_R+</td></tr><tr><td>2</td><td>GND</td><td>EP01_T-</td><td>EP01_T+</td><td>GND</td><td>EP01_R-</td><td>EP01_R+</td><td>GND</td></tr><tr><td>3</td><td>P1_VBAT</td><td>GND</td><td>EP02_T-</td><td>EP02_T+</td><td>GND</td><td>EP02_R-</td><td>EP02_R+</td></tr><tr><td>4</td><td>GND</td><td>EP03_T-</td><td>EP03_T+</td><td>GND</td><td>EP03_R-</td><td>EP03_R+</td><td>GND</td></tr><tr><td>5</td><td>SYSCON#</td><td>GND</td><td>EP04_T-</td><td>EP04_T+</td><td>GND</td><td>EP04_R-</td><td>EP04_R+</td></tr><tr><td>6</td><td>GND</td><td>EP05_T-</td><td>EP05_T+</td><td>GND</td><td>EP05_R-</td><td>EP05_R+</td><td>GND</td></tr><tr><td>7</td><td>NC</td><td>GND</td><td>EP06_T-</td><td>EP06_T+</td><td>GND</td><td>EP06_R-</td><td>EP06_R+</td></tr><tr><td>8</td><td>GND</td><td>EP07_T-</td><td>EP07_T+</td><td>GND</td><td>EP07_R-</td><td>EP07_R+</td><td>GND</td></tr><tr><td>9</td><td>Maintenance Port TX</td><td>GND</td><td>EP08_T-</td><td>EP08_T+</td><td>GND</td><td>EP08_R-</td><td>EP08_R+</td></tr><tr><td>10</td><td>GND</td><td>EP09_T-</td><td>EP09_T+</td><td>GND</td><td>EP09_R-</td><td>EP09_R+</td><td>GND</td></tr><tr><td>11</td><td>Maintenance Port RX</td><td>GND</td><td>EP10_T-</td><td>EP10_T+</td><td>GND</td><td>EP10_R-</td><td>EP10_R+</td></tr><tr><td>12</td><td>GND</td><td>EP11_T-</td><td>EP11_T+</td><td>GND</td><td>EP11_R-</td><td>EP11_R+</td><td>GND</td></tr><tr><td>13</td><td>NC</td><td>GND</td><td>EP12_T-</td><td>EP12_T+</td><td>GND</td><td>EP12_R-</td><td>EP12_R+</td></tr><tr><td>14</td><td>GND</td><td>EP13_T-</td><td>EP13_T+</td><td>GND</td><td>EP13_R-</td><td>EP13_R+</td><td>GND</td></tr><tr><td>15</td><td>MASKABLE RESET#</td><td>GND</td><td>EP14_T-</td><td>EP14_T+</td><td>GND</td><td>EP14_R-</td><td>EP14_R+</td></tr><tr><td>16</td><td>GND</td><td>EP15_T-</td><td>EP15_T+</td><td>GND</td><td>EP15_R-</td><td>EP15_R+</td><td>GND</td></tr></table>

P2 Connector (DP SKU)

<table><tr><td>Pin</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>P3V3_DPA</td><td>GND</td><td>DPA_L1-</td><td>DPA_L1+</td><td>GND</td><td>DPA_L0-</td><td>DPA_L0+</td></tr><tr><td>2</td><td>GND</td><td>DPA_L3-</td><td>DPA_L3+</td><td>GND</td><td>DPA_L2-</td><td>DPA_L2+</td><td>GND</td></tr><tr><td>3</td><td>P3V3_DPB</td><td>GND</td><td>DPA_CFG1</td><td>HOTPLUGA</td><td>GND</td><td>DPA_AUX-</td><td>DPA_AUX+</td></tr><tr><td>4</td><td>GND</td><td>DPB_L1-</td><td>DPB_L1+</td><td>GND</td><td>DPB_L0-</td><td>DPB_L0+</td><td>GND</td></tr><tr><td>5</td><td>P3V3_DPC</td><td>GND</td><td>DPB_L3-</td><td>DPB_L3+</td><td>GND</td><td>DPB_L2-</td><td>DPB_L2+</td></tr><tr><td>6</td><td>GND</td><td>DPB_CF G1</td><td>HOTPLUG B</td><td>GND</td><td>DPB_AUX-</td><td>DPB_AUX+</td><td>GND</td></tr><tr><td>7</td><td>P3V3_DPD</td><td>GND</td><td>DPC_L1-</td><td>DPC_L1+</td><td>GND</td><td>DPC_L0-</td><td>DPC_L0+</td></tr><tr><td>8</td><td>GND</td><td>DPC_L3-</td><td>DPC_L3+</td><td>GND</td><td>DPC_L2-</td><td>DPC_L2+</td><td>GND</td></tr><tr><td>9</td><td>P3V3_DPE</td><td>GND</td><td>DPC_CFG1</td><td>HOTPLUGC</td><td>GND</td><td>DPC_AUX-</td><td>DPC_AUX+</td></tr><tr><td>10</td><td>GND</td><td>DPD_L1-</td><td>DPD_L1+</td><td>GND</td><td>DPD_L0-</td><td>DPD_L0+</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>GND</td><td>DPD_L3-</td><td>DPD_L3+</td><td>GND</td><td>DPD_L2-</td><td>DPD_L2+</td></tr><tr><td>12</td><td>GND</td><td>DPD_CF G1</td><td>HOTPLUG D</td><td>GND</td><td>DPD_AUX-</td><td>DPD_AUX+</td><td>GND</td></tr><tr><td>13</td><td>NC</td><td>GND</td><td>DPE_L1-</td><td>DPE_L1+</td><td>GND</td><td>DPE_L0-</td><td>DPE_L0+</td></tr><tr><td>14</td><td>GND</td><td>DPE_L3-</td><td>DPE_L3+</td><td>GND</td><td>DPE_L2-</td><td>DPE_L2+</td><td>GND</td></tr><tr><td>15</td><td>NC</td><td>GND</td><td>DPE_CFG1</td><td>HOTPLUGE</td><td>GND</td><td>DPE_AUX-</td><td>DPE_AUX+</td></tr><tr><td>16</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td><td>NC</td><td>NC</td><td>GND</td></tr></table>

DDI Port A: DPA\_xx

DDI Port B: DPB\_xx

DDI Port C: DPC\_xx

DDI Port D: DPD:xx

DDI Port E: No Function

![An icon depicting a white document with a folded upper right corner and faint horizontal lines, overlaid with a large red checkmark.](.vpx3-mxm-a4500-50m-37622-1000-10/0acc59163c7b75d8f88d17369b35f03e6c184c0fdffab5a44f114fc96aae2d88.jpg)
NOTE:

• VPX-MXM/A4500 supports up to 4x DisplayPort.

• DP[A:D]\_CFG1 for DP++ of CONFIG1 pin definition in DP connector.

• HOTPLUG[A:D] for DP port hot-plug detection.

• 3.3V for DP.

# 7 RTM Board Interfaces

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the VPX3-RMXM-DP RTM.

# VPX-RMXM-DP Block Diagram

![The diagram displays a block diagram with the following elements and connections:\n\n*   **RP0**: A large vertical rectangular block on the left with a green border. Inside, the text 'RP0' is centered in large green letters. On the right edge of this block, there are labels for connections.\n*   **Power Terminal**: A horizontal rectangular block on the right with a blue border containing the text 'Power Terminal'.\n*   **Connections**:\n    *   Two horizontal lines connect the **P12_PSU** and **P3V3_AUX** labels on the RP0 block to the **Power Terminal** block.\n    *   Two additional horizontal lines extend from the lower portion of the RP0 block to the right. They terminate at black diamond shapes. The upper diamond is labeled **JTAG** and the lower diamond is labeled **SMBUS**.](.vpx3-mxm-a4500-50m-37622-1000-10/8cb99195e9eeca585604339cb3178db38dc281d291cc745526ed71dfe90027d5.jpg)

![The diagram illustrates a mapping between interface labels and connector functions.\n\n**Left Side:**\nA large rectangular box with a green border contains the text '**RP1/2**'. To its right, five labels are arranged vertically:\n*   **DP_A**\n*   **DP_B**\n*   **DP_C**\n*   **DP_D**\n*   **DP_E**\n\n**Right Side:**\nFive rectangular boxes with blue borders are stacked vertically. From top to bottom, they contain the following text:\n*   **Mini DP_A Connector**\n*   **Mini DP_B Connector**\n*   **Mini DP_C Connector**\n*   **Mini DP_D Connector**\n*   **No Function**\n\n**Connections:**\nHorizontal lines connect each label on the left to its corresponding block on the right:\n*   **DP_A** connects to **Mini DP_A Connector**\n*   **DP_B** connects to **Mini DP_B Connector**\n*   **DP_C** connects to **Mini DP_C Connector**\n*   **DP_D** connects to **Mini DP_D Connector**\n*   **DP_E** connects to **No Function**](.vpx3-mxm-a4500-50m-37622-1000-10/02a94b7be5aa87597a2ba8ce4f1e0e2113c5137fb2487183892619aa552152b3.jpg)

Figure 5: VPX3-RMXM-DP functional block diagram

![A white document icon featuring a folded top-left corner and horizontal lines, overlaid with a large red checkmark.](.vpx3-mxm-a4500-50m-37622-1000-10/32836d71e848353d4350e96e84ca4d0d1a6ae529633cb67350a58a49dc945648.jpg)
NOTE:

The VPX3-MXM/A4500 supports 4x DP outputs. Ports A, B, C, D are active on the RTM.

# RTM Board Layout

![A\nB\nC D E](.vpx3-mxm-a4500-50m-37622-1000-10/8ac416518cac763e1a7b17ea1a89652f1ddff0c6c15429d3fa7d1be011bf9a18.jpg)

DP A-D
![DP\nE\nDP\nD\nDP\nC\nDP\nB\nDP\nA](.vpx3-mxm-a4500-50m-37622-1000-10/850c807e221382ea8552425b5a632de330b3a212ff44478e1fdf39578823e3d9.jpg)

Figure 6: RTM board layout

Table 3: RTM board labels

<table><tr><td>A</td><td>JTAG Header</td><td>D</td><td>3.3V Power Terminal (No Function)</td></tr><tr><td>B</td><td>IPM1/IPM2 Selection Switch</td><td>E</td><td>Ground Terminal</td></tr><tr><td>C</td><td>5V Power Terminal (No Function)</td><td colspan="2"></td></tr></table>

![The image displays a digital icon representing a document. It features a white piece of paper with a black outline and a folded corner at the top right. Inside the paper, there are several horizontal black lines suggesting text. A large, bold red checkmark is superimposed over the document, indicating approval or verification.](.vpx3-mxm-a4500-50m-37622-1000-10/d40ace331b8755179fb53f7c71e53ae8bcf2b3c011570184b509728d80874412.jpg)
NOTE:

The VPX3-MXM/A4500 supports 4x DP outputs. Ports A, B, C, D are active on the VPX3-RMXM-DP.

# RTM Connector Pin Assignments

# VPX3-RMXM-DP Rear I/O Connectors

Mini DisplayPort Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>11</td><td>DP1_TXN1_CN</td></tr><tr><td>2</td><td>DP_CN_HPD</td><td>12</td><td>DP1_TXN3_CN</td></tr><tr><td>3</td><td>DP1_TXP0_CN</td><td>13</td><td>GND</td></tr><tr><td>4</td><td>DP1_CFG1_CN</td><td>14</td><td>GND</td></tr><tr><td>5</td><td>DP1_TXN0_CN</td><td>15</td><td>DP1_TXP2_CN</td></tr><tr><td>6</td><td>DP1_CFG2_CN</td><td>16</td><td>DP_AUX_C_P</td></tr><tr><td>7</td><td>GND</td><td>17</td><td>DP1_TXN2_CN</td></tr><tr><td>8</td><td>GND</td><td>18</td><td>DP_AUX_C_N</td></tr><tr><td>9</td><td>DP1_TXP1_CN</td><td>19</td><td>GND</td></tr><tr><td>10</td><td>DP1_TXP3_CN</td><td>20</td><td>P_+3V3_DP1_CN</td></tr></table>

![The image displays a schematic symbol for an electronic component, likely an integrated circuit. It features a square outline with rounded corners. Inside this outer square is a smaller, thick-bordered square, also with rounded corners. Within the inner square are two horizontal rows of small squares representing pins, with 12 squares in the top row and 12 in the bottom row. At the four corners of the outer square are the numbers '19' (top left), '1' (top right), '20' (bottom left), and '2' (bottom right).](.vpx3-mxm-a4500-50m-37622-1000-10/68ed1db0031d93cc6b33b7c493e84e3a3461751bc1a2d744f8c30276743ec522.jpg)

IPMC Debug Port (RJ-45)

<table><tr><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>NC</td></tr><tr><td>2</td><td>NC</td></tr><tr><td>3</td><td>MTN_TXD</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>MTN_RXD</td></tr><tr><td>7</td><td>NC</td></tr><tr><td>8</td><td>NC</td></tr></table>

![The image displays a schematic diagram featuring a grey, abstract shape resembling a connector or plug enclosed within a thin rectangular border. At the bottom, the number '8' is positioned on the left and the number '1' is on the right. Thin black lines extend from the bottom of the central grey shape downwards to these respective numbers. The background is white.](.vpx3-mxm-a4500-50m-37622-1000-10/d1a3771d3bb6526f85d4fe80fbf1bd80cffa9a9b77a86ea18e9e4040771c9f53.jpg)

# RTM Onboard Connectors and Switches

JTAG Header

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TCK</td></tr><tr><td>3</td><td>NC</td></tr><tr><td>4</td><td>TDO</td></tr><tr><td>5</td><td>+3.3V</td></tr><tr><td>6</td><td>TMS</td></tr><tr><td>7</td><td>TRST</td></tr><tr><td>8</td><td>+3.3V</td></tr><tr><td>9</td><td>GND</td></tr><tr><td>10</td><td>TDI</td></tr></table>

![The image features a vertical column of four stacked, rounded-rectangular frames, each containing two smaller empty squares. To the left of the column is the number '2', and to the right is the number '1'.](.vpx3-mxm-a4500-50m-37622-1000-10/5ec92562b7daef7c5e5083a5718f16fd9f8027bad6557b64d7e21e4c84bd4ec9.jpg)

IPM1/IPM2 Selection Switch

<table><tr><td>Function</td><td>Pin Settings</td></tr><tr><td>IPM1</td><td>1,2 OFF3,4 ON</td></tr><tr><td>IPM2</td><td>1,2 ON3,4 OFF</td></tr></table>

# Safety Instructions

Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.

Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:

Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
 Keep equipment properly ventilated (do not block or cover ventilation openings).
 Make sure to use recommended voltage and power source settings.
 Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
 Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

# Getting Services

Ask an Expert: https://www.adlinktech.com/en/Askanexpert

# ADLINK Technology, Inc.

Address: No. 66, Huaya 1st Road, Guishan District Taoyuan City 333, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5723

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address: 6450 Via Del Oro, San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Address: Hans-Thoma-Strasse 8-10, 68163, Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
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