# VPX3-TL Series

SOSA-aligned Rugged 3U VPX Processor Blade with Intel $^{®}$ Xeon $^{®}$ W11865MRE

User's Manual

![Close-up of a green printed circuit board with various electronic components and connectors (no visible text or symbols)](.vpx3-tl-50m-31129-1010/9231dcc70eb4964e26a9b88022c3cf61ab4da38189b9240fb40d18dbea2140d1.jpg)

Manual Rev.: 1.1

Revision Date: October 19, 2023

Part No: 50M-31129-1010

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2023-07-05</td><td>Initial release</td></tr><tr><td>1.1</td><td>2023-10-19</td><td>Update storage specifications</td></tr></table>

# Preface

# Copyright © 2023 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with two crossed lines, no text or labels present](.vpx3-tl-50m-31129-1010/2402dbb6c9569cd90a6ba8e92d41ddc95a77b7851668f0b3d3d5d5126ad5109c.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.vpx3-tl-50m-31129-1010/7e98138791ddb3885bc34314905bcab0373c7a4843d68996d3be444bd3f264eb.jpg)

![Recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.vpx3-tl-50m-31129-1010/b557a504b7444c1b93a38ca1ea4128a9aaef3415689bdec205154ef8fa796730.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.vpx3-tl-50m-31129-1010/e2a91d19dad439c4899ecb9d05eb92f449264b24dcb3c97f4c36dda24f3f7f27.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.vpx3-tl-50m-31129-1010/1c214bd0d7868d17c4ecda272d6d03352582c466d4df1663ae8b9b0b7cf20e9d.jpg)

廢電池請回收

# California Proposition 65 Warning

![The image displays a yellow triangular warning sign with a thick black border. In the center of the triangle is a large black exclamation mark.](.vpx3-tl-50m-31129-1010/fd8e5c4323504a19c8834718100b5131bd0a732be67154db7c3da087ed4901eb.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white document icon featuring faint horizontal grey lines. A large, thick red checkmark is superimposed over the paper, angled upwards from the bottom left to the top right.](.vpx3-tl-50m-31129-1010/e9d367ddeba5e064207aea9913a334e03c18195b6d277cefdb9c208df2e0318a.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a close-up crop of a warning sign. It features a yellow triangle with a thick black border containing a large black exclamation point in the center. Above the triangle is the bottom edge of a thick black horizontal line, part of a larger rectangular frame.](.vpx3-tl-50m-31129-1010/0cab0cf13e500ba6f927705a14dcfe8f9147506ed5c9636cae28ee26b5f4b8ea.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image features a standard warning symbol consisting of a red triangle with a white border. Inside the triangle is a large white exclamation point (!). The symbol is positioned directly below a thick black horizontal line.](.vpx3-tl-50m-31129-1010/487e4510062a74fcfb39169c63edc679421fcff0266c4d4175817d5e7ce6ea9c.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History...... ii

# Preface .... iii

# List of Figures ...... vii

# List of Tables ix

# 1 Introduction ...... 1

1.1 Overview.... 1
1.2 Features.... 2
1.3 Block Diagrams.... 3
1.4 Model Number Decoder - Processor Blade 4
1.5 Package Contents 5

# 2 Specifications.... 7

2.1 VPX3-TL Blade Specifications.... 7
2.2 VPX3-TL-RL1 RTM Specifications 9
2.3 Power Consumption 10

# 3 Functional Description 11

3.1 Processors.... 11
3.2 Intel® Turbo Boost Technology 13
3.3 Chipset.... 13
3.4 USB 14
3.5 SPI BIOS 14
3.6 System Management Bus.... 14
3.7 Real Time Clock 14
3.8 Serial ATA Controller 14
3.9 PCI Express Interface 14
3.10 Intel ® Gigibit Ethernet Controller I225-IT.... 15
3.11 Ethernet for 10GbE.... 15
3.12 Graphics 15

3.13 GPIO Expander PCA9554 15
3.14 UART NCT5104D 15
3.15 TPM 16
3.16 Embedded Controller 16
3.17 XMC Site.... 16

# 4 VPX3-TL Board Interfaces.... 17

4.1 VPX3-TL Board Layout 17
4.2 VPX3-TL Mechanical Dimensions 19
4.3 VPX3-TL Connector Pin Assignments 20
4.4 Status LEDs 26

# 5 VPX3-TL-RL1 RTM 27

5.1 Connector Allocation.... 27
5.2 VPX3-TL-RL1 Block Diagram 28
5.3 VPX3-TL-RL1 RTM Board Layout 29
5.4 VPX3-TL-RL1 RTM Connector Pin Assignments 30

# 6 Getting Started 35

6.1 Installing the VPX3-TL to the Chassis 35
6.2 Installing the VPX3-TL-RL1 RTM to the Chassis.... 35
6.3 Driver Installation 36

# 7 Utilities.... 41

7.1 SEMA 41
7.2 Watchdog Timer.... 41

# 8 BIOS Setup 43

8.1 Starting the BIOS.... 43
8.2 Setup Menus.... 45

# Important Safety Instructions.... 47

# Getting Service 49

# List of Figures

Figure 1-1: VPX3-TL Functional Block Diagram .... 3
Figure 4-1: VPX3-TL Top Side Layout....17
Figure 4-2: VPX3-TL Bottom Side Layout....17
Figure 4-3: VPX3-TL Conduction-Cooled Mechanical Dimensions . 19
Figure 4-4: VPX3-TL Front View 26
Figure 5-1: VPX3-TL-RL1 RTM Functional Block Diagram....28
Figure 5-2: VPX3-TL-RL1 RTM Board Layout 29

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# List of Tables

Table 1-1: VPX3-TL SKU Table....4
Table 2-1: VPX3-TL Blade Specifications....7
Table 2-2: VPX3-TL-RL1 RTM Specifications 9
Table 4-1: VPX3-TL Board Layout Legend....18
Table 5-1: VPX3-TL-RL1 RTM Board Layout Legend ...... 29

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# 1 Introduction

# 1.1 Overview

The VPX3-TL Series is a 3U VPX processor blade based on the Intel® Xeon® W11865MRE Processor (formerly "Tiger Lake-H"), supporting up to 64GB DDR4-2666 soldered ECC memory, 2x 10GBASE-KR or 2x 1GBASE-KX, one XMC expansion slot with PCIe x8 Gen3 to P1 & P2 rear I/O, USB 3.0 and SATA 6GB/s; as well as a high performance NVMe/SATA M.2 slot for storage expansion up to 1TB (by BOM option). The SOSA-aligned design offers embedded computing capabilities that are easily reconfigurable and upgradable, highly cost-effective, and quick to develop and deploy.

The VPX3-TL Series with work station grade Intel® processor brings high-bandwidth, high-powered computing and artificial intelligence to demanding applications that expose hardware to extreme temperatures, vibration, and operating conditions.

Interoperability between different systems - including Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR), electronic warfare (EW), signals intelligence (SIGINT), cognitive radio and radar - is critical. The SOSA standard is one of several standards that fall broadly within the MOSA initiative. SOSA centers on key interfaces and open standards, based on the VPX standard (VITA 46/48/65), and aims to develop a common, modular hardware architecture across next-generation, mission-critical applications.

# 1.2 Features

Intel® Xeon® W11865MRE Processor (formerly "Tiger Lake-H"); up to 8 cores with 45 watt TDP
▶ SOSA-aligned and VITA 46/47/48/65 compliant for quick deployment
▶ 32GB DDR4-2666 soldered ECC SDRAM (roadmap to 64GB)
▶ Supports NVMe and SATA SSD up to 1TB (by BOM option)
▶ One XMC expansion slot with PCIe x8 Gen3
▶ Ethernet connectivity: 1x 2.5GBASE-T to P2; 2x 10GBASE-KR to P1; optional 2x 1GBASE-KX to P1
▶ 1x DisplayPort to P2, supports DP++ with resolution up to 8K/60Hz

# 1.3 Block Diagrams

![Based on the provided block diagram, here is a description of the labeled blocks and their connections:\n\n**Central Components:**\n*   **CPU:** `Intel® Xeon® W-11000E` (TCP0) connects to memory and the chipset.\n    *   **Memory:** Connected via `DDR4 Ch A` and `DDR4 Ch B` to two blocks labeled `DDR4 3200 16GB Max w ECC`.\n    *   **PCIe Lanes:**\n        *   `PCIE16 (0:7)` connects via `PCIe x4 Gen3` to `XMC J15`.\n        *   `PCIE16 (8:11)` connects via `PCIe x4 Gen3` to `XMC J16`.\n        *   `PCIE16 (12:15)` connects via `PCIe x4 Gen3` to the right bus `P1`.\n    *   **DMI:** `DMI(0:7)` connects via `DMI` to the chipset.\n*   **Chipset:** `Intel® RM590E Chipset` connects to various peripherals.\n    *   **Flex I/O:** `FLEX I/O(6:9)` and `FLEX I/O(26:29)` connect via dotted `PCIe x4 Gen3` lines to `XMC J16`.\n    *   **UART/IO:** `FLEX I/O(14:21)` (labeled `Maintenance port (COM1)`), `UART0`, and `FLEX IO (10:13)` are present.\n    *   **SPI:** `SPI0` connects to `TPM` and `MUX`. `SPI` interconnects `TPM` and `MUX`.\n    *   **eSPI:** `eSPI` connects to `eSPI to LPC ECE1200`.\n\n**Left Side (P2 Bus/Block):**\n*   **Top Connections:** `DisplayPort`, `X16s`, and `X8d` connect `P2` to the CPU. `X16s` and `X8d` also connect to `XMC J16`.\n*   **Mid Connections:**\n    *   `USB 2.0 x2` connects to the chipset (`USB2(1:2)`).\n    *   `USB 3.2 Gen1 x1` connects to the chipset (`FLEX I/O(0)`).\n    *   `2.5GBASE-T` connects to `2.5GLAN Intel® I225`, which connects via `PCIe x1 Gen3` to the chipset (`FLEX I/O(22)`).\n    *   `SATA 6Gb/s` connects to the chipset (`FLEX I/O(24)`).\n*   **Bottom Connections:**\n    *   `M.2 2242 M Key`, `RS232/422/485`, and `RS232` connect to `Tranceiver ISL41334`.\n    *   `Tranceiver ISL41334` connects to `SIO NCT5104D` via `UARTB (COM2)` and `UARTD (COM4)`.\n    *   `SIO NCT5104D` connects to an `IPMC` block via `UARTC (COM3)` and `UARTA (COM5)`.\n    *   `P2` connects to the same `IPMC` block via `IPMB`.\n    *   `P2` connects to `P0` via the `IPMC` block.\n*   **GPIO/EC:** `3.3V GPIO(2:4)` connects to `EC ITS121`, which connects via a dotted line to an `IPMC` block.\n\n**Right Side (P1 Bus/Block):**\n*   **Top Connections:** `X12d` connects `XMC J16` to `P1`.\n*   **Mid Connections:**\n    *   `Maintenance port (COM1)` connects to the chipset.\n    *   `10GBASE-KR x2` connects to `10GLAN Intel® X710-BM2`.\n    *   `10GLAN Intel® X710-BM2` connects via `PCIe x4 Gen3` to the chipset.\n*   **Bottom Connections:** `DP_CONFIG` (dotted) connects `P1` to `EC ITS121` (bottom right).\n\n**Bottom Right Components:**\n*   **Storage/Config:** `TPM`, `MUX`, `BIOS1`, and `BIOS2` are interconnected. `MUX` connects to `BIOS1` and `BIOS2`.\n*   **LPC Bridge:** `eSPI to LPC ECE1200` connects the chipset (`eSPI`) to an `IPMC` block (`LPC`).\n*   **GPIO/EC:** `3.3V GPIO1` connects to `EC ITS121`, which connects via dotted lines to `DP_CONFIG` and an `IPMC` block.\n\n**Other Labels:**\n*   `Reserved Circuit` labels a dotted line near the bottom right.](.vpx3-tl-50m-31129-1010/9ae0561c050180fa91325c519c9825f91f5e11d02863da399c6c06741db5a740.jpg)

Figure 1-1: VPX3-TL Functional Block Diagram

# 1.4 Model Number Decoder - Processor Blade

# VPX3-TL/W11865MRE/M32/XMC1.0-R2

![|    |    |    |\n(A)    (B)    (C)    (D)](.vpx3-tl-50m-31129-1010/f9bc45e43032f7157fd0701a8dbb0c91d9b5d4b888275e79c4d1510874703019.jpg)

# (A) CPU Code

W11865MRE = Intel® Xeon® W11865MRE Processor, 8 cores, 45W TDP

# (B) Memory Size Code

M32 = 32GB DDR4-2666 ECC soldered SDRAM

# (C) PCI Express interface code

▷ XMC1.0 = XMC 1.0 interface, 2x PCIe x4 Gen3 to P1
▷ XMC2.0 = XMC 2.0 interface, 2x PCIe x4 Gen3 to P1
▷ P16 = 2x PCIe x4 Gen3 to P1 + 2x PCIe x4 Gen3 to P1

# (D) Ruggedized Level Code

▷ R2 = Conduction Cooled version supporting -40°C to +85°C at card edge

VPX3-TL SKU Table

<table><tr><td>Function</td><td>XMC1.0</td><td>XMC2.0</td><td>P16</td></tr><tr><td>XMC</td><td>1.0 connector for expansionX16s+X8d to P2 and X12d to P1</td><td>2.0 connector for expansionX16s+X8d to P2 and X12d to P1</td><td>N/A</td></tr><tr><td>PCIe</td><td>2x PCIe x4 Gen3 to P1</td><td>2x PCIe x4 Gen3 to P1</td><td>2x PCIe x4 Gen3 to P12x PCIe x4 Gen3 to P2</td></tr></table>

Table 1-1: VPX3-TL SKU Table

# 1.5 Package Contents

The VPX3-TL is packaged with the following components. If any of the items on the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the VPX3-TL are non-standard configurations and may vary depending on customer requests.

# Processor Blade

▶ VPX3-TL

▷ CPU and memory specifications will differ depending on options selected
▷ Thermal module is assembled on the board

# Rear Transition Module (optional)

▶ VPX3-TL-RL1 RTM

# Test Backplane (optional)

▶ tBP-VPX3-TL test backplane

![The image shows a white document icon with a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark.](.vpx3-tl-50m-31129-1010/f84634b4c0dce1bf465de5db185cd1499642a094d60bc6733efcb64751533f3f.jpg)
NOTE:

The contents of non-standard VPX3-TL configurations may vary depending on the customer requirements.

![A yellow triangular warning sign with a black border containing a black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.vpx3-tl-50m-31129-1010/6d64a6bc481bcc7853859750fb8ee825744663650117a987ec06470f4309f583.jpg)

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

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# 2 Specifications

# 2.1 VPX3-TL Blade Specifications

<table><tr><td>VITA Standards</td><td>• VITA 46, 47, 48, 65 compliant • SOSA aligned</td></tr><tr><td>Module Profile</td><td>• MOD3-PAY-1F1F2U1TU1T1U1T-16.2.15-2</td></tr><tr><td>Slot Profile</td><td>• SLT3-PAY-1F1F2U1TU1T1U1T- 14.2.16</td></tr><tr><td>Processor</td><td>• Intel® Xeon® W11865MRE, up to 8 cores, 45W TDP</td></tr><tr><td>Chipset</td><td>• Intel® RM590E Chipset</td></tr><tr><td>Memory</td><td>• 32GB DDR4 soldered with ECC (roadmap to 64GB)</td></tr><tr><td>USB</td><td>• 2x USB 2.0 to P2 • 1x USB 3.2 Gen1 to P2 • Supports USB 3.0 power to P1/G7 (supply 0.9A) with over current protection • Supports USB 2.0 power to P2/G9 (supply 0.5A) with over current protection</td></tr><tr><td>XMC</td><td>• 1x PCIe x8 to J15 • Rear I/O (X16s + X8d) to P2 and X12d to P1 from J16</td></tr><tr><td>Gigabit Ethernet</td><td>• 1x 2.5GBASE-T to P2 supporting PXE and Wake on LAN (WOL)</td></tr><tr><td>PCI Express</td><td>• 2x PCIe x4 co-layout with XMC X8d+X16s on P2 (PCIe NT function not supported)</td></tr><tr><td>Storage</td><td>• 1x M2. 2242 onboard (M-Key), supports NVMe and SATA • 1x SATA 6Gb/s to P2 • M.2 devices supporting spec S1, S2, S3, D1, D2, D3, D4 • M.2 capacity up to 1TB</td></tr><tr><td>Graphics</td><td>• 1x DisplayPort to P2 • Resolution up to 8K/60Hz • Supports passive DP to HDMI dongle with BIOS selection</td></tr><tr><td>GPIO</td><td>• 1x GPIO to P1 • 3x GPIO to P2 • Supports +3.3V (default) or +5V GPIO (BOM option) • GPI with edge trigger or level trigger interrupt</td></tr></table>

Table 2-1: VPX3-TL Blade Specifications

<table><tr><td>Serial</td><td>COM1:2-wire TX/RX on P1 supporting TIA-232 &amp; LVCOMS (3.3V) mode selected by BIOS optionCOM2:1x RS-232/422/485 to P2 (RS232, 2-wire)Max. data rate for RS232/422/485 is 115200bpsRS485 mode supports auto flow controlRS232/422/485 mode selected by BIOS optionCOM3:1x RS-232 to P2 (2-wire, available when COM2 is set RS232</td></tr><tr><td>TPM</td><td>Discrete TPM 2.0 chipSupports Intel Secure Boot (UEFI)</td></tr><tr><td>LEDs</td><td>Power and SATA Activity LEDs on front panelReserved LED (for customer definition)Embedded Controller Status LED on front panel</td></tr><tr><td>Reset Button</td><td>On front panel</td></tr><tr><td>Watchdog Timer</td><td>Provided by SEMA</td></tr><tr><td>Environmental</td><td>Operating Temp.-40°C to +85°C at wedge locks (VITA47.0, ECC4-CC4)Storage Temp:-55°C to +105°CVibration:Random: 12Grms, 5Hz to 2000Hz (VITA47.0, ECC4-V3)Sinusoidal: 5g, 20Hz to 2000HzShock: 40g, 11 ms (VITA47.0, ECC4-OS2)Relative Humidity:95% non-condensingAltitude: 60,000 ft. (operating)</td></tr><tr><td>EMC</td><td>CE (EN555032 / EN55035) ; FCC Part 15B Class A</td></tr></table>

Table 2-1: VPX3-TL Blade Specifications

Note: Specifications are subject to change without prior notice.

# 2.2 VPX3-TL-RL1 RTM Specifications

<table><tr><td>Ethernet</td><td>• 2x 10GBASE-KR via RP1• 1x 2.5GBASE-T via RP1</td></tr><tr><td>Graphics</td><td>• 1x DisplayPort signal via RP1</td></tr><tr><td>SATA</td><td>• 1x SATA 6Gb/s via RP1 (7-pin vertical SATA connector)</td></tr><tr><td>USB</td><td>• 1x USB 3.0 (backwards compatible) via RP1</td></tr><tr><td>Serial</td><td>• Serial Port 1: RS232 (2T2R) via RP1 (DB-9 connector)• Serial Port 2: RS232 (2T2R) via RP2 (2x5 pin header)</td></tr><tr><td>GPIO</td><td>• 1 bit GPIO signal via RP1, 3 bits GPIO signals via RP2</td></tr><tr><td>PCIe</td><td>• 1x PCIe x4 via RP0• 2x PCIe x4 via RP1• 2x PCIe x4 via RP2</td></tr><tr><td>XMC</td><td>• X12D via RP1• X8D via RP2• X16S via RP2</td></tr><tr><td>JTAG</td><td>• JTAG via RP0 (2x5 pin header)</td></tr><tr><td>Reset</td><td>• Reset via RP0</td></tr><tr><td>SMBus</td><td>• SMBus signal via RP0</td></tr><tr><td>Power</td><td>• Power terminal for +12V, +5V, +3.3V, GND</td></tr></table>

Table 2-2: VPX3-TL-RL1 RTM Specifications

Note: Specifications are subject to change without prior notice.

# 2.3 Power Consumption

This section provides information on the power consumption of the VPX3-TL when using the Intel® Xeon® W-11865MRE processor with Dual Channel 16GB DDR4-2666 soldered memory. The VPX3-TL is powered by 12V. Windows 10 idle mode power consumption was measured running BurnInTest at 100% loading. Windows 10 Max Loading power consumption was measured running Intel TAT test at 100% loading.

<table><tr><td>Processor</td><td>Xeon® W-11865MRE (2.6 GHz)</td></tr><tr><td colspan="2">Windows Idle mode, EIST Enabled</td></tr><tr><td>12V (A)</td><td>2.55</td></tr><tr><td>Power Cons. (W)</td><td>32.48</td></tr><tr><td colspan="2">Windows Idle mode, EIST Disabled</td></tr><tr><td>12V (A)</td><td>2.53</td></tr><tr><td>Power Cons. (W)</td><td>32.17</td></tr><tr><td colspan="2">Windows Max Loading mode, EIST Enabled</td></tr><tr><td>Package Power reading (TAT)</td><td>49.86</td></tr><tr><td>Package Temperature reading (TAT)</td><td>88</td></tr><tr><td>CPU DTS reading (TAT)</td><td>87</td></tr><tr><td>CPU frequency reading (TAT)</td><td>2867</td></tr><tr><td>12V (A)</td><td>6.64</td></tr><tr><td>Power Cons. (W)</td><td>81.83</td></tr><tr><td colspan="2">Windows Max Loading mode, EIST Disabled</td></tr><tr><td>Package Power reading (TAT)</td><td>45.72</td></tr><tr><td>Package Temperature reading (TAT)</td><td>83</td></tr><tr><td>CPU DTS reading (TAT)</td><td>82</td></tr><tr><td>CPU frequency reading (TAT)</td><td>2600</td></tr><tr><td>12V (A)</td><td>6.28</td></tr><tr><td>Power Cons. (W)</td><td>77.26</td></tr></table>

# 3 Functional Description

The following sections describe the VPX3-TL features and functions.

# 3.1 Processors

The Intel® Xeon® W-11865MRE is a 64-bit, multi-core processor built on 14-nanometer process technology. The processor is designed for a two-chip platform consisting of a processor and chipset. The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics and Integrated Memory Controller.

<table><tr><td>Features</td><td>Intel® Xeon® W-11865MRE</td></tr><tr><td>Configurable TDP-up Base Freq.</td><td>2.6 GHz</td></tr><tr><td>Configurable TDP-down Base Freq.</td><td>2.1 GHz</td></tr><tr><td>Max. Turbo Freq.</td><td>4.7 GHz</td></tr><tr><td>Last Level Cache</td><td>24MB</td></tr><tr><td>No. of Cores/Threads</td><td>8/16</td></tr><tr><td>Maximum Power (TDP $^{1}$ )</td><td>45 W</td></tr><tr><td> $T_{Junction}^{2}$ </td><td>100°C</td></tr></table>

# Notes:

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.

2. The maximum temperature allowed at the processor die.

# Supported Technologies

Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
Intel® Virtualization Technology (Intel® VT-x)
Intel® VT-x with Extended Page Tables (EPT)
Intel® Hyper-Threading Technology
Intel® Turbo Boost Technology
Intel® Speed Shift Technology
▶ Thermal Monitoring Technologies

# Interfaces

▶ Dual channel DDR4 memory with two channel of soldered SDRAM
▶ Memory DDR4 data transfer rates of 3200 MT/s
▶ 64-bit wide channels plus 8-bits of ECC support for each channel
▶ System Memory Interface I/O Voltage of 1.2V
The PCI Express lanes are fully-compliant with the PCI Express Base Specification, Revision 3.0, including support for 8 GT/s transfer speeds.

# 3.2 Intel® Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and/or render clock frequency when there is sufficient power headroom, and the product is within specified temperature and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. The processor supports a Turbo mode where the processor can use the thermal capacity associated with package and run at power levels higher than TDP power for short durations. This improves the system responsiveness for short, bursty usage conditions.

Turbo Mode availability is independent of the number of active cores; however, the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load, the number of active cores, user configurable settings, operating environment, and system design. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

# 3.3 Chipset

The Mobile Intel® 500 Series Chipset provides extensive I/O support. Functions and capabilities include:

▶ PCI Express Base Specification, Revision 3.0
▶ Interrupt controller and timer functions
▶ Integrated Serial ATA host controller 3.2, supports data transfer rates up to 6Gb/s on all ports
▶ USB Revision 3.2/2.0
▶ Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
▶ System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
Intel® High Definition Audio
Intel® Rapid Storage Technology
Intel® Platform Trust Technology
▶ Serial Peripheral Interface (SPI) Support

# 3.4 USB

The VPX3-TL provides one USB 3.2 Gen1 port to the P2 connector supporting data transfers up to 5Gb/s, and one USB 2.0 port to the P2 connector supporting data transfers up to 480 Mb/s.

# 3.5 SPI BIOS

The VPX3-TL implements a dual BIOS feature. Each SPI flash has a capacity of 256Mb. When the main BIOS crashes, the backup BIOS will be used to boot the device.

# 3.6 System Management Bus

The PCH provides a System Management Bus (SMBus) Specification Version 2.0 compliant Host Controller as well as an SMBus Slave Interface. The PCH provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves) as well as I2C compatible devices.

# 3.7 Real Time Clock

The PCH contains a real-time clock with 256 bytes of battery-backed RAM. The internal RTC module provides two key functions: keeping the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal.

# 3.8 Serial ATA Controller

The VPX3-TL has one SATA port capable of 6Gb/s transfers with all capable SATA devices.

# 3.9 PCI Express Interface

The VPX3-TL is compatible with the VPX ANSI/VITA 46.0-2007 standard. The VPX3-TL supports 1 x8 or 2 x4 PCIe bus to the XMC module and 2x PCIe x4 Gen3 to P2.

# 3.10 Intel ® Gigibit Ethernet Controller I225-IT

The VPX3-TL has one 2.5GBASE-T LAN interface for network access. The Intel® 2.5 Gigabit Ethernet Controller I225 is a single-port, compact, low power Gigabit Ethernet (GbE) controller. It is a fully-integrated GbE Media Access Control (MAC) and Physical Layer (PHY) device, offering 10/100/1000/2500 Mb/s data rates. The interface-to-host system is a one lane PCIe Gen 2 version 3.1.

# 3.11 Ethernet for 10GbE

The VPX3-TL has two 10GBASE-KR LAN interfaces for network access. The dual 10GBASE-KR is implemented via an Intel® Ethernet Controller X710-BM2, a dual-port 10GBASE-KR controller via PCIe x4 Gen3 from the TGL-H host.

# 3.12 Graphics

The VPX3020 provides one DisplayPort consisting of a Main Link, Auxiliary channel and a Hot-Plug Detect signal. The DisplayPort supports VESA DisplayPort 1.2 specifications.

# 3.13 GPIO Expander PCA9554

The VPX3-TL offers 4x GPIO pins which are configurable as input or output signals, 3.3V tolerant, and SCI (GPE) and IOAPIC interrupt capable.

# 3.14 UART NCT5104D

The NCT5104D is a LPC to UART IC, which supports 4 high-speed serial communication ports (UART). Each UART includes a 128-byte send/receive FIFO, a programmable baud rate generator, complete modem-control capability, and a processor interrupt system. The UART supports legacy speeds up to 115.2K bps as well as even higher baud rates of 230K, 460K, or 921K bps to support higher speed modems.

In addition to UART, the NCT5104D provides flexible I/O control functions through a set of general purpose I/O (GPIO) ports. These GPIO ports may serve as simple I/O ports or may be individually configured to provide alternative functions. The

NCT5104D supports port 80 decode on the LPC bus and could output the signal via SOUTC. It also supports LED control.

# 3.15 TPM

The Infineon SLB 9665 TPM 2.0 is a fully standard compliant TPM based on the latest Trusted Computing Group (TCG) specification 2.0 and features Low Pin Count (LPC) interface.

# 3.16 Embedded Controller

The VPX3-TL implements an ITE IT5121VG as embedded controller. The IT5121VG communicates with the host system through an eSPI v1.0 interface.

# 3.17 XMC Site

The VPX3-TL Series supports one XMC site for rear I/O expansion. The XMC site provides a x8 PCI Express Gen 3.0 lane. Jn2 rear XMC I/O connector is compliant to VITA 46.9, X8d+X12d+X16S.

# 4 VPX3-TL Board Interfaces

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the VPX3-TL.

# 4.1 VPX3-TL Board Layout

![C\nI\nA\nB\nF\nD\nG\nE\nH](.vpx3-tl-50m-31129-1010/72344f51c75aaa0ffdce5ad1dc9958aa5ae20d82112fec2499aa3192e0e1fa0a.jpg)

Figure 4-1: VPX3-TL Top Side Layout
![J\nL\nK\nC](.vpx3-tl-50m-31129-1010/ee9948a33bd6ca6a91471720b6384df1352894890f355af9b79c1c7180d32668.jpg)

Figure 4-2: VPX3-TL Bottom Side Layout

<table><tr><td>A</td><td>CPU (W-11865MRE)</td><td>G</td><td>XMC Connector(X8d+X12d+X16s)</td></tr><tr><td>B</td><td>Chipset (PCH RM590E)</td><td>H</td><td>M.2 Connector (M Key)</td></tr><tr><td>C</td><td>DDR4 ECC Memory</td><td>I</td><td>Embedded Controller (IT5121)</td></tr><tr><td>D</td><td>Ethernet Controller (FTX710-BM2)</td><td>J</td><td>Super IO (NCT5104D)</td></tr><tr><td>E</td><td>IPMC</td><td>K</td><td>LAN Transformer</td></tr><tr><td>F</td><td>XMC Primary Connector</td><td>L</td><td>Ethernet Controller (I215IT)</td></tr></table>

Table 4-1: VPX3-TL Board Layout Legend

# 4.2 VPX3-TL Mechanical Dimensions

Conduction-Cooled Version
![The image displays a technical line drawing of a rectangular electronic component, presented in three orthographic views with blue dimension lines.\n\n*   **Top View:** A profile view at the top indicates a vertical dimension of `(23.78)`.\n*   **Front View:** The central view shows the face of the component, featuring mounting holes with crosses and a connector edge on the right. It is labeled with a horizontal width of `(160)` and a vertical height of `(99.85)`.\n*   **Side View:** A side profile view is positioned on the left.\n\nAt the bottom center, the text reads: **Dimensions in mm**.](.vpx3-tl-50m-31129-1010/ca589dc7d2164e0e79dadd16f5812ec616088b3cee4e06bfaf2960cc0509424c.jpg)
Figure 4-3: VPX3-TL Conduction-Cooled Mechanical Dimensions

# 4.3 VPX3-TL Connector Pin Assignments

XMC Connectors
![F1\nF19\nA1\nA19](.vpx3-tl-50m-31129-1010/1dc8968fe0b44ed99540d480e7f60f4eab12bd7add678fcea3ef36f4f4e5ae44.jpg)

JN15 Connector Pin Definition (Primary)

<table><tr><td>Pin</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>PET0p0</td><td>PET0n0</td><td>3.3V</td><td>PET0p1</td><td>PET0n1</td><td>VPWR</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>TRST#</td><td>GND</td><td>GND</td><td>RESET#</td></tr><tr><td>3</td><td>PET0p2</td><td>PET0n2</td><td>3.3V</td><td>PET0p3</td><td>PET0n3</td><td>VPWR</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>TCK</td><td>GND</td><td>GND</td><td>PULL UP</td></tr><tr><td>5</td><td>PET0p4</td><td>PET0n4</td><td>3.3V</td><td>PET0p5</td><td>PET0n5</td><td>VPWR</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>TMS</td><td>GND</td><td>GND</td><td>12V_AUX</td></tr><tr><td>7</td><td>PET0p6</td><td>PET0n6</td><td>3.3V</td><td>PET0p7</td><td>PET0n7</td><td>VPWR</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>TDI</td><td>GND</td><td>GND</td><td>-12V_AUX</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>TDO</td><td>GND</td><td>GND</td><td>GA0</td></tr><tr><td>11</td><td>PER0p0</td><td>PER0n0</td><td>MBIST#</td><td>PER0p1</td><td>PER0n1</td><td>VPWR</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>GA1</td><td>GND</td><td>GND</td><td>PRSNT#</td></tr><tr><td>13</td><td>PER0p2</td><td>PER0n2</td><td>3.3V_AUX</td><td>PER0p3</td><td>PER0n3</td><td>VPWR</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GA2</td><td>GND</td><td>GND</td><td>MSDA</td></tr><tr><td>15</td><td>PER0p4</td><td>PER0n4</td><td>NC</td><td>PER0p5</td><td>PER0n5</td><td>VPWR</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>XMC_NVMRO</td><td>GND</td><td>GND</td><td>MSCL</td></tr><tr><td>17</td><td>PER0p6</td><td>PER0n6</td><td>NC</td><td>PER0p7</td><td>PER0n7</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>19</td><td>REF_CLK+</td><td>REF_CLK-</td><td>NC</td><td>WAKE#</td><td>NC</td><td>NC</td></tr></table>

![The image displays a graphic icon of a white document with a folded upper-left corner. Faint grey horizontal lines run across the page, resembling a list. A large, bold red checkmark is superimposed over the document, drawn diagonally from the upper right to the lower left.](.vpx3-tl-50m-31129-1010/3428a50b37abed4c7578cb0cb6381e7520cad0bf9938f9b9cdbc0d36cff6071a.jpg)
NOTE:

The signal definitions of the primary XMC connector (J15) are presented relative to the XMC Mezzanine card.

J16 Connector Pin Definition (X8d+X12d+X16s)

<table><tr><td>Pin</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>XMC_A1+</td><td>XMC_B1-</td><td>NC</td><td>XMC_D1+</td><td>XMC_E1-</td><td>NC</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>3</td><td>XMC_A3+</td><td>XMC_B3-</td><td>NC</td><td>XMC_D3+</td><td>XMC_E3-</td><td>NC</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>5</td><td>XMC_A5+</td><td>XMC_B5-</td><td>NC</td><td>XMC_D5+</td><td>XMC_E5-</td><td>NC</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>7</td><td>XMC_A7+</td><td>XMC_B7-</td><td>NC</td><td>XMC_D7+</td><td>XMC_E7-</td><td>NC</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>9</td><td>XMC_A9+</td><td>XMC_B9-</td><td>NC</td><td>XMC_D9+</td><td>XMC_E9-</td><td>NC</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>11</td><td>XMC_A11+</td><td>XMC_B11-</td><td>NC</td><td>XMC_D11+</td><td>XMC_E11-</td><td>NC</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>XMC_C12</td><td>GND</td><td>GND</td><td>XMC_F12</td></tr><tr><td>13</td><td>XMC_A13+</td><td>XMC_B13-</td><td>XMC_C13</td><td>XMC_D13+</td><td>XMC_E13-</td><td>XMC_F13</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>XMC_C14</td><td>GND</td><td>GND</td><td>XMC_F14</td></tr><tr><td>15</td><td>XMC_A15+</td><td>XMC_B15-</td><td>XMC_C15</td><td>XMC_D15+</td><td>XMC_E15-</td><td>XMC_F15</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>XMC_C16</td><td>GND</td><td>GND</td><td>XMC_F16</td></tr><tr><td>17</td><td>XMC_A17+</td><td>XMC_B17-</td><td>XMC_C17</td><td>XMC_D17+</td><td>XMC_E17-</td><td>XMC_F17</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>XMC_C18</td><td>GND</td><td>GND</td><td>XMC_F18</td></tr><tr><td>19</td><td>XMC_A19+</td><td>XMC_B19-</td><td>XMC_C19</td><td>XMC_D19+</td><td>XMC_E19-</td><td>XMC_F19</td></tr></table>

M.2 Connector Pin Definition

<table><tr><td>Signal</td><td>Pin</td><td>Pin</td><td>Signal</td></tr><tr><td>GND</td><td>1</td><td>2</td><td>P_+3V3</td></tr><tr><td>GND</td><td>3</td><td>4</td><td>P_+3V3</td></tr><tr><td>PCH_PCIE20_RX_R_N</td><td>5</td><td>6</td><td>NC</td></tr><tr><td>PCH_PCIE20_RX_R_P</td><td>7</td><td>8</td><td>NC</td></tr><tr><td>GND</td><td>9</td><td>10</td><td>NC</td></tr><tr><td>PCH_PCIE20_TX_C_N</td><td>11</td><td>12</td><td>P_+3V3</td></tr><tr><td>PCH_PCIE20_TX_C_P</td><td>13</td><td>14</td><td>P_+3V3</td></tr><tr><td>GND</td><td>15</td><td>16</td><td>P_+3V3</td></tr><tr><td>PCH_PCIE19_RX_R_N</td><td>17</td><td>18</td><td>P_+3V3</td></tr><tr><td>PCH_PCIE19_RX_R_P</td><td>19</td><td>20</td><td>NC</td></tr><tr><td>GND</td><td>21</td><td>22</td><td>NC</td></tr><tr><td>PCH_PCIE19_TX_C_N</td><td>23</td><td>24</td><td>NC</td></tr><tr><td>PCH_PCIE19_TX_C_P</td><td>25</td><td>26</td><td>NC</td></tr><tr><td>GND</td><td>27</td><td>28</td><td>NC</td></tr><tr><td>PCH_PCIE18_RX_R_N</td><td>29</td><td>30</td><td>NC</td></tr><tr><td>PCH_PCIE18_RX_R_P</td><td>31</td><td>32</td><td>NC</td></tr><tr><td>GND</td><td>33</td><td>34</td><td>GND</td></tr><tr><td>PCH_PCIE18_TX_C_N</td><td>35</td><td>36</td><td>NC</td></tr><tr><td>PCH_PCIE18_TX_C_P</td><td>37</td><td>38</td><td>DEVSLP_M2_CON_R</td></tr><tr><td>GND</td><td>39</td><td>40</td><td>NC</td></tr><tr><td>PCH_PCIE17_SATA4_RX_R_P</td><td>41</td><td>42</td><td>NC</td></tr><tr><td>PCH_PCIE17_SATA4_RX_R_N</td><td>43</td><td>44</td><td>NC</td></tr><tr><td>GND</td><td>45</td><td>46</td><td>NC</td></tr><tr><td>PCH_PCIE17_SATA4_TX_C_N</td><td>47</td><td>48</td><td>NC</td></tr><tr><td>PCH_PCIE17_SATA4_TX_C_P</td><td>49</td><td>50</td><td>M2_RST-L</td></tr><tr><td>GND</td><td>51</td><td>52</td><td>CLK_REQ_M2_R-L</td></tr><tr><td>C_PCIECLK2_100M_N</td><td>53</td><td>54</td><td>NC</td></tr><tr><td>C_PCIECLK2_100M_P</td><td>55</td><td>56</td><td>NC</td></tr><tr><td>GND</td><td>57</td><td>58</td><td>NC</td></tr><tr><td colspan="4">Key</td></tr><tr><td>NC</td><td>67</td><td>68</td><td>NC</td></tr><tr><td>M2TYPE_PEDET</td><td>69</td><td>70</td><td>P3V3</td></tr><tr><td>GND</td><td>71</td><td>72</td><td>P3V3</td></tr><tr><td>GND</td><td>73</td><td>74</td><td>P3V3</td></tr><tr><td>GND</td><td>75</td><td>76</td><td>NA</td></tr></table>

# VPX Connectors

# P0 Connector

<table><tr><td>Row</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>+12V (VS1)</td><td>+12V (VS1)</td><td>+12V (VS1)</td><td>NC</td><td>NC (VS2)</td><td>NC (VS2)</td><td>NC (VS2)</td></tr><tr><td>2</td><td>+12V (VS1)</td><td>+12V (VS1)</td><td>+12V (VS1)</td><td>NC</td><td>NC (VS2)</td><td>NC (VS2)</td><td>NC (VS2)</td></tr><tr><td>3</td><td>NC (VS3)</td><td>NC (VS3)</td><td>NC (VS3)</td><td>NC</td><td>NC (VS3)</td><td>NC (VS3)</td><td>NC (VS3)</td></tr><tr><td>4</td><td>IPM1_CLK</td><td>IPM1_DAT</td><td>GND</td><td>NC(-12V_AUX)</td><td>GND</td><td>SYSRESET#</td><td>NVMRO</td></tr><tr><td>5</td><td>GAP#</td><td>GA4#</td><td>GND</td><td>+3.3V_AUX</td><td>GND</td><td>IPM2_CLK</td><td>IPM2_DAT</td></tr><tr><td>6</td><td>GA3#</td><td>GA2#</td><td>GND</td><td>NC(+12V_AUX)</td><td>GND</td><td>GA1#</td><td>GA0#</td></tr><tr><td>7</td><td>IPMB_JTCK</td><td>GND</td><td>IPMB_JTDO</td><td>IPMB_JTDI</td><td>GND</td><td>IPMB_JTMS</td><td>IPMB_JTRST-L</td></tr><tr><td>8</td><td>GND</td><td>REF_CLK-</td><td>REF_CLK+</td><td>GND</td><td>AUX_CLK-</td><td>AUX_CLK+</td><td>GND</td></tr></table>

P1 Connector

<table><tr><td>Row</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>GDiscrete1#</td><td>GND</td><td>PCIE1_TX0-</td><td>PCIE1_TX0+</td><td>GND</td><td>PCIE1_RX0-</td><td>PCIE1_RX0+</td></tr><tr><td>2</td><td>GND</td><td>PCIE1_TX1-</td><td>PCIE1_TX1+</td><td>GND</td><td>PCIE1_RX1-</td><td>PCIE1_RX1+</td><td>GND</td></tr><tr><td>3</td><td>P1_VBAT</td><td>GND</td><td>PCIE1_TX2-</td><td>PCIE1_TX2+</td><td>GND</td><td>PCIE1_RX2-</td><td>PCIE1_RX2+</td></tr><tr><td>4</td><td>GND</td><td>PCIE1_TX3-</td><td>PCIE1_TX3+</td><td>GND</td><td>PCIE1_RX3-</td><td>PCIE1_RX3+</td><td>GND</td></tr><tr><td>5</td><td>SYSCON#</td><td>GND</td><td>PCIE2_TX0-</td><td>PCIE2_TX0+</td><td>GND</td><td>PCIE2_RX0-</td><td>PCIE2_RX0+</td></tr><tr><td>6</td><td>GND</td><td>PCIE2_TX1-</td><td>PCIE2_TX1+</td><td>GND</td><td>PCIE2_RX1-</td><td>PCIE2_RX1+</td><td>GND</td></tr><tr><td>7</td><td>+5V_USB1(for USB3.0)</td><td>GND</td><td>PCIE2_TX2-</td><td>PCIE2_TX2+</td><td>GND</td><td>PCIE2_RX2-</td><td>PCIE2_RX2+</td></tr><tr><td>8</td><td>GND</td><td>PCIE2_TX3-</td><td>PCIE2_TX3+</td><td>GND</td><td>PCIE2_RX3-</td><td>PCIE2_RX3+</td><td>GND</td></tr><tr><td>9</td><td>COM1_TX</td><td>GND</td><td>J16-A5</td><td>J16-B5</td><td>GND</td><td>J16-D5</td><td>J16-E5</td></tr><tr><td>10</td><td>GND</td><td>J16-A7</td><td>J16-B7</td><td>GND</td><td>J16-D7</td><td>J16-E7</td><td>GND</td></tr><tr><td>11</td><td>COM1_RX</td><td>GND</td><td>J16-A9</td><td>J16-B9</td><td>GND</td><td>J16-D9</td><td>J16-E9</td></tr><tr><td>12</td><td>GND</td><td>J16-A15</td><td>J16-B15</td><td>GND</td><td>J16-D15</td><td>J16-E15</td><td>GND</td></tr><tr><td>13</td><td>GPIO1(DP_CONFIG)</td><td>GND</td><td>J16-A17</td><td>J16-B17</td><td>GND</td><td>J16-D17</td><td>J16-E17</td></tr><tr><td>14</td><td>GND</td><td>J16-A19</td><td>J16-B19</td><td>GND</td><td>J16-D19</td><td>J16-E19</td><td>GND</td></tr><tr><td>15</td><td>MASKABLE RESET#</td><td>GND</td><td>KR-TX0-</td><td>KR-TX0+</td><td>GND</td><td>KR-RX0-</td><td>KR-RX0+</td></tr><tr><td>16</td><td>GND</td><td>KR-TX1-</td><td>KR-TX1+</td><td>GND</td><td>KR-RX1-</td><td>KR-RX1+</td><td>GND</td></tr></table>

# Signal Types:

1. Data Plane: 1x PCIe x4 (PCIE1\_xx)
2. Expansion Plane: 1x PCIe x4 (PCIE2\_xx)
3. XMC X12d Mapping: (J16-xx)
4. Maintenance Port: (COM1\_xx)
5. 10GBASE-KR x2: (KR-xx)

P2 Connector

<table><tr><td>Row</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>SER_TX1-/DATA1-/TX1</td><td>GND</td><td>DP_L1-</td><td>DP_L1+</td><td>GND</td><td>DP_L0-</td><td>DP_L0+</td></tr><tr><td>2</td><td>GND</td><td>DP_L3-</td><td>DP_L3+</td><td>GND</td><td>DP_L2-</td><td>DP_L2+</td><td>GND</td></tr><tr><td>3</td><td>SER_TX1+/DATA1+/TX2</td><td>GND</td><td>DP_PWR</td><td>DP_HPD</td><td>GND</td><td>DP_AUX-</td><td>DP_AUX+</td></tr><tr><td>4</td><td>GND</td><td>USB2.0_2_D-</td><td>USB2.0_2_D+</td><td>GND</td><td>USB2.0_1_D-</td><td>USB2.0_1_D+</td><td>GND</td></tr><tr><td>5</td><td>SER_RX1-/RX1</td><td>GND</td><td>USB3_TX-</td><td>USB3_TX+</td><td>GND</td><td>USB3_RX-</td><td>USB3_RX+</td></tr><tr><td>6</td><td>GND</td><td>SATA3_TX-</td><td>SATA3_TX+</td><td>GND</td><td>SATA3_RX-</td><td>SATA3_RX+</td><td>GND</td></tr><tr><td>7</td><td>SER_RX1+/RX2</td><td>GND</td><td>TB-</td><td>TB+</td><td>GND</td><td>TA-</td><td>TA+</td></tr><tr><td>8</td><td>GND</td><td>TD-</td><td>TD+</td><td>GND</td><td>TC-</td><td>TC+</td><td>GND</td></tr><tr><td>9</td><td>+5V_USB2 (for USB2)</td><td>GND</td><td>J16-C12/PCIE3_TX0-</td><td>J16-C13/PCIE3_TX0+</td><td>GND</td><td>J16-F12/PCIE3_RX0-</td><td>J16-F13/PCIE3_RX0+</td></tr><tr><td>10</td><td>GND</td><td>J16-C14/PCIE3_TX1-</td><td>J16-C15/PCIE3_TX1+</td><td>GND</td><td>J16-F14/PCIE3_RX1-</td><td>J16-F15/PCIE3_RX1+</td><td>GND</td></tr><tr><td>11</td><td>GPIO2</td><td>GND</td><td>J16-C16/PCIE3_TX2-</td><td>J16-C17/PCIE3_TX2+</td><td>GND</td><td>J16-F16/PCIE3_RX2-</td><td>J16-F17/PCIE3_RX2+</td></tr><tr><td>12</td><td>GND</td><td>J16-C18/PCIE3_TX3-</td><td>J16-C19/PCIE3_TX3+</td><td>GND</td><td>J16-F18/PCIE3_RX3-</td><td>J16-F19/PCIE3_RX3+</td><td>GND</td></tr><tr><td>13</td><td>GPIO3</td><td>GND</td><td>J16-A1/PCIE4_TX0-</td><td>J16-B1/PCIE4_TX0+</td><td>GND</td><td>J16-D1/PCIE4_RX0-</td><td>J16-E1/PCIE4_RX0+</td></tr><tr><td>14</td><td>GND</td><td>J16-A3/PCIE4_TX1-</td><td>J16-B3/PCIE4_TX1+</td><td>GND</td><td>J16-D3/PCIE4_RX1-</td><td>J16-E3/PCIE4_RX1+</td><td>GND</td></tr><tr><td>15</td><td>GPIO4</td><td>GND</td><td>J16-A11/PCIE4_TX2-</td><td>J16-B11/PCIE4_TX2+</td><td>GND</td><td>J16-D11/PCIE4_RX2-</td><td>J16-E11/PCIE4_RX2+</td></tr><tr><td>16</td><td>GND</td><td>J16-A13/PCIE4_TX3-</td><td>J16-B13/PCIE4_TX3+</td><td>GND</td><td>J16-D13/PCIE4_RX3-</td><td>J16-E13/PCIE4_RX3+</td><td>GND</td></tr></table>

# Signal Types:

1. 1x Display Port: DP\_xx

2. 1x USB 3.2 Gen1: (USB3\_xx)

3. 2x USB 2.0: (USB2.0\_1\_xx, USB2.0\_2\_xx)

4. 1x SATA 6Gb/s: (SATA3\_xx)

5. 1x 2.5GBASE-T: (TA/TB/TC/TD +/-)

6. XMC X16s Mapping: co-layout with 1x PCIe x4 or 2x PCIe x2 or 4x PCIe x1 (J16-Fxx, J16-Cxx, PCIE3\_xx)

7. XMC X8d Mapping: co-layout with 1x PCIe x4 or 2x PCIe x2 or 4x PCIe x1 (J16-Axx, J16-Bxx, J16-Dxx, J16-Exx, PCIE4\_xx)

# 4.4 Status LEDs

![Power-up Button\nIPMC WDT LED\nReset Button\nSATA LED\nEC Status LED\nPower LED\nCOM1 LVCOMS/RS232 Status](.vpx3-tl-50m-31129-1010/f65359435fe374b5014ddea1d11fa8424f524e999c1c993aa4dbf12073f8b917.jpg)

Figure 4-4: VPX3-TL Front View

# Reset Button

Press this button to perform a hard system reset.

# Power-up Button

Press this button to power-up in ATX mode.

LEDs

<table><tr><td>Description</td><td>Indication</td></tr><tr><td>Power LED</td><td>Green: On when blade is receiving power</td></tr><tr><td>SATA LED</td><td>Yellow: Blinks when SATA is active</td></tr><tr><td>IPMC WDT LED</td><td>TBD</td></tr><tr><td>Embedded Controller (EC) Status LED</td><td>Red (error codes TBD)</td></tr><tr><td>COM1 LVCOMS/RS232 Status LED</td><td>On: RS232 modeOff: LVCOMS mode</td></tr></table>

# 5 VPX3-TL-RL1 RTM

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the VPX3-TL-RL1 RTM.

5.1 Connector Allocation

<table><tr><td>Function</td><td>Rear</td><td>Top</td><td>RPx</td><td>Connector Type</td></tr><tr><td>DisplayPort</td><td>1</td><td>—</td><td>RP1</td><td>4 lanes DDI to Mini DisplayPort</td></tr><tr><td>2.5GBASE-T MDI</td><td>1</td><td>—</td><td>RP1</td><td>4 lanes MDI to RJ45 port</td></tr><tr><td>USB 3.0/2.0</td><td>1</td><td>—</td><td>RP1</td><td>USB 2.0 + USB 3.0 combo port</td></tr><tr><td>USB 2.0</td><td>1</td><td>—</td><td>RP1</td><td>USB2.0 port</td></tr><tr><td>Maintenance Port</td><td>1</td><td>—</td><td>RP1</td><td>RJ45</td></tr><tr><td>SATA Gen3</td><td>—</td><td>1</td><td>RP1</td><td>7 Pin SATA connector</td></tr><tr><td>COM Port</td><td>—</td><td>1</td><td>RP1</td><td>Box 2x5 pin header</td></tr><tr><td>IPMB JTAG</td><td>—</td><td>1</td><td>RP0</td><td>2x5 pin header</td></tr><tr><td>IPMB SMBus</td><td>—</td><td>1</td><td>RP0</td><td>Wafer ML 1*5P ST D1.25</td></tr><tr><td>VPX MB RTC Power Source</td><td>—</td><td>1</td><td>RP0</td><td>Wafer ML 1x2P RT D1.25</td></tr><tr><td>IPMB SMBus Switch</td><td>—</td><td>1</td><td>RP0</td><td>SW DIP SPST 4-POS ST</td></tr><tr><td>VPX Utility Test Jumper</td><td>—</td><td>1</td><td>RP0</td><td>2x3 pin header</td></tr><tr><td>VPX GPIO Test Jumper</td><td>—</td><td>1</td><td>RP1/RP2</td><td>2x5 pin header</td></tr><tr><td>2x 10GBASE-KR</td><td rowspan="4">—</td><td rowspan="4">1</td><td>RP1</td><td rowspan="4">Board to Board Connector</td></tr><tr><td>XMC X12d</td><td>RP1</td></tr><tr><td>XMC X8d</td><td>RP2</td></tr><tr><td>XMC X16s</td><td>RP2</td></tr></table>

# 5.2 VPX3-TL-RL1 Block Diagram

![The flowchart features three primary vertical blocks labeled **RP0**, **RP1**, and **RP2**, along with input blocks and destination blocks.\n\n**RP0 Block**\n*   **Input:** A blue box labeled **VBAT** connects to the bottom-left dot of the RP0 block.\n*   **Connections:** Six lines extend from the top dots of RP0 to text labels on the right:\n    *   **Vs1 (12V), 8A**\n    *   **Vs2 (3.3V), 8A**\n    *   **Vs3 (5V), 8=16A**\n    *   **SM (0:1) IPM2, SM (2:3) I2C**\n    *   **NVMRO, SYSRESET#**\n    *   **JTAG**\n\n**RP1 Block**\n*   **Input:** A blue box labeled **Mask Reset** connects to a dot on the left side of the RP1 block.\n*   **Connections:** Double-headed arrows connect the right side of RP1 to the following destination blocks:\n    *   **COM (2x RS232 or 1x RS422 or 1x RS485)** connects to **COM Port**.\n    *   **1x DDI (1.4)** connects to **DP Port**.\n    *   **1x USB 2.0** connects to **USB 2.0 Port**.\n    *   **1x USB 3.0 / 2.0 Combo** connects to **USB 3.0 Port**.\n    *   **1x SATA (Gen 3)** connects to **SATA Port**.\n    *   **2.5GBASE-T MDI** connects to **RJ45 Port**.\n    *   **2x 10GBASE-KR** connects to the top section of a large blue box labeled **Board to Board**.\n    *   **XMC X12d** connects to the middle section of the **Board to Board** box.\n\n**RP2 Block**\n*   **Connections:** Double-headed arrows connect the right side of RP2 to the bottom section of the **Board to Board** box:\n    *   **XMC X12d**\n    *   **XMC X12d**](.vpx3-tl-50m-31129-1010/a447aeb7c9239526e6bed32b3dbe9cb4b1aac5e4000550fdc5f3a27d73b7d199.jpg)

Figure 5-1: VPX3-TL-RL1 RTM Functional Block Diagram

# 5.3 VPX3-TL-RL1 RTM Board Layout

![A\nB\nC\nD\nE\nJ\nK\nL\nM\nN\nQ\nElectrons\nP\nO\nF\nG\nH\nI](.vpx3-tl-50m-31129-1010/399945c4a2a49b4f8fe5adafe0c21a0e0a8783421cbf981d31133f2a6ae04f35.jpg)

Figure 5-2: VPX3-TL-RL1 RTM Board Layout

<table><tr><td>A</td><td>LAN Port</td><td>J</td><td>COM Port</td></tr><tr><td>B</td><td>USB 2.0 Port</td><td>K</td><td>VPX GPIO Test Jumper</td></tr><tr><td>C</td><td>USB 3.0 + USB 2.0 Combo Port</td><td>L</td><td>SATA Port</td></tr><tr><td>D</td><td>Mini DP Port</td><td>M</td><td>IPMB SMBus Switch</td></tr><tr><td>E</td><td>Maintenance Port (MGMT)</td><td>N</td><td>RTM L2 B2B Connector(reserved)</td></tr><tr><td>F</td><td>VPX Utility Test Jumper</td><td>O</td><td>VPX RP0 Connector</td></tr><tr><td>G</td><td>VPX MB RTC Power Source</td><td>P</td><td>VPX RP1 Connector</td></tr><tr><td>H</td><td>IPMB SMBus</td><td>Q</td><td>VPX RP2 Connector</td></tr><tr><td>I</td><td>IPMB JTAG</td><td></td><td></td></tr></table>

Table 5-1: VPX3-TL-RL1 RTM Board Layout Legend

# 5.4 VPX3-TL-RL1 RTM Connector Pin Assignments

# Rear I/O Connectors

Mini DisplayPort Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>1</td><td>GND</td><td>11</td><td>DP1_TXN1_CN</td></tr><tr><td>2</td><td>DP_CN_HPD</td><td>12</td><td>DP1_TXN3_CN</td></tr><tr><td>3</td><td>DP1_TXP0_CN</td><td>13</td><td>GND</td></tr><tr><td>4</td><td>DP1_CFG1_CN</td><td>14</td><td>GND</td></tr><tr><td>5</td><td>DP1_TXN0_CN</td><td>15</td><td>DP1_TXP2_CN</td></tr><tr><td>6</td><td>DP1_CFG2_CN</td><td>16</td><td>DP_AUX_C_P</td></tr><tr><td>7</td><td>GND</td><td>17</td><td>DP1_TXN2_CN</td></tr><tr><td>8</td><td>GND</td><td>18</td><td>DP_AUX_C_N</td></tr><tr><td>9</td><td>DP1_TXP1_CN</td><td>19</td><td>GND</td></tr><tr><td>10</td><td>DP1_TXP3_CN</td><td>20</td><td>P_+3V3_DP1_CN</td></tr></table>

![19\n1\n20\n2](.vpx3-tl-50m-31129-1010/413f7d6138d1b6a5256b9b65c11e7d89619554792de081393b7ee133c9bfbe66.jpg)

USB 3.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>USB3.0_P5VA</td></tr><tr><td>2</td><td>USB2_CMAN</td></tr><tr><td>3</td><td>USB2_CMAP</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_CMRXN</td></tr><tr><td>6</td><td>USB3A_CMRXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_CMTXN</td></tr><tr><td>9</td><td>USB3A_CMTXP</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.vpx3-tl-50m-31129-1010/562fc444dba9e6ca345573418eb05ba3d8131eb1d504f602d0ac20422879cd65.jpg)

# USB 2.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>Vcc</td></tr><tr><td>2</td><td>UV0-</td></tr><tr><td>3</td><td>UV0+</td></tr><tr><td>4</td><td>GND</td></tr></table>

![4\n3\n2\n1](.vpx3-tl-50m-31129-1010/57c71e2ca0d635f79020488568a7763ea456fd9efbe266c619582c4af6448927.jpg)

# Serial Port (RJ-45)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>NC</td></tr><tr><td>2</td><td>NC</td></tr><tr><td>3</td><td>MTN_TXD</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>GND</td></tr><tr><td>6</td><td>MTN_RXD</td></tr><tr><td>7</td><td>NC</td></tr><tr><td>8</td><td>NC</td></tr></table>

![A black and white line drawing depicts a square outline containing a shape resembling a camera or lens. Below the square are the numbers '8' and '1'. Thin black lines connect the number '8' to the bottom-left corner of the inner shape and the number '1' to the bottom-right corner of the inner shape.](.vpx3-tl-50m-31129-1010/9c3a05f7fe6d909b8fe81f2c6daaa1663d10c5f28a50d50f2258c029474dedfa.jpg)

# System LAN Port (RJ-45)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>MDIA_P</td></tr><tr><td>2</td><td>MDIA_N</td></tr><tr><td>3</td><td>MDIB_P</td></tr><tr><td>4</td><td>MDIC_P</td></tr><tr><td>5</td><td>MDIC_N</td></tr><tr><td>6</td><td>MDIB_N</td></tr><tr><td>7</td><td>MDID_P</td></tr><tr><td>8</td><td>MDID_N</td></tr></table>

![The image displays a line drawing of a square outline. Inside the square is a gray shape resembling a camera or sensor, featuring a rectangular base with a smaller, centered rectangular section on top. At the bottom, the number '8' is on the left and the number '1' is on the right. Thin black lines connect the number '8' to the bottom-left corner of the inner gray shape and the number '1' to the bottom-right corner.](.vpx3-tl-50m-31129-1010/d68274bcd3b2781982d287a4b4a01e6e2137b437a4b6223297868f5ae4e46bc6.jpg)

# Onboard Connectors

COM Port (COM1)

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>NC</td><td>2</td><td>NC</td></tr><tr><td>3</td><td>COM1_RX_RX-</td><td>4</td><td>COM2_TX_TX+</td></tr><tr><td>5</td><td>COM1_TX_TX-</td><td>6</td><td>COM2_RX_RX+</td></tr><tr><td>7</td><td>NC</td><td>8</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>10</td><td>NC</td></tr></table>

![1\n2\n9\n10](.vpx3-tl-50m-31129-1010/aa66a6fab9cc8075e3263a213918c10b0a58a4827ba58aa2c0a403bb76c1b813.jpg)

JTAG Header

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TCK</td></tr><tr><td>3</td><td>NC</td></tr><tr><td>4</td><td>TDO</td></tr><tr><td>5</td><td>+3.3V</td></tr><tr><td>6</td><td>TMS</td></tr><tr><td>7</td><td>TRST</td></tr><tr><td>8</td><td>+3.3V</td></tr><tr><td>9</td><td>GND</td></tr><tr><td>10</td><td>TDI</td></tr></table>

![2\n1](.vpx3-tl-50m-31129-1010/dd65ed88a20e23c60beb1ba41e674a2bf53b7df7107d0d155e3cc068df308a0c.jpg)

SATA Connectors

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TXP</td></tr><tr><td>3</td><td>TXN</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RXN</td></tr><tr><td>6</td><td>RXP</td></tr><tr><td>7</td><td>GND</td></tr></table>

![1\n2\n3\n4\n5\n6\n7](.vpx3-tl-50m-31129-1010/637c7bdd5dd9d82cf225c71c81c81e988e04863040dc28ac21839cbfe11baa76.jpg)

IPMB Connector

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>IPMB_SDA</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>IPMB_SCL</td></tr><tr><td>4</td><td>+5V</td></tr><tr><td>5</td><td>+5V</td></tr></table>

![5\n4\n3\n2\n1](.vpx3-tl-50m-31129-1010/1aba41436606588fca0e9b7a199da587417766c62903c4271207e0a8068ba67f.jpg)

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# 6 Getting Started

This chapter describes the installation of the following components to the VPX3-TL and rear transition modules:

▶ VPX Blade installation to chassis

▶ RTM installation to chassis

# 6.1 Installing the VPX3-TL to the Chassis

These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the system slot to install the blade. The system power may be powered either on or off.

2. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If a strong resistance is felt, check if the wedge locks are expanded or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.

3. Ensure the module in place, and then screw the wedge lock on the module

# 6.2 Installing the VPX3-TL-RL1 RTM to the Chassis

The installation and removal procedures for a RTM are the same as those for VPX boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the VPX3-TL Series and related RTMs, make sure the RTM is the correct matching model.

# 6.3 Driver Installation

The VPX3-TL drivers are available from the ADLINK website at www.adlinktech.com/Products/VPX/VPX3UProcessorBlades/VPX3-TL. ADLINK provides validated drivers for Windows 10 IoT Enterprise LTSC 21H2. We recommend using the drivers provided on the ADLINK website to ensure compatibility.

Follow the steps below to install the drivers for Windows 10.

1. Install the Windows operating system before installing any driver. Most standard I/O device drivers are installed during Windows installation.
2. Install the chipset driver by extracting and running the application "SetupChipset.exe" in the Intel® Chipset Device Software directory.
3. Install the graphics driver by extracting and running the application "Installer.exe" in the Intel® UHD Graphics directory.
4. Install the management engine driver by extracting and running the application "SetupME.exe" in the Intel® Management Engine Components/SW/ME\_SW\_DCH directory.
5. Install the GPIO/Serial I/O driver by extracting and running the application "SetupSerialIO.exe" in the Intel® SerialIO directory.

6. Install the Intel Trace Hub driver by extracting the contents of the Intel Trace Hub directory, and perform the following steps:

a. In the Device Manager, right-click on "Unknown device" and click on "Update driver".

![Device Manager\nFile Action View Help\nDESKTOP-A71KDT8\nAudio inputs and outputs\nBatteries\nComputer\nDisk drives\nDisplay adapters\nFirmware\nHuman Interface Devices\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nNetwork adapters\nOther devices\nEthernet Controller\nEthernet Controller\nEthernet Controller\nUnknown device*\nPorts (COM & LPT)\nPrint queues\nProcessors\nSecurity devices\nSoftware compone\nSoftware devices\nSound, video and g\nStorage controllers\nSystem devices\nUniversal Serial Bus controllers\nUpdate driver\nDisable device\nUninstall device\nScan for hardware changes\nProperties](.vpx3-tl-50m-31129-1010/742698d28bcb31738d715860521fa0b0b13fe289ec58282f854cde238f824ed0.jpg)

b. Click on "Browse my computer for driver software".

← Update Drivers - Unknown Device

How do you want to search for drivers?

→ Search automatically for updated driver software
Windows will search your computer and the Internet for the latest driver software for your device, unless you've disabled this feature in your device installation settings.
→ Browse my computer for driver software
Locate and install driver software manually.

Cancel

c. Navigate to the "Intel Trace Hub" directory, click "OK" to search/install the driver. Click "Close" when done.

×

← Update Drivers - Intel(R) Trace Hub Device

Windows has successfully updated your drivers

Windows has finished installing the drivers for this device:

![The image displays a low-resolution icon of a computer setup. On the left stands a grey vertical computer tower. To its right is a computer monitor with a bright blue screen and a light grey bezel, angled slightly towards the tower.](.vpx3-tl-50m-31129-1010/e54706ee9dced246845cbc8aae359ec6e8a21cc5b751bab9dd624a1b5b0935ab.jpg)

Intel(R) Trace Hub Device

Close

7. Install the Intel Network drivers by extracting the contents of the Intel network connections directory, and performing the following steps.

a. In the Device Manager, right-click on "Unknown device" and click on "Update driver".

![Device Manager\nFile Action View Help\nDESKTOP-A71KDT8\nAudio inputs and outputs\nBatteries\nComputer\nDisk drives\nDisplay adapters\nFirmware\nHuman Interface Devices\nIDE ATA/ATAPI controllers\nKeyboards\nMice and other pointing devices\nMonitors\nNetwork adapters\nOther devices\nEthernet Controller\nEthernet Controller\nEthernet Controller](.vpx3-tl-50m-31129-1010/6ac41cc8d26afea6cc940290190cc3547eed8f4dce11e827f0d87abd8925b94e.jpg)

# b. Click on "Browse my computer for driver software".

×

![Three identical grey upward-pointing arrows arranged horizontally against a white background.](.vpx3-tl-50m-31129-1010/8ad7540b93ea17c3320003a04fca016fba924228ecba42af7c57a086cf692f0c.jpg)

Update Drivers - Unknown Device

How do you want to search for drivers?

→ Search automatically for updated driver software

Windows will search your computer and the Internet for the latest driver software for your device, unless you've disabled this feature in your device installation settings.

→ Browse my computer for driver software

Locate and install driver software manually.

Cancel

# c. Navigate to the "Intel Trace Hub" directory, click "OK" to search/install the driver. Click "Close" when done. Repeat for the other two "Ethernet Controller" under "Other devices"

![Device Manager\nFile	Action	View	Help\nDESKTOP-A7IKDT8\n)Audio inputs and outputs\n)Batteries\n)Computer\n)Disk drives\n)Display adapters\n)Firmware\n)Human Interface Devices\n)IDE ATA/ATAPI controllers\n)Keyboards\n)Mice and other pointing devices\n)Monitors\n)Network adapters\nIntel(R) Ethernet Controller (3) I225-IT\nIntel(R) Ethernet Controller X710 for 10GbE backplane\nIntel(R) Ethernet Controller X710 for 10GbE backplane #2\nWAN Miniport (IKEv2)\nWAN Miniport (IP)\nWAN Miniport (IPv6)\nWAN Miniport (L2TP)\nWAN Miniport (Network Monitor)\nWAN Miniport (PPPOE)\nWAN Miniport (PPTP)\nWAN Miniport (SSTP)\nPortable Devices\nPorts (COM & LPT)\nPrint queues\n)Processors\n)Security devices\n)Software components\n)Software devices\n)Sound, video and game controllers\n)Storage controllers\n)System devices\n)Universal Serial Bus controllers](.vpx3-tl-50m-31129-1010/38a25f2cf883947ea4e9e83e4df65ce2bab5acbabaa814b4f4516f17c1347d1f.jpg)

d. The drivers for Intel Ethernet Controllers i225-IT and X710 are now successfully installed.

# 7 Utilities

# 7.1 SEMA

Hardware monitoring and Watchdog Timer functionality are provided by ADLINK's Smart Embedded Management Agent (SEMA), which operates via a Board Management Controller and communicates with the CPU through the SMBus. A graphical user interface program and command line interface are available to allow you to communicate with SEMA. Please refer to the SEMA user's manual, available the SEMA GitHub page:

https://adlinktech.github.io/sema/index.html

# 7.2 Watchdog Timer

The VPX3-TL's watchdog timer (WDT) is implemented by SEMA. For detailed information on how to program the WDT, refer to the SEMA user's manual WDT section on the SEMA GitHub page: https://adlinktech.github.io/sema/WatchDog.html#sysfs-In

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# 8 BIOS Setup

The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt:
&lt;Press DEL to run Setup&gt;
3. After you press the &lt;Delete&gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu.

![The image displays a white document icon with a folded top-right corner and faint gray horizontal lines running across it. A large, bold red checkmark is superimposed over the center of the document.](.vpx3-tl-50m-31129-1010/ed5825ce9b3b2e310cd3539014c84e4b08285d5dbe189da71d7ce662ec949dc2.jpg)
NOTE:

In most cases, the &lt;Delete&gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt;F1&gt;, &lt;F2&gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user's guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. "Grayed" options cannot be configured, "Blue" options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

![The flowchart begins with a top block labeled 'BIOS Setup Utility'. A downward arrow points to the text 'Screens'.\n\nTo the left of the screen row is a block labeled 'Left and Right Keys to Select a Setup Screen', which connects via a dotted arrow to the row of screens. This row consists of five blocks labeled 'Screen 1', 'Screen 2', 'Screen 3', 'Screen 4', and 'Screen 5', all connected horizontally by double-headed arrows.\n\nBelow 'Screens', a downward arrow points to the text 'Items'.\n\nBelow the 'Items' label is a row of three boxes containing a '±' symbol, connected by double-headed horizontal arrows.\n- To the left, a block labeled 'Tab Key to Select Fields' connects via a dotted arrow to the first item box.\n- To the right, a block labeled '± To Change Field Values' connects via a dotted line to the third item box.\n\nBelow the 'Items' row, there are vertical downward and upward arrows.\n- To the right of these arrows, a block labeled 'Up and Down Keys to Select a Setup Item' connects via a dotted arrow.\n- To the left, the text 'Fields' is connected via a bracket to a bottom row of three boxes containing the '±' symbol. These bottom boxes are connected horizontally by double-headed arrows.](.vpx3-tl-50m-31129-1010/ab49106df03872d6148c46bb252ac2729e63a1c389fa6a61e985d2b1c84ef228.jpg)

![The image displays a white document icon with a folded upper right corner and faint horizontal lines. A large red checkmark is superimposed over the center of the document.](.vpx3-tl-50m-31129-1010/321fb1628f1cd6a01c7a6c85d6686f97ecaa2992a0888369f77883022b7ea700.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

![The image displays a black and white graphic consisting of a horizontal line with two arrowheads in the center pointing towards each other. Specifically, there is a horizontal line segment on the left, followed by a right-pointing arrowhead, immediately followed by a left-pointing arrowhead, and then a horizontal line segment on the right. The arrowheads touch at their tips in the middle.](.vpx3-tl-50m-31129-1010/48b245933db7ea82f46c557eb66881c7c182b8045e5af222fa0898077d27eb29.jpg)

Left/Right. The Left and Right &lt; Arrow &gt; keys allow you to select a setup screen. For example: Main screen, Advanced screen, Chipset screen, and so on.

![The image displays two black arrows on a white background. On the left, an arrow points vertically upwards. On the right, an arrow points vertically downwards.](.vpx3-tl-50m-31129-1010/4b09acc45aa55ff5e341e8b9970a4c68320a9950908f5e5543a8892ed360f56f.jpg)

Up/Down The Up and Down &lt;Arrow&gt; keys allow you to select a setup item or sub-screen.

![The image displays a black plus sign (+) followed immediately by a black minus sign (-) on a white background.\n\n+-](.vpx3-tl-50m-31129-1010/c26d721839617807a74d6bf662193c99bf28e0844cebd3da344d58766c5845b4.jpg)

Plus/Minus The Plus and Minus &lt;Arrow&gt; keys allow you to change the field value of a particular setup item. For example: Date and Time.

![The image shows a black horizontal bar at the top. Below it, on a white background, is the word 'Tab' in black, bold, sans-serif text.](.vpx3-tl-50m-31129-1010/2288acd650c50840d268e58f92c12138da68f2f28bdc1bcb968b84230495acf5.jpg)

The &lt; Tab &gt; key allows you to select setup fields.

![The image displays the uppercase text 'ESC' in a bold, black, sans-serif typeface set against a plain white background.](.vpx3-tl-50m-31129-1010/c24edffe65df52ee79a2ee441b6138383ce99013f7f47ff3b5824a5d5de702aa.jpg)

The &lt;Esc&gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt;Esc&gt; key to exit the setup without saving your changes. Press the &lt;Enter&gt; key to discard changes and exit. You can also use the &lt;Arrow&gt; key to select Cancel and then press the &lt;Enter&gt; key to abort this function and return to the previous screen.

# 8.2 Setup Menus

Refer to the document VPX3-TL BIOS User's Manual for detailed BIOS setup menu information, available for download from the ADLINK website at www.adlinktech.com/Products/VPX/VPX3U ProcessorBlades/VPX3-TL.

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# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

▶ Read these safety instructions carefully.
- Keep this user’s manual for future reference.
▶ Read the specifications section of this manual for detailed information on the operating environment of this equipment.
▶ When installing/mounting or uninstalling/removing equipment:

▷ Turn off power and unplug any power cords/cables.

▶ To avoid electrical shock and/or damage to equipment:

▷ Keep equipment away from water or liquid sources;
▷ Keep equipment away from high heat or high humidity;
▷ Keep equipment properly ventilated (do not block or cover ventilation openings);

▶ Make sure to use recommended voltage and power source settings;

▶ Always install and operate equipment near an easily accessible electrical socket-outlet;

▷ Secure the power cord (do not place any object on/over the power cord);

▶ Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

▷ If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

▶ Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a standard warning symbol. At the top, there is a red equilateral triangle containing a white exclamation point in its center. Below the triangle, the word 'WARNING' is printed in black, uppercase letters.](.vpx3-tl-50m-31129-1010/edef7aa1c3c05bd6fe791e7d44167803f60c50d01ab2ccf6ff7aa540a0ef4170.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

▶ Equipment must be serviced by authorized technicians when:

▷ The power cord or plug is damaged;
▷ Liquid has penetrated the equipment;
▷ It has been exposed to high humidity/moisture;
$\triangleright$ It is not functioning or does not function according to the user's manual;
▷ It has been dropped and/or damaged; and/or,
▷ It has an obvious sign of breakage.

# Getting Service

Ask an Expert: https://www.adlinktech.com/en/Askanexpert.aspx

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan Dist.,

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.vpx3-tl-50m-31129-1010/vpx3-tl-50m-31129-1010.pdf)