# VPX3-XMXM Series # User’s Manual 3U VPX GPGPU Blade with NVIDIA® RTX™ ADA5000/ADA2000 ![Close-up of an electronic circuit board with integrated circuits and connectors (no visible text or symbols)](.vpx3-xmxm-50m-32214-1000-10/1a51a637c819a1aa52b66988dedc384818e0c6fb8174a51e3d4638932e8f4ea8.jpg) Manual Rev.: Rev. 1.0 Revision Date: January 9, 2026 Part Number: 50M-32214-1000 # Revision History

Revision	Description	Date	By
1.0	Initial release	2026-01-09	AL

# Preface # Copyright Copyright 2026 ADLINK Technology, Inc. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. # Disclaimer The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. # Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company. ![Symbol of a trash bin crossed with no text or labels, accompanied by a solid black rectangle below (no text or symbols present)](.vpx3-xmxm-50m-32214-1000-10/92261a978e27ddd212e01e4a0aad81b81b79c05afa0a84d86b79da4bce0348f8.jpg) Battery Labels (for products with battery) ![Simple line drawing of a trash bin with two crossed lines indicating no waste or prohibition (no text or symbols)](.vpx3-xmxm-50m-32214-1000-10/fe7fe1fad873eb29bf3743ca4351d80b3c1dbd90526516c12a8bad6b14e1733a.jpg) ![Li-ion](.vpx3-xmxm-50m-32214-1000-10/4101c06c835f7c01888de9cdf35f5b429e8586a4090b09f6e0bb093cd1d09b8b.jpg) ![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.vpx3-xmxm-50m-32214-1000-10/12931c9089006c7fcb10bab1cf7664eec8767fe3994114da32ed91c84043e3a8.jpg) ![廢電池請回收](.vpx3-xmxm-50m-32214-1000-10/cf4370af96d8885dcc0efe7c70628742543e67ff5428183caf25cdfe7cff21a4.jpg) # California Proposition 65 Warning ![The image displays a standard warning symbol: a yellow equilateral triangle with a thick black border containing a black exclamation point in the center.](.vpx3-xmxm-50m-32214-1000-10/312b55e1ea6c7eb59e6b70401fcccec075fe342ffb836c662be946c5dc98d391.jpg) WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov. # Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies. # Conventions Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly. ![The image displays a digital icon representing a document or file. It features a white rectangular page with the top-right corner folded over (a 'dog-ear'). Faint horizontal gray lines run across the page, simulating text. Superimposed on top of the document is a large, bold, red checkmark. The entire graphic is enclosed within a black border.](.vpx3-xmxm-50m-32214-1000-10/c4df150eb313f1f307b422acbab15c5acf910395258af27a02bac77bb14e8954.jpg) NOTE: Additional information, aids, and tips that help users perform tasks. ![The image shows a yellow triangular warning sign with a thick black border. Inside the triangle is a large black exclamation mark.](.vpx3-xmxm-50m-32214-1000-10/ad45b3265b8952f0120b7fdbbff6d35dc8a6973ca23010486bca3cf937a130c3.jpg) CAUTION: Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task. ![The image shows a red triangular warning sign containing a white exclamation mark in the center.](.vpx3-xmxm-50m-32214-1000-10/65b7a6f66ac69f2c3d4588890d9ec79b5b8306fe50e1b30f386e7bebc702bd62.jpg) WARNING: Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task. # Table of Contents Preface... List of Figures .... ..vi List of Tables...... ..vi 1 Introduction.... 1.1 Overview.. 1.2 Features.. .7 1.3 VPX-XMXM SKUs.. 7 1.4 Package Contents.. .8 2 Specifications .... 2.1 Product Specifications.. .9 2.2 Functional Descriptions... ..10 3 Block Diagram .. .11 4 Mechanical Layout .. .13 4.1 Mechanical Dimensions . ..13 Connectors, Switch Locations, and LEDs Status... ..14 5 Connector Pinouts .. .17 5.1 VPX Connectors .... .17 6 Driver Installation .... .21 Safety Instructions......... .22 Getting Services.......... .23 # List of Figures Figure 1: Functional block diagram. .11 Figure 2: Mechanical dimensions .. .13 Figure 3: Top side board layout (carrier only) . ..14 Figure 4: Bottom side board layout (carrier only) .. ..15 Figure 5: LED locations . ..16 # List of Tables Table 1: Top side board layout labels (carrier only).. ..14 Table 2: Bottom side board layout labels (carrier only).. .15 Table 3: LED status .. ..16 # 1 Introduction # Overview The VPX3-XMXM/ADA2000 or ADA5000 is a 3U VPX general-purpose GPU (GPGPU) blade based on the NVIDIA ADA2000 or ADA5000, supporting 16 GB of GDDR6 graphics memory with four DisplayPort or four HDMI outputs. The VPX3-XMXM/ADA2000 or ADA5000 delivers a new level of performance for visual graphics and computing applications, fully integrating hardware acceleration for both graphics and compute workloads, enabling hardware acceleration for a wider range of applications than ever before. The VPX3-XMXM/ADA2000 or ADA5000 features rugged, conduction-cooled construction with conformal coating, making it ideal for mission-critical applications requiring artificial intelligence and machine learning (AI/ML), parallel computing, and SWaP optimization. Typical use cases include radar processing, target tracking, software-defined radio (SDR), intelligence, surveillance and reconnaissance (ISR), degraded visual environments (DVE), digital signal processing (DSP), electronic warfare (EW), and signals intelligence (SIGINT). The VPX3-XMXM/ADA2000 or ADA5000 is also SOSA-aligned, with SOSA being one of several standards that fall broadly within the Modular Open Systems Approach (MOSA) initiative. SOSA focuses on key interfaces and open standards, based on the VPX standard (VITA 46/48/65), and aims to develop a common, modular hardware architecture for next-generation mission-critical applications. # Features • NVIDIA® RTX ADA5000 or ADA2000 embedded graphics based on Ada Lovelace architecture • Up to 9728 CUDA cores, 42.6 TFLOPS peak FP32 performance (RTX ADA5000 SKU) • Native PCIe Gen4 interface • PCIe lanes configurable by PCIe switch 1x DisplayPort 1.4a (SKU option) • Additional ports from SBC for expansion (SKU option): 2x USB3.2 Gen1x1, 1x USB2.0, and 1x RS-232 • VITA 46/48/65 compliant for quick deployment • SOSA-aligned # VPX-XMXM SKUs With P2 Connector (P0+P1+P2)

SKU	Description
VPX3-XMXM/AD5000, COMM	3U VPX GPGPU blade with MXM RTX 5000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, 1x DP, 2x USB3.0, 1x USB2.0, and 1x RS-232, supports common PCIe clock mode
VPX3-XMXM/AD5000, non-COMM	3U VPX GPGPU blade with MXM RTX 5000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, 1x DP, 2x USB3.0, 1x USB2.0, and 1x RS-232, supports non-common PCIe clock mode
VPX3-XMXM/AD2000, COMM	3U VPX GPGPU blade with MXM RTX 2000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, 1x DP, 2x USB3.0, 1x USB2.0, and 1x RS-232, supports common PCIe clock mode
VPX3-XMXM/AD2000, non-COMM	3U VPX GPGPU blade with MXM RTX 2000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, 1x DP, 2x USB3.0, 1x USB2.0, and 1x RS-232, supports non-common PCIe clock mode

Without P2B Connector (P0+P1+P2A)

SKU	Description
VPX3-XMXM/AD5000, w/o P2B, COMM	3U VPX GPGPU blade with MXM RTX 5000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, supports common PCIe clock mode, P2B de-populated
VPX3-XMXM/AD5000, w/o P2B, non-COMM	3U VPX GPGPU blade with MXM RTX 5000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, supports non-common PCIe clock mode, P2B de-populated
VPX3-XMXM/AD2000, w/o, P2B, COMM	3U VPX GPGPU blade with MXM RTX 2000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, supports common PCIe clock mode, P2B de-populated
VPX3-XMXM/AD2000, w/o P2B, non-COMM	3U VPX GPGPU blade with MXM RTX 2000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 3x PCIe x8, supports non-common PCIe clock mode, P2B de-populated

Without P2 Connector (P0+P1)

SKU	Description
VPX3-XMXM/AD5000, w/o P2, COMM	3U VPX GPGPU blade with MXM RTX 5000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 2x PCIe x8, supports common PCIe clock mode, P2 fully de-populated
VPX3-XMXM/AD5000, w/o P2, non-COMM	3U VPX GPGPU blade with MXM RTX 5000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 2x PCIe x8, supports non-common PCIe clock mode, P2 fully de-populated
VPX3-XMXM/AD2000, w/o P2, COMM	3U VPX GPGPU blade with MXM RTX 2000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 2x PCIe x8, supports common PCIe clock mode, P2 fully de-populated
VPX3-XMXM/AD2000, w/o P2, non-COMM	3U VPX GPGPU blade with MXM RTX 2000 ADA, SOSA aligned, conformal coating & ETT, -40 to +85°C, conduction-cooled, with 2x PCIe x8, supports non-common PCIe clock mode, P2 fully de-populated

# Package Contents The VPX3-XMXM is packaged with the following components. If any of the items on the contents list are missing or dam- aged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the VPX3-XMXM are non-standard configurations and may vary depending on customer requests. # GPGU Blade VPX3-XMXM o Thermal module is assembled on the board ![The image displays a white document icon with a folded top-right corner. Faint horizontal grey lines run across the page, simulating text. A large, bold red checkmark is superimposed over the document, extending diagonally from the bottom left to the top right.](.vpx3-xmxm-50m-32214-1000-10/807e19a9162a7a2a91747f87a7663b760d28b6da4fb37c9c8da6848cfed8cbb2.jpg) NOTE: The contents of non-standard VPX3-XMXM configurations may vary depending on the customer’s requirements. ![The image displays a standard warning sign featuring a yellow triangle with a black border. Inside the triangle is a black exclamation point. Below the triangle, the text 'CAUTION:' is printed in black capital letters.](.vpx3-xmxm-50m-32214-1000-10/ef0b34455f57b1a59b7decf5fbc05a234c8ba5949282cd20fed2a2d50b290955.jpg) This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the antistatic bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components. # 2 Specifications Product Specifications

Architecture	3U VPX carrier board with one MXM slot
VITA standards	VITA 46/48/65 compliantSOSA aligned
Slot Profile	SLT3-PAY-2F2U-14.2.3 (PCIe Upstream Port: P1A)SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-0, P2B de-populated (PCIe Upstream Port: P1B)SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-0, P2 fully de-populated (PCIe Upstream Port: P1B)
PCI Express	One PCIe Gen4 x8 to P1A, configurable as two PCIe x4One PCIe Gen4 x8 to P1B, configurable as two PCIe x4One PCIe Gen4 x8 to P2A (SKU option), configurable as two PCIe x4Two of PCIe Gen4 x8 (P1B + P2A) can be configured to one PCIe x16
Video Output	One DisplayPort 1.4a output to P2B (SKU option)
USB	Two USB3.2 Gen 1x1 from SBC to P2B via PCIe switch (SKU option)One USB2.0 from SBC to P2B via PCIe switch (SKU option)
COM	One RS-232 from SBC to P2B via PCIe switch (SKU option)
GPIO	Two GPIO to P2A for multi-configuration (SKU option)Two GPIO to P2A for upstream/downstream rest (SKU option)
Others	One maintenance port (default RS-232)One UART connects directly from the PCIe switch to P1A for PCIe switch debugging
Power Input	12V(VS1/VS2) and 3.3V_AUX only
Operating System	Windows 10/11 64-bitLinux (Support by request)
Miscellaneous	Status LED (Appendix 1)Board reset button on front panel
Mechanical	Form Factor3U VPX, conduction-cooled construction, 1" pitch (VITA 48.2)Thermal DissipationConduction-cooling by wedge locks
Environmental	Operating Temp.-40°C to +85°C at wedge locks (VITA47.0, ECC4-CC4)Storage Temp.-55°C to +100°CVibrationRandom: 12Grms, 5Hz to 2000Hz (VITA47.0, ECC4-V3)Sinusoidal: 5g, 20Hz to 2000HzShock40g, 11ms (VITA47.0, ECC4-OS2)Relative Humidity95% non-condensingAltitude60,000 feet. (operating)EMCCE (EN555032 / EN55035); FCC Part 15B Class A

# Functional Descriptions The following sections describe the VPX3-XMXM (GPU) features and functions. GPGU Specifications

	VPX3-XMXM/AD5000	VPX3-XMXM/AD2000
GPU	NVIDIA RTXTM 5000 ADA	NVIDIA RTXTM 2000 ADA
Memory	16GB GDDR6 memoryBandwidth: 576GB/s	8GB GDDR6 memoryBandwidth: 256GB/s
CUDA Cores	9728 CUDA cores42.6 TFLOPS peak (FP32 performance)	3072 CUDA cores14.5 TFLOPS peak (FP32 performance)
Tensor Cores	304 Tensor Cores	96 Tensor Cores
RT Cores	76 RT Cores	24 RT Cores
Compute API	CUDA Tool Kit 8.0 and aboveCUDA Compute version 8 and above, OpenCLTM 1.2
Graphics API	DirectX® 12, OpenGL 4.6Graphics API
TGP Configuration	80W (115W configurable by request)	60W
Base Clock	930 MHz	1635 MHz
Boost Clock	1680 MHz	2115 MHz
PCIe	PCIe Gen4 x16	PCIe Gen4 x8

# GDDR6 Memory GDDR6 (Graphics Double Data Rate 6) synchronous graphics RAM (SGRAM) conforms to the standards set by the JEDEC GDDR6 specification. It is specifically designed for use in graphics devices that demand high memory bandwidth, such as 3D gaming systems and HD video editing platforms. This dedicated memory serves the Graphics Processing Unit (GPU), reducing the display and graphics load on the system’s main memory and significantly improving GPU and overall display performance. As a result, it enables a much richer visual experience than would be possible with integrated graphics alone. # 3 Block Diagram BlockDiagram ![**Labeled Blocks:**\n* MXM GPU\n* Microchip PCIe Switch PM43052B1-F3EI (52 lanes)\n* IPMC\n* MUX\n* USB Bridge Renesas\n* UART Bridge FTDI\n* P0, P1A, P1B, P2A, P2B (vertical strip on the right edge)\n\n**Connections:**\n* **Microchip PCIe Switch** connects to **MXM GPU** via a red arrow labeled **PCIe x16**.\n* **Microchip PCIe Switch** connects to **P1A** via a red arrow labeled **PCIe x8**.\n* **Microchip PCIe Switch** connects to **P1B** via a red arrow labeled **PCIe x8**.\n* **Microchip PCIe Switch** connects to the bottom section (near **P2A**/**P2B**) via a red arrow labeled **PCIe x8**.\n* **Microchip PCIe Switch** connects to **MUX** (black arrow pointing up).\n* **MUX** connects to **IPMC** (black arrow pointing up).\n* **IPMC** connects to **P0** via a black arrow labeled **IPMC (I2C)**.\n* **P0** sends signals **SYSRST** (blue line) and **REFCLK #1/#2** (orange line) to the **IPMC**/**MUX** area.\n* **IPMC**/**MUX** area connects to **P1A** via black arrows labeled **1x Maintenance Port** and **1x UART (Debug)**.\n* **Microchip PCIe Switch** connects to **USB Bridge Renesas** via a green double arrow.\n* **USB Bridge Renesas** connects to **UART Bridge FTDI** via a green double arrow.\n* **UART Bridge FTDI** connects to **P2B** via green/blue arrows labeled **2x USB3, 1x USB2**, **1x RS-232**, and **1x DisplayPort**.\n* **Microchip PCIe Switch** connects to the **P2A**/**P2B** area via purple/pink lines labeled **2x GPIO for Multi-Configuration**, **2x GPIO for up/downstream reset**, and **Downstream Common Mode Clock out #1/#2**.\n\n**Additional Labels:**\n* Next to **P1A**: **x4**, **x4**, bracket **x8**.\n* Next to **P1B**: **x4**, **x4**, bracket **x8**.\n* Next to **P2A**: **x4**, **x4**, bracket **x8**.\n* Large bracket covering **P2A** and **P2B**: **x16**.\n* Text **Configurable PCIe lane** is next to the bottom section.](.vpx3-xmxm-50m-32214-1000-10/2095861c4faa0e7293674b673949aca3b33eca45640bfe4a3d11ad9be453f475.jpg) Figure 1: Functional block diagram This page intentionally left blank. # 4 Mechanical Layout # Mechanical Dimensions ![The image displays a technical line drawing of a rectangular electronic device or module presented in three views: top, front, and side profile. Blue dimension lines indicate the following measurements:\n\n* **Top View:** The vertical dimension is **23.60**.\n* **Front View:** The vertical dimension is **160** and the horizontal width is **99.85**. The face of the device shows a grid of mounting screw holes and a connector strip along the top edge.\n* **Side View:** Two horizontal measurements are visible at the bottom: **16.30** and **7.30**.](.vpx3-xmxm-50m-32214-1000-10/b4de5abadc3e2bd0837b5303a179426ebabe5c449d8c16c80d07bbe434ae226b.jpg) Figure 2: Mechanical dimensions # Connectors, Switch Locations, and LEDs Status This chapter illustrates the board layouts, connector pin assignments, and jumper settings. # Board Layout ![1\n2\n3\n4\n5\n6\n7\n8\nSTD](.vpx3-xmxm-50m-32214-1000-10/3b3f21a5d623e172f88b194d44043f99f453d72952d89034f1a797a532e558df.jpg) Figure 3: Top side board layout (carrier only) Table 1: Top side board layout labels (carrier only)

1	VPX Connector_P0	5	VPX Connector_P2B
2	VPX Connector_P1A	6	MXM Connector
3	VPX Connector_P1B	7	PCIe Switch PM43052B1-F3EI
4	VPX Connector_P2A	8	Reset Bottom

![2\n1](.vpx3-xmxm-50m-32214-1000-10/16d3d42384c29d85b7894bf713b213cfd55286defd1c74ac5174b62ad610fd54.jpg) Figure 4: Bottom side board layout (carrier only) Table 2: Bottom side board layout labels (carrier only)

IPMC STM32F407IEH7

LEDs

# LED Status ![1\n2\n3\n4\n5\n6\n7\n8\nGreen\nBlue\nOrange\nGreen\nGreen / Orange\nRed\nRed](.vpx3-xmxm-50m-32214-1000-10/13cce7b08ba335a0351a2705eca5bda255f2311ac2dc87ca99a82e71d4e5cbec.jpg) Figure 5: LED locations Table 3: LED status

No.	Function	Color	Blink Rate	Description
1	Power	Green	Always on	Board power ready
			Off	Board power NOT ready
2	IPMC Heartbeat	Blue	One blink per second	IPMC ready
			Off	IPMC NOT ready
3	PCIe SwitchHeartbeat &Debug	Green	One blink per second	PCIe switch ready
			Off	PCIe switch NOT ready
		Orange	Off	Normal Status
			Always on	MXM GPU abnormal
4	Internal Heater	Orange	Off	Heater off
			Four blinks per second	Heater on (below -20C)
5	IPMCMaintenance PortSelection	Green	Off	Maintenance port is RS-232 (default)
			Always on	Maintenance port is UART
6	PCIe SwitchDebug PortSelection	Green	Off	PCIe switch debug port to IPMC
			Always on	PCIe switch debug port to P1A (default)
7	MXM GPUTemperature	Red	Off	MXM GPU in normal temperature
			Four blinks per second	MXM GPU in critical temperature
8	BoardTemperature	Red	Off	Board in normal temperature
			Four blinks per second	Board in critical temperature

# 5 Connector Pinouts # VPX Connectors # P0+P1+P2 SKUs P0 Connector

Pin	G	F	E	D	C	B	A
1	P_+12V_PSU	P_+12V_PSU	P_+12V_PSU	NC	NC	NC	NC
2	P_+12V_PSU	P_+12V_PSU	P_+12V_PSU	NC	NC	NC	NC
3	NC	NC	NC	NC	NC	NC	NC
4	IPMB_PORTB_CLK	IPMB_PORTB_DAT	GND	NC	GND	P0_SYSRST-L	NVMRO_EXT_IN
5	GAP	GA4	GND	P_+3V3_AUX	GND	IPMB_PORTA_CLK	IPMB_PORTA_DAT
6	GA3	GA2	GND	NC	GND	GA1	GA0
7	IPMB_JTCK	GND	IPMB_JTDO	IPMB_JTDI	GND	IPMB_JTMS	IPMB_JTRST-L
8	GND	REF1_PCIECLK-	REF1_PCIECLK+	GND	REF2_PCIECLK-	REF2_PCIECLK+	GND

P1 Connector

Pin	G	F	E	D	C	B	A
1	GDiscrete1#	GND	SKT3_PCIE_TX0_N	SKT3_PCIE_TX0_P	GND	SKT3_PCIE_RX0_N-	SKT3_PCIE_RX0_P
2	GND	SKT3_PCIE_TX1_N	SKT3_PCIE_TX1_P	GND	SKT3_PCIE_RX1_N	SKT3_PCIE_RX1_P	GND
3	NC	GND	SKT3_PCIE_TX2_N	SKT3_PCIE_TX2_P	GND	SKT3_PCIE_RX2_N	SKT3_PCIE_RX2_P
4	GND	SKT3_PCIE_TX3_N	SKT3_PCIE_TX3_P	GND	SKT3_PCIE_RX3_N	SKT3_PCIE_RX3_P	GND
5	SYS_CON-L	GND	SKT3_PCIE_TX4_N	SKT3_PCIE_TX4_P	GND	SKT3_PCIE_RX4_N	SKT3_PCIE_RX4_P
6	GND	SKT3_PCIE_TX5_N	SKT3_PCIE_TX5_P	GND	SKT3_PCIE_RX5_N-	SKT3_PCIE_RX5_P	GND
7	SW_DEBUG_UART_TX	GND	SKT3_PCIE_TX6_N	SKT3_PCIE_TX6_P	GND	SKT3_PCIE_RX6_N	SKT3_PCIE_RX6_P
8	GND	SKT3_PCIE_TX7_N-	SKT3_PCIE_TX7_P	GND	SKT3_PCIE_RX7_N	SKT3_PCIE_RX7_P	GND
9	IPMC_MTN_UART_TX	GND	SKT1_PCIE_TX0_N-	SKT1_PCIE_TX0_P	GND	SKT1_PCIE_RX0_N	SKT1_PCIE_RX0_P
10	GND	SKT1_PCIE_TX1_N-	SKT1_PCIE_TX1_P	GND	SKT1_PCIE_RX1_N	SKT1_PCIE_RX1_P	GND
11	IPMC_MTN_UART_RX	GND	SKT1_PCIE_TX2_N-	SKT1_PCIE_TX2_P	GND	SKT1_PCIE_RX2_N	SKT1_PCIE_RX2_P
12	GND	SKT1_PCIE_TX3_N--	SKT1_PCIE_TX3_P	GND	SKT1_PCIE_RX3_N	SKT1_PCIE_RX3_P	GND
13	SW_DEBUG_UART_RX	GND	SKT1_PCIE_TX4_N-	SKT1_PCIE_TX4_P	GND	SKT1_PCIE_RX4_N-	SKT1_PCIE_RX4_P
14	GND	SKT1_PCIE_TX5_N	SKT1_PCIE_TX5_P	GND	SKT1_PCIE_RX5_N	SKT1_PCIE_RX5_P	GND
15	MASK_RESET-L	GND	SKT1_PCIE_TX6_N	SKT1_PCIE_TX6_P	GND	SKT1_PCIE_RX6_N	SKT1_PCIE_RX6_P
16	GND	SKT1_PCIE_TX7_N	SKT1_PCIE_TX7_P	GND	SKT1_PCIE_RX7_N-	SKT1_PCIE_RX7_P	GND

P2 Connector

Pin	G	F	E	D	C	B	A
1	PFX52_GPIO1	GND	SKT1_PCIE_TX8_N-	SKT1_PCIE_TX8_P	GND	SKT1_PCIE_RX8_N-	SKT1_PCIE_RX8_P
2	GND	SKT1_PCIE_TX9_N	SKT1_PCIE_TX9_P	GND	SKT1_PCIE_RX9_N-	SKT1_PCIE_RX9_P	GND
3	PFX52_GPIO2	GND	SKT1_PCIE_TX10_N	SKT1_PCIE_TX10_P	GND	SKT1_PCIE_RX10_N-	SKT1_PCIE_RX10_P
4	GND	SKT1_PCIE_TX11_N	SKT1_PCIE_TX11_P	GND	SKT1_PCIE_RX11_N-	SKT1_PCIE_RX11_P	GND
5	PFX52_RESET1	GND	SKT1_PCIE_TX12_N-	SKT1_PCIE_TX12_P	GND	SKT1_PCIE_RX12_N	SKT1_PCIE_RX12_P
6	GND	SKT1_PCIE_TX13_N	SKT1_PCIE_TX13_P	GND	SKT1_PCIE_RX13_N-	SKT1_PCIE_RX13_P	GND
7	PFX52_RESET2	GND	SKT1_PCIE_TX14_N-	SKT1_PCIE_TX14_P	GND	SKT1_PCIE_RX14_N	SKT1_PCIE_RX14_P
8	GND	SKT1_PCIE_TX15_N	SKT1_PCIE_TX15_P	GND	SKT1_PCIE_RX15_N-	SKT1_PCIE_RX15_P	GND
9	P_+3V3_DP	GND	VPXCN_DP_L1_TXN	VPXCN_DP_L1_TXP	GND	VPXCN_DP_L0_TXN-	VPXCN_DP_L0_TXP
10	GND	VPXCN_DP_L3_TXN	VPXCN_DP_L3_TXP	GND	VPXCN_DP_L2_TXN	VPXCN_DP_L2_TXP	GND
11	P_+5V_U3_P1	GND	VPXCN_DP++_CONFIG_R	VPXCN_DP_HPD	GND	VPXCN_DP_AUX_N-	VPXCN_DP_AUX_P
12	GND	VPXCN_U3_P1_TX_N	VPXCN_U3_P1_TX_P	GND	VPXCN_U3_P1_RX_N	VPXCN_U3_P1_RX_P	GND
13	P_+5V_U3_P2	GND	VPXCN_U3_P2_TX_N	VPXCN_U3_P2_TX_P	GND	VPXCN_U3_P2_RX_N	VPXCN_U3_P2_RX_P
14	GND	VPXCN_U2_P3_TX_N	VPXCN_U2_P3_TX_P	GND	VPXCN_U2_P1_TX_N	VPXCN_U2_P1_TX_P	GND
15	P_+5V_U2_P3	GND	VPXCN_UART_RX	VPXCN_UART_TX	GND	VPXCN_U2_P2_TX_N	VPXCN_U2_P2_TX_P
16	GND	VPXCN_DS2_REF_CLKN	VPXCN_DS2_REF_CLKP	GND	VPXCN_DS1_REF_CLKN	VPXCN_DS1_REF_CLKP	GND

# P0+P1+P2A SKUs P0 Connector

Pin	G	F	E	D	C	B	A
1	P_+12V_PSU	P_+12V_PSU	P_+12V_PSU	NC	NC	NC	NC
2	P_+12V_PSU	P_+12V_PSU	P_+12V_PSU	NC	NC	NC	NC
3	NC	NC	NC	NC	NC	NC	NC
4	IPMB_PORTB_CLK	IPMB_PORTB_DAT	GND	NC	GND	P0_SYSRST-L	NVMRO_EXT_IN
5	GAP	GA4	GND	P_+3V3_AUX	GND	IPMB_PORTA_CLK	IPMB_PORTA_DAT
6	GA3	GA2	GND	NC	GND	GA1	GA0
7	IPMB_JTCK	GND	IPMB_JTDO	IPMB_JTDI	GND	IPMB_JTMS	IPMB_JTRST-L
8	GND	REF1_PCIECLK-	REF1_PCIECLK+	GND	REF2_PCIECLK-	REF2_PCIECLK+	GND

P1 Connector

Pin	G	F	E	D	C	B	A
1	GDiscrete1#	GND	SKT3_PCIE_TX0_N	SKT3_PCIE_TX0_P	GND	SKT3_PCIE_RX0_N-	SKT3_PCIE_RX0_P
2	GND	SKT3_PCIE_TX1_N	SKT3_PCIE_TX1_P	GND	SKT3_PCIE_RX1_N	SKT3_PCIE_RX1_P	GND
3	NC	GND	SKT3_PCIE_TX2_N	SKT3_PCIE_TX2_P	GND	SKT3_PCIE_RX2_N	SKT3_PCIE_RX2_P
4	GND	SKT3_PCIE_TX3_N	SKT3_PCIE_TX3_P	GND	SKT3_PCIE_RX3_N	SKT3_PCIE_RX3_P	GND
5	SYS_CON-L	GND	SKT3_PCIE_TX4_N	SKT3_PCIE_TX4_P	GND	SKT3_PCIE_RX4_N	SKT3_PCIE_RX4_P
6	GND	SKT3_PCIE_TX5_N	SKT3_PCIE_TX5_P	GND	SKT3_PCIE_RX5_N-	SKT3_PCIE_RX5_P	GND
7	SW_DEBUG_UART_TX	GND	SKT3_PCIE_TX6_N	SKT3_PCIE_TX6_P	GND	SKT3_PCIE_RX6_N	SKT3_PCIE_RX6_P
8	GND	SKT3_PCIE_TX7_N-	SKT3_PCIE_TX7_P	GND	SKT3_PCIE_RX7_N	SKT3_PCIE_RX7_P	GND
9	IPMC_MTN_UART_TX	GND	SKT1_PCIE_TX0_N-	SKT1_PCIE_TX0_P	GND	SKT1_PCIE_RX0_N	SKT1_PCIE_RX0_P
10	GND	SKT1_PCIE_TX1_N-	SKT1_PCIE_TX1_P	GND	SKT1_PCIE_RX1_N	SKT1_PCIE_RX1_P	GND
11	IPMC_MTN_UART_RX	GND	SKT1_PCIE_TX2_N-	SKT1_PCIE_TX2_P	GND	SKT1_PCIE_RX2_N	SKT1_PCIE_RX2_P
12	GND	SKT1_PCIE_TX3_N--	SKT1_PCIE_TX3_P	GND	SKT1_PCIE_RX3_N	SKT1_PCIE_RX3_P	GND
13	SW_DEBUG_UART_RX	GND	SKT1_PCIE_TX4_N-	SKT1_PCIE_TX4_P	GND	SKT1_PCIE_RX4_N-	SKT1_PCIE_RX4_P
14	GND	SKT1_PCIE_TX5_N	SKT1_PCIE_TX5_P	GND	SKT1_PCIE_RX5_N	SKT1_PCIE_RX5_P	GND
15	MASK_RESET-L	GND	SKT1_PCIE_TX6_N	SKT1_PCIE_TX6_P	GND	SKT1_PCIE_RX6_N	SKT1_PCIE_RX6_P
16	GND	SKT1_PCIE_TX7_N	SKT1_PCIE_TX7_P	GND	SKT1_PCIE_RX7_N-	SKT1_PCIE_RX7_P	GND

P2A Connector

Pin	G	F	E	D	C	B	A
1	PFX52_GPIO1	GND	SKT1_PCIE_TX8_N-	SKT1_PCIE_TX8_P	GND	SKT1_PCIE_RX8_N-	SKT1_PCIE_RX8_P
2	GND	SKT1_PCIE_TX9_N	SKT1_PCIE_TX9_P	GND	SKT1_PCIE_RX9_N-	SKT1_PCIE_RX9_P	GND
3	PFX52_GPIO2	GND	SKT1_PCIE_TX10_N	SKT1_PCIE_TX10_P	GND	SKT1_PCIE_RX10_N-	SKT1_PCIE_RX10_P
4	GND	SKT1_PCIE_TX11_N	SKT1_PCIE_TX11_P	GND	SKT1_PCIE_RX11_N-	SKT1_PCIE_RX11_P	GND
5	PFX52_RESET1	GND	SKT1_PCIE_TX12_N-	SKT1_PCIE_TX12_P	GND	SKT1_PCIE_RX12_N	SKT1_PCIE_RX12_P
6	GND	SKT1_PCIE_TX13_N	SKT1_PCIE_TX13_P	GND	SKT1_PCIE_RX13_N-	SKT1_PCIE_RX13_P	GND
7	PFX52_RESET2	GND	SKT1_PCIE_TX14_N-	SKT1_PCIE_TX14_P	GND	SKT1_PCIE_RX14_N	SKT1_PCIE_RX14_P
8	GND	SKT1_PCIE_TX15_N	SKT1_PCIE_TX15_P	GND	SKT1_PCIE_RX15_N-	SKT1_PCIE_RX15_P	GND

# P0+P1 SKUs P0 Connector

Pin	G	F	E	D	C	B	A
1	P_+12V_PSU	P_+12V_PSU	P_+12V_PSU	NC	NC	NC	NC
2	P_+12V_PSU	P_+12V_PSU	P_+12V_PSU	NC	NC	NC	NC
3	NC	NC	NC	NC	NC	NC	NC
4	IPMB_PORTB_CLK	IPMB_PORTB_DAT	GND	NC	GND	P0_SYSRST-L	NVMRO_EXT_IN
5	GAP	GA4	GND	P_+3V3_AUX	GND	IPMB_PORTA_CLK	IPMB_PORTA_DAT
6	GA3	GA2	GND	NC	GND	GA1	GA0
7	IPMB_JTCK	GND	IPMB_JTDO	IPMB_JTDI	GND	IPMB_JTMS	IPMB_JTRST-L
8	GND	REF1_PCIECLK-	REF1_PCIECLK+	GND	REF2_PCIECLK-	REF2_PCIECLK+	GND

P1 Connector

Pin	G	F	E	D	C	B	A
1	GDiscrete1#	GND	SKT3_PCIE_TX0_N	SKT3_PCIE_TX0_P	GND	SKT3_PCIE_RX0_N-	SKT3_PCIE_RX0_P
2	GND	SKT3_PCIE_TX1_N	SKT3_PCIE_TX1_P	GND	SKT3_PCIE_RX1_N	SKT3_PCIE_RX1_P	GND
3	NC	GND	SKT3_PCIE_TX2_N	SKT3_PCIE_TX2_P	GND	SKT3_PCIE_RX2_N	SKT3_PCIE_RX2_P
4	GND	SKT3_PCIE_TX3_N	SKT3_PCIE_TX3_P	GND	SKT3_PCIE_RX3_N	SKT3_PCIE_RX3_P	GND
5	SYS_CON-L	GND	SKT3_PCIE_TX4_N	SKT3_PCIE_TX4_P	GND	SKT3_PCIE_RX4_N	SKT3_PCIE_RX4_P
6	GND	SKT3_PCIE_TX5_N	SKT3_PCIE_TX5_P	GND	SKT3_PCIE_RX5_N-	SKT3_PCIE_RX5_P	GND
7	SW_DEBUG_UART_TX	GND	SKT3_PCIE_TX6_N	SKT3_PCIE_TX6_P	GND	SKT3_PCIE_RX6_N	SKT3_PCIE_RX6_P
8	GND	SKT3_PCIE_TX7_N-	SKT3_PCIE_TX7_P	GND	SKT3_PCIE_RX7_N	SKT3_PCIE_RX7_P	GND
9	IPMC_MTN_UART_TX	GND	SKT1_PCIE_TX0_N-	SKT1_PCIE_TX0_P	GND	SKT1_PCIE_RX0_N	SKT1_PCIE_RX0_P
10	GND	SKT1_PCIE_TX1_N-	SKT1_PCIE_TX1_P	GND	SKT1_PCIE_RX1_N	SKT1_PCIE_RX1_P	GND
11	IPMC_MTN_UART_RX	GND	SKT1_PCIE_TX2_N-	SKT1_PCIE_TX2_P	GND	SKT1_PCIE_RX2_N	SKT1_PCIE_RX2_P
12	GND	SKT1_PCIE_TX3_N-	SKT1_PCIE_TX3_P	GND	SKT1_PCIE_RX3_N	SKT1_PCIE_RX3_P	GND
13	SW_DEBUG_UART_RX	GND	SKT1_PCIE_TX4_N-	SKT1_PCIE_TX4_P	GND	SKT1_PCIE_RX4_N-	SKT1_PCIE_RX4_P
14	GND	SKT1_PCIE_TX5_N	SKT1_PCIE_TX5_P	GND	SKT1_PCIE_RX5_N	SKT1_PCIE_RX5_P	GND
15	MASK_RESET-L	GND	SKT1_PCIE_TX6_N	SKT1_PCIE_TX6_P	GND	SKT1_PCIE_RX6_N	SKT1_PCIE_RX6_P
16	GND	SKT1_PCIE_TX7_N	SKT1_PCIE_TX7_P	GND	SKT1_PCIE_RX7_N-	SKT1_PCIE_RX7_P	GND

# 6 Driver Installation The VPX3-XMXM/ADA2000 or ADA5000 drivers are available from the ADLINK website. Ada 2000 Driver: https://www.adlinktech.com/Products/DownloadSoftwareDriver?lang=zhhant&pdNo=2173&MainCategory=em bedded-graphics-solutions&kind=DR Ada 5000 Driver: https://www.adlinktech.com/Products/DownloadSoftwareDriver?lang=en&pdNo=2244&MainCategory=embedd edgraphics-solutions&kind=DR # Safety Instructions For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment. Read these safety instructions carefully. Keep this user’s manual for future reference. Read the specifications section of this manual for detailed information on the operating environment of this equipment. When installing/mounting or uninstalling/removing equipment: o Turn off power and unplug any power cords/cables. • To avoid electrical shock and/or damage to equipment: o Keep equipment away from water or liquid sources; o Keep equipment away from high heat or high humidity; o Keep equipment properly ventilated (do not block or cover ventilation openings); o Make sure to use recommended voltage and power source settings; o Always install and operate equipment near an easily accessible electrical socket-outlet; o Secure the power cord (do not place any object on/over the power cord); o Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and, o If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source. Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel. A Lithium-type battery may be provided for uninterrupted, backup or emergency power. ![This image displays a standard warning symbol: a red triangle with a white exclamation point centered inside it.](.vpx3-xmxm-50m-32214-1000-10/152020281989708eb201544155d07686022e665a09d57889fd45d8ad1ceede81.jpg) WARNING: Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately. Equipment must be serviced by authorized technicians when: o The power cord or plug is damaged; o Liquid has penetrated the equipment; o It has been exposed to high humidity/moisture; o It is not functioning or does not function according to the user’s manual; o It has been dropped and/or damaged; and/or, o It has an obvious sign of breakage. # Getting Services Ask an Expert: https://www.adlinktech.com/en/Askanexpert # ADLINK Technology, Inc.

Address:	No. 66, Huaya 1st Road, Guishan DistrictTaoyuan City 333, Taiwan
Tel:	+886-3-216-5088
Fax:	+886-3-328-5723
Email:	service@adlinktech.com

# Ampro ADLINK Technology, Inc.

Address:	6450 Via Del Oro, San Jose, CA 95119-1208, USA
Tel:	+1-408-360-0200
Toll Free:	+1-800-966-5200 (USA only)
Fax:	+1-408-600-1189
Email:	info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

Address:	300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area Shanghai, 201203 China
Tel:	+86-21-5132-8988
Fax:	+86-21-5132-3588
Email:	market@adlinktech.com

# ADLINK Technology GmbH

Address:	Hans-Thoma-Strasse 8-10, 68163, Mannheim, Germany
Tel:	+49-621-43214-0
Fax:	+49-621 43214-30
Email:	emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. [🔗 Link to the original document](.vpx3-xmxm-50m-32214-1000-10/vpx3-xmxm-50m-32214-1000-10.pdf)