# VPX3020 Series

Performance Rugged Conduction Cooled 3U VPX Intel® Xeon® Processor E Processor Blade

User’s Manual

![Close-up of a green printed circuit board with various electronic components and gold heat sinks (no visible text or symbols)](.vpx3020-50m-00050-1000-10/6836b91a69b8e8b7f11d70aa3a22ca40337d307559425c59caf753ca57ccd866.jpg)

Manual Rev.: 1.0

Revision Date: August 25, 2022

Part No: 50M-00050-1000

Revision History

<table><tr><td>Revision</td><td>Release Date</td><td>Description of Change(s)</td></tr><tr><td>1.0</td><td>2022/08/25</td><td>Initial release</td></tr></table>

# Preface

# Copyright © 2022 ADLINK Technology, Inc.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

# Disclaimer

The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

# Environmental Responsibility

ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.

![Symbol of a trash bin crossed with a diagonal line and a horizontal bar below (no text or labels)](.vpx3020-50m-00050-1000-10/c83a25ed5ee29e0bc8b371a5e47b990866dcca24caad043d2e50b0faa5d240bd.jpg)

Battery Labels (for products with battery)

![Symbol of a trash bin crossed out by two diagonal lines (no text or numbers present)](.vpx3020-50m-00050-1000-10/e5a74d0ea76962ded3b193dcaaf8169bcb42259d778f86dd5fadbd4fe260069f.jpg)

![Simple recycling symbol icon with three chasing arrows inside a square frame (no text or labels)](.vpx3020-50m-00050-1000-10/6f322975d6e276a39ac54338a8e4d995ed26f53bf8c0329c6d6a3cb82df26ef4.jpg)

Li-ion

![RECYCLE\nRBRC\nLi-ion\n7.800.822.8837](.vpx3020-50m-00050-1000-10/740a55aec85827f94532f10d1ac09ad71e265c81a1b68c2c7f8513cb6412a45a.jpg)

![Abstract geometric pattern with interlocking black and white shapes (no text or symbols)](.vpx3020-50m-00050-1000-10/ec22507a2e87bd22cc42f48c762f0d187778080f7bf38913e0d63f10fd209755.jpg)

ᑜ㔚ᳰ⺧࿁ᡴ

# California Proposition 65 Warning

![This image displays a standard warning symbol. It consists of a yellow equilateral triangle with a thick black border. Centered inside the triangle is a large black exclamation point.](.vpx3020-50m-00050-1000-10/553f44adffe16de854819b8a17c8d5ebe22a9ae0ddb83e69a84710998c9afe23.jpg)

WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or other reproductive harm. For more information go to www.P65Warnings.ca.gov.

# Trademarks

Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

# Conventions

Take note of the following conventions used throughout this manual to make sure that users perform certain tasks and instructions properly.

![The image displays a white document icon with horizontal lines representing text. A large, red checkmark is superimposed over the document.](.vpx3020-50m-00050-1000-10/01a0b713689754d90ba73e7ec014efcf0e9bcf60bee05e8a0b29a9e73b5ed217.jpg)
NOTE:

Additional information, aids, and tips that help users perform tasks.

![The image displays a yellow triangular warning sign with a black border. Centered inside the triangle is a large black exclamation mark. Portions of thick black horizontal lines are visible at the very top and bottom edges of the frame.](.vpx3020-50m-00050-1000-10/01267782a6d041fb33f4e3e7f38920f781d50da59e5ec29b88a9491339aa9137.jpg)
CAUTION:

Information to prevent minor physical injury, component damage, data loss, and/or program corruption when trying to complete a task.

![The image displays a red triangular warning symbol with rounded corners. Centered inside the red triangle is a large white exclamation point. A thin black horizontal line runs across the very top edge of the image, just above the triangle.](.vpx3020-50m-00050-1000-10/6071ca6f6045b5fda2008e43a8711f8f8219ec9e5e49548a114d25d239462e5b.jpg)
WARNING:

Information to prevent serious physical injury, component damage, data loss, and/or program corruption when trying to complete a specific task.

# Table of Contents

# Revision History........... ii

# Preface ........ iii

# List of Figures ....... .... vii

# List of Tables ....... ix

# 1 Introduction .......

1.1 Overview... 1
1.2 Features... 1
1.3 Block Diagrams.. 2
1.4 Model Number Decoder - Processor Blade ... 3
1.5 Package Contents .. 5

# 2 Specifications ........ 7

2.1 VPX3020 Blade Specifications .... 7
2.2 VPX-R3020 RTM Specifications.. 9
2.3 Power Consumption ..... 10

# 3 Functional Description ...... 1 3

3.1 Processors..... 13
3.2 Intel® Turbo Boost Technology . 1 5
3.3 Chipset... 16
3.4 USB .. 16
3.5 SPI BIOS .... . 16
3.6 System Management Bus.... 1 7
3.7 Real Time Clock .. 17
3.8 Serial ATA Controller ... 17
3.9 PCI Express Interface... 17
3.10 Intel ® Gigibit Ethernet Controller I350 ... 1 7
3.11 Graphics ...... 18
3.12 GPIO Expander PCA9554 . 18

3.13 UART NCT5104... 18
3.14 TPM ... 18
3.15 XMC Site... 18

# 4 VPX3020 Board Interfaces ...... . 19

4.1 VPX3020 Board Layout ... 1 9
4.2 VPX3020 Mechanical Dimensions.. . 20
4.3 VPX3020 Connector Pin Assignments .... 2 2
4.4 Status LEDs ..... 27

# 5 VPX-R3020 RTM . .. 29

5.1 Connector Allocation..... 29
5.2 VPX-R3020 Block Diagram.. 30
5.3 VPX-R3020 RTM Board Layout... 3 1
5.4 VPX-R3020 RTM Connector Pin Assignments........... 32

# 6 Getting Started ....... . 37

6.1 Installing the VPX3020 to the Chassis... . 37
6.2 Installing the VPX-R3020 to the Chassis.... 3 7
6.3 Driver Installation ... 38

# 7 Utilities ........ . 39

7.1 Watchdog Timer..... 39

# 8 BIOS Setup .......... ...... 45

8.1 Starting the BIOS ... 45
8.2 Main Setup Menu... 47
8.3 Advanced.. 49
8.4 Server Mgmt .. 58
8.5 Chipset... 59
8.6 Boot .... 71
8.7 Save & Exit .... 73

# Important Safety Instructions....... .. 75

# Getting Service ......... .. 77

# List of Figures

Figure 1-1: VPX3020 Functional Block Diagram.. . 2
Figure 4-1: VPX3020 Top Side Layout . . 19
Figure 4-2: VPX3020 Bottom Side Layout . . 19
Figure 4-3: VPX3020 Conduction-Cooled Mechanical Dimensions. 20
Figure 4-4: VPX3020 Air-Cooled Mechanical Dimensions............... 21
Figure 4-5: VPX3020 Front View . . 27
Figure 5-1: VPX-R3020 RTM Functional Block Diagram ................. 30
Figure 5-2: VPX-R3020 RTM Board Layout.. . 31

This page intentionally left blank.

# List of Tables

Table 1-1: VPX3020 SKU Table .. 4
Table 2-1: VPX3020 Blade Specifications .
Table 2-2: VPX-R3020 RTM Specifications... 9

This page intentionally left blank.

# 1 Introduction

# 1.1 Overview

The VPX3020 Series is a 3U VPX processor blade based on the Intel® Xeon® Processor E-2254ML (formerly "Coffee Lake-H Refresh"), supporting DDR4-2666 ECC soldered memory up to 16GB. For storage, the VPX3020 provides a high endurance soldered 32GB SLC SSD. The VPX3020 is compliant with the VITA 48 and VITA 65 specifications.

The VPX3020 Series with server grade Intel® processor brings extreme computing power with low power consumption. A total of PCIe x16 Gen3 lanes are supported, with PCIe x8 to rear supporting DMA and non-transparent bridge for peer-to-peer communication and PCIe x8 Gen3 to XMC. Graphics is supported by integrated Intel GPU with DisplayPort to P2.

The ADLINK VPX3020 provides an Infineon TPM 2.0 chip for system security, dual BIOS functionality, as well as an ADLINK ABS-Diag self-diagnosis tool. These features bring additional value by ensuring high reliability. All components on the VPX3020 Series are soldered on the PCB board to ensure product reliability and quality, and enable compliance with MIL-STD-810G shock and vibration. The VPX3020 supports a wide operating temperature range from $\angle 4 0 ^ { \circ } \mathsf { C }$ to $+ 7 5 ^ { \circ } \complement$ (optionally up to $+ 8 5 ^ { \circ } \mathsf { C } )$ .

The VPX3020 Series is available in a rugged conduction cooled version with conformal coating and an air cooled version to meet different application needs. A VPX-R3020 Rear Transition Module is available to access rear I/O signals for users to validate VPX3020 functionality.

# 1.2 Features

Intel® Xeon® Processor E-2254ML (formerly "Coffee Lake-H Refresh")
 DDR4-2666 soldered ECC SDRAM up to 16GB
 32GB SATA SLC SSD option
 Up to PCIe x16 Gen3 interface supporting non-transparent bridge
 One XMC expansion slot, PCIe x8 Gen3 with Rear I/O to P2

# 1.3 Block Diagrams

![Based on the provided block diagram, here is an accurate and concise description of the labeled blocks and connections:\n\n**Central Processing and Memory**\n*   **Intel® Xeon® E** ('Coffee Lake' 25W TDP) is the central processor block.\n    *   **DDR4 8Gb + ECC 2666MT/s**: Two blocks are connected to the CPU via **Channel A** and **Channel B**.\n    *   **Display Port**: A connection line extends left from the CPU.\n    *   **DMI**: Connects the CPU to the **Intel® CM246 Chipset** below.\n    *   **PCIe x8 Gen3**: Connects the CPU to the **PCIe Switch** on the right.\n    *   **PCIe 3.0 x8**: Connects the Chipset to the CPU.\n\n**Chipset and Main Bus**\n*   **Intel® CM246 Chipset**: The central hub connecting various components.\n    *   **2x PCIe x4 Gen3** and **PCIe SKU**: Inputs connecting to the left side of the Chipset.\n    *   **SPI**: Connects to **Dual BIOS**.\n    *   **LPC**: Connects to **Super IO NCT5104**.\n    *   **PCIe 2.0 x4**: Connects to **Ethernet Controller Intel I350**.\n    *   **LPC**: Connects to **TPM** and **IPMC**.\n    *   **3x GPIO**: Connects to the bottom bus bar (P1).\n    *   **1x SATA 6Gb/s**: Connects to **SSD Card VPX3020-SSD**.\n    *   **1x SATA 6Gb/s**, **1x USB 3.0**, **1x USB 2.0**: Connect to the bottom bus bar (P2).\n\n**Expansion and Peripheral Blocks**\n*   **PCIe Switch (w/ NTB + DMA) PEX8725**: Located top-right. Contains **Station 0 Port** and **Station 1 Port**.\n    *   Outputs **PCIe Gen3 2 x4** and **PCIe Gen3 1 x4** down to the bottom bus bar.\n*   **XMC**: A blue box containing **J15** and **J16**.\n    *   Connected via **x8d+x12d** (red text) and **XMC SKU** (red text) from the Chipset area.\n*   **Super IO NCT5104**: Contains **COM2** and **COM1**.\n    *   **COM2**: Connects via **UART** to a **Transceiver**, then to **1x RS-232/422/485** (leading to P1).\n    *   **COM1**: Connects via **UART** to a **Transceiver**, then to **1x RS-232/RS422** (leading to P1).\n*   **Ethernet Controller Intel I350**:\n    *   Outputs **1x 1000BASE-T** (via **Transceiver**) and **2x 1000BASE-BX** (leading to P1).\n*   **TPM**: Connected via **LPC**.\n*   **IPMC**: Connected via **LPC**. Outputs **IPMB** to P0.\n\n**Bottom Bus Interface**\n*   An orange bar at the bottom is divided into sections labeled **P2**, **P1**, and **P0**.\n*   **P2**: Receives SATA and USB connections.\n*   **P1**: Receives connections from Super IO, Ethernet, GPIO, and the PCIe Switch.\n*   **P0**: Receives connections from the PCIe Switch and IPMC.](.vpx3020-50m-00050-1000-10/66662313876b39f2c0bc4858ab77c8c4fefe3ef47972e90a9153f34660f41d48.jpg)

Figure 1-1: VPX3020 Functional Block Diagram

# 1.4 Model Number Decoder - Processor Blade

![VPX3020/2254/M16/S32/XMC-R2\n(A) (B) (C) (D) (E)](.vpx3020-50m-00050-1000-10/5327fb48d51b3e8f8e34818257a50f932a8eb7ba6069b8c772f056dbe56225f4.jpg)

# (A) CPU Code

 E-2254ML = Intel® processor E-2254ML, 4 cores, 25W TDP

# (B) Memory Size Code

 $\mathtt { M } 1 6 = 1 6 \mathsf { G B }$ DDR4-2666 ECC soldered SDRAM

# (C) SATA NAND Flash Size Code

 $\$ 32 =9 L C$ NAND flash 32GB SATA 6Gb/s via add-on card

# (D) PCI Express interface code

 ${ \mathsf { X M C } } = { \mathsf { X M C } }$ interface

 $\mathsf { P } 8 = \mathsf { P } \mathsf { C } |$ Express x8 Gen3 (BOM option)

# (E) Ruggedized Level Code

 R1 = Conduction Cooled version supporting $\angle 4 0 ^ { \circ } \mathsf { C }$ to $\yen 75 ^ { \circ } \mathrm { C }$ at card edge

 R2 = Conduction Cooled version supporting $\angle 4 0 ^ { \circ } \mathsf { C }$ to $+ 8 5 ^ { \circ } \mathsf { C }$ at card edge

 $\mathsf { A } 1 = \mathsf { A i r }$ Cooled version supporting $\angle 4 0 ^ { \circ } \mathsf { C }$ to $+ 7 5 ^ { \circ } \complement$

VPX3020 SKU Table

<table><tr><td>Function</td><td>XMC Version</td><td>PCIe Version</td></tr><tr><td>XMC</td><td>PCIe x8 Gen3 (or 2x PCIe x4)w/ rear IO to P2 (X8d+X12d)</td><td>N/A</td></tr><tr><td>Ethernet</td><td colspan="2">1x 1000BASE-T + 2x 1000BASE-BX to P1</td></tr><tr><td rowspan="2">PCIExpress</td><td colspan="2">PCIe Switch downstream port to P1Station 0 port: 2 x4Station 1 port: 1 x4</td></tr><tr><td>N/A</td><td>2x PCIe Gen3 x4 to P2</td></tr><tr><td rowspan="2">SATA6Gbps</td><td colspan="2">SATA 6Gb/s to P2</td></tr><tr><td colspan="2">SATA 6Gb/s SLC NAND flash 32GB</td></tr><tr><td>GPIO</td><td colspan="2">3x GPIO</td></tr><tr><td rowspan="2">Serial</td><td colspan="2">1x RS-232/422 (COM1) to P2</td></tr><tr><td colspan="2">1x RS-232/422/485 (COM2) to P2 (BOM option as 4x GPIO)</td></tr></table>

Table 1-1: VPX3020 SKU Table
Note: Items in red differ between SKU options.

# 1.5 Package Contents

The VPX3020 is packaged with the following components. If any of the items on the contents list are missing or damaged, retain the shipping carton and packing material and contact the dealer for inspection. Please obtain authorization before returning any product to ADLINK. The packing contents of the VPX3020 are non-standard configurations and may vary depending on customer requests.

# Processor Blade

 VPX3020

 CPU and memory specifications will differ depending on options selected
 Thermal module is assembled on the board

# Rear Transition Module (optional)

 VPX-R3020 RTM

# Test Backplane (optional)

 tBP-VPX3020 test backplane

![An icon depicting a white document with horizontal gray lines and a folded top-right corner, overlaid with a large, bold red checkmark.](.vpx3020-50m-00050-1000-10/ae8eef7a72730a0e180b7ce900e89e131b08a6b1d9b0db1e686b0f694fa25934.jpg)
NOTE:

The contents of non-standard VPX3020 configurations may vary depending on the customer requirements.

![A yellow triangular warning sign featuring a black exclamation mark in the center. Below the triangle, the text reads 'CAUTION:' in black capital letters.](.vpx3020-50m-00050-1000-10/c54ad2d3adab505c784348f9ed3c7e436571e7b31e5936252d91f887c632e840.jpg)

This product must be protected from static discharge and physical shock. Never remove any of the components except at a static-free workstation. Use the anti-static bag shipped with the product when putting the board on a surface. Wear an anti-static wrist strap properly grounded on one of the system's ESD ground jacks when installing or servicing system components.

This page intentionally left blank.

# 2 Specifications

# 2.1 VPX3020 Blade Specifications

<table><tr><td>VITAStandards</td><td>VITA 46.0 VPX Base StandardVITA 46.4 PCI Express on VPX Fabric ConnectorVITA 46.6 Gigabit Ethernet Control Plane on VPXVITA 46.9 PMC/XMC/Ethernet Signal Mapping to 3U/6U VPXVITA 46.10 Rear Transition Module on VPXVITA 46.11 System Management on VPXVITA 48.0 Ruggedized Enhanced Design Implementation Mechanical Base SpecificationVITA 65 OpenVPX Architecture Framework for VPX</td></tr><tr><td>Mechanical</td><td>Conduction-cooled 3U VPXAir-cooled 3U VPX</td></tr><tr><td>Processor</td><td>Intel® Xeon® Processor E-2254ML, 4 cores, 25W TDP</td></tr><tr><td>Chipset</td><td>Intel® CM246 Chipset</td></tr><tr><td>Memory</td><td>Dual channel 1.2V DDR4 2666MT/s SDRAM with ECC, up to 16GB</td></tr><tr><td>USB</td><td>1x USB 3.0 (backwards compatible) to P2(can be separated to USB 3.0 only + USB 2.0)</td></tr><tr><td>XMC</td><td>PCIe x8 Gen3 w/ rear IO (X8d+X12d) to P2 (XMC SKU only)</td></tr><tr><td>GigabitEthernet</td><td>1x 10/100/1000BASE-T + 2x 10/100/1000BASE-BX to P1</td></tr><tr><td>PCI Express</td><td>2x PCIe switch downstream port configuration to P1:□ Station 0 port: 2 x4□ Station 1 port: 1 x42x PCIe 3.0 x4 to P2 (PCIe SKU only)</td></tr><tr><td>SATA</td><td>SATA 6Gb/s to P2SATA 6Gb/s SLC NAND flash 32GB</td></tr><tr><td>Graphics</td><td>1x DisplayPort to P2Integrated Intel® GPU engine</td></tr><tr><td>IPMC</td><td>Smart Fusion A2F200 with VPX code base</td></tr><tr><td>GPIO</td><td>3x GPIO to P1</td></tr></table>

Table 2-1: VPX3020 Blade Specifications

<table><tr><td>Serial</td><td>1x RS-232/422 (COM1) to P21x RS-232/422/485 (COM2) to P2Note:RS-422 on COM1 &amp; RS-485 on COM2 are not simultaneously supported.</td></tr><tr><td>RTC</td><td>To P1</td></tr><tr><td>TPM</td><td>Infineon TPM version 2.0</td></tr><tr><td>LEDs</td><td>Status LEDs on front and rear</td></tr><tr><td>Reset Button</td><td>On front panel</td></tr><tr><td>Watchdog Timer</td><td>System reset or NMI with programmable interval</td></tr><tr><td>Environmental</td><td>Operating Temperature: -40°C to +85°C at wedge locksStorage Temperature: -50°C to +100°CRelatively Humidity: 95% non-condensingShock: sawtooth 40G, 11ms, each axis, operatingVibration: 15Hz-2KHz, 12Grms, random, each axis, operatingThermal Dissipation: convection and conductionOperating Altitude: 60,000 feet (VITA 47)</td></tr><tr><td>EMI</td><td>CE, FCC Class A</td></tr></table>

Table 2-1: VPX3020 Blade Specifications

Note: Specifications are subject to change without prior notice.

# 2.2 VPX-R3020 RTM Specifications

<table><tr><td>Ethernet</td><td>• 2x 1000BASE-BX via RP1• 1x 1000BASE-T via RP1</td></tr><tr><td>Graphics</td><td>• 1x DisplayPort signal via RP1</td></tr><tr><td>SATA</td><td>• 1x SATA 6Gb/s via RP1 (7 pin vertical SATA connector)</td></tr><tr><td>USB</td><td>• 1x USB 3.0 (backwards compatible) via RP1</td></tr><tr><td>Serial</td><td>• Serial Port 1: RS232 (2T2R) via RP1 (DB-9 connector)• Serial Port 2: RS232 (2T2R) via RP2 (2x5 pin header)</td></tr><tr><td>GPIO</td><td>• 2-bit GPIO signal via RP1 (2x3 pin header)</td></tr><tr><td>PCIe</td><td>• 1x PCIe x4 via RP0, 2x PCIe x4 via RP1• 2x PCIe x4 via RP2</td></tr><tr><td>JTAG</td><td>• JTAG via RP0 (2x5 pin header)</td></tr><tr><td>Reset</td><td>• Reset via RP0</td></tr><tr><td>SMBus</td><td>• SMBus signal via RP0</td></tr><tr><td>Power</td><td>• Power terminal for +12V, +5V, +3.3V, GND</td></tr></table>

Table 2-2: VPX-R3020 RTM Specifications

Note: Specifications are subject to change without prior notice.

# 2.3 Power Consumption

This section provides information on the power consumption of the VPX3020 Series when using Intel® Xeon® E-2254ML processors with Dual Channel 8GB DDR4-2666 soldered memory and SATA SSD. The VPX3020 is powered by 5V and 3.3V. Windows 10 Typical power consumption was measured running BurnInTest at 100% loading. Windows 10 Max Loading power consumption was measured running Intel TAT test at 100% loading.

<table><tr><td>Processor</td><td>Xeon® E-2254ML (1.7 GHz)</td></tr><tr><td colspan="2">Windows Idle mode, EIST Enabled</td></tr><tr><td>3.3V (A)</td><td>2.03</td></tr><tr><td>5V (A)</td><td>0.77</td></tr><tr><td>Power Cons. (W)</td><td>10.55</td></tr><tr><td colspan="2">Windows Idle mode, EIST Disabled</td></tr><tr><td>3.3V (A)</td><td>2.02</td></tr><tr><td>5V (A)</td><td>0.78</td></tr><tr><td>Power Cons. (W)</td><td>10.57</td></tr><tr><td colspan="2">Windows Typical mode, EIST Enabled</td></tr><tr><td>3.3V (A)</td><td>3.5</td></tr><tr><td>5V (A)</td><td>6.3</td></tr><tr><td>Power Cons. (W)</td><td>43.05</td></tr><tr><td colspan="2">Windows Typical mode, EIST Disabled</td></tr><tr><td>3.3V (A)</td><td>3.1</td></tr><tr><td>5V (A)</td><td>6.1</td></tr><tr><td>Power Cons. (W)</td><td>40.73</td></tr><tr><td colspan="2">Windows Max Loading mode, EIST Enabled</td></tr><tr><td>Package Power reading (TAT)</td><td>25.00W</td></tr><tr><td>Package Temperature reading (TAT)</td><td>74°C</td></tr><tr><td>CPU DTS reading (TAT)</td><td>72°C</td></tr><tr><td>CPU frequency reading (TAT)</td><td>1287MHz</td></tr><tr><td>3.3V (A)</td><td>2.7</td></tr><tr><td>5V (A)</td><td>6.45</td></tr><tr><td>Power Cons. (W)</td><td>41.74</td></tr><tr><td colspan="2">Windows Max Loading mode, EIST Disabled</td></tr><tr><td>Package Power reading (TAT)</td><td>24.98W</td></tr><tr><td>Package Temperature reading (TAT)</td><td>72°C</td></tr><tr><td>CPU DTS reading (TAT)</td><td>72°C</td></tr><tr><td>CPU frequency reading (TAT)</td><td>1287MHz</td></tr><tr><td>3.3V (A)</td><td>2.7</td></tr><tr><td>5V (A)</td><td>6.45</td></tr><tr><td>Power Cons. (W)</td><td>41.16</td></tr></table>

This page intentionally left blank.

# 3 Functional Description

The following sections describe the VPX3020 features and functions.

# 3.1 Processors

The Intel® Xeon® E Processor is a 64-bit, multi-core processor built on 14-nanometer process technology. The processor is designed for a two-chip platform consisting of a processor and chipset. The platform enables higher performance, lower cost, easier validation, and improved x-y footprint. The processor includes an Integrated Display Engine, Processor Graphics and Integrated Memory Controller.

<table><tr><td>Features</td><td>Xeon® E-2254ML</td></tr><tr><td>Clock</td><td>1.7 GHz</td></tr><tr><td>Max. Single Core Turbo Freq.</td><td>3.5 GHz</td></tr><tr><td>Last Level Cache</td><td>8MB</td></tr><tr><td>No. of Cores/Threads</td><td>4/8</td></tr><tr><td>Maximum Power (TDP $^{1}$ )</td><td>25 W</td></tr><tr><td> $T_{case,MAX}^{2}$ </td><td>100°C</td></tr><tr><td>Operating Temperature</td><td>-40°C to 85°C</td></tr></table>

# Notes:

1. The highest expected sustainable power while running known power intensive applications. TDP is not the maximum power that the processor can dissipate.
2. The maximum supported operating temperature.

# Supported Technologies

 Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
 Intel® Virtualization Technology (Intel® VT-x)
 Intel® VT-x with Extended Page Tables (EPT)
 Intel® Hyper-Threading Technology (Xeon® E-2254ML only)
 Intel® 64 Architecture
 Execute Disable Bit
 Intel® Turbo Boost Technology 2.0
 Intel® TSX-NI
 Enhanced Intel SpeedStep® Technology
 Thermal Monitoring Technologies

# Interfaces

 Dual channel DDR4 memory with two channel of soldered SDRAM
 Memory DDR4 data transfer rates of 2666 MT/s
 64-bit wide channels plus 8-bits of ECC support for each channel
 System Memory Interface I/O Voltage of 1.2V
The PCI Express lanes are fully-compliant with the PCI Express Base Specification, Revision 3.0, including support for 8.0 GT/s transfer speeds.

# 3.2 Intel® Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating core and/or render clock frequency when there is sufficient power headroom, and the product is within specified temperature and current limits. The Intel Turbo Boost Technology feature is designed to increase performance of both multi-threaded and single-threaded workloads. The processor supports a Turbo mode where the processor can use the thermal capacity associated with package and run at power levels higher than TDP power for short durations. This improves the system responsiveness for short, bursty usage conditions.

Turbo Mode availability is independent of the number of active cores; however, the Turbo Mode frequency is dynamic and dependent on the instantaneous application power load, the number of active cores, user configurable settings, operating environment, and system design. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

# 3.3 Chipset

The Mobile Intel® C240 Series Chipset provides extensive I/O support. Functions and capabilities include:

 PCI Express Base Specification, Revision 3.0
 ACPI Power Management Logic Support, Revision 4.0a
 Interrupt controller and timer functions
 Integrated Serial ATA host controller 3.2, supports data transfer rates up to 6Gb/s on all ports
 XHCI USB 3.1 Controller
 Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
 System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
 Support Intel® High Definition Audio
 Support Intel® Rapid Storage Technology
 Support Intel® Virtualization Technology for Directed I/O
 Integrated Clock Controller
 Analog and Digital Display ports
 Low Pin Count (LPC) Interface
 Firmware Hub (FWH) Interface Support
 Serial Peripheral Interface (SPI) Support

# 3.4 USB

The VPX3020 provides one USB 3.0 port to the P2 connector supporting data transfers up to 5Gb/s, and one USB 2.0 port to the P2 connector supporting data transfers up to 480 Mb/s.

# 3.5 SPI BIOS

The VPX3020 implements a dual BIOS feature. Each SPI flash has a capacity of 256Mb. When the main BIOS crashes, the backup BIOS will be used to boot the device.

# 3.6 System Management Bus

The PCH provides a System Management Bus (SMBus) Specification Version 2.0 compliant Host Controller as well as an SMBus Slave Interface. The PCH provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves) as well as I2C compatible devices.

# 3.7 Real Time Clock

The PCH contains a real-time clock with 256 bytes of battery-backed RAM. The internal RTC module provides two key functions: keeping the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal.

# 3.8 Serial ATA Controller

The VPX3020 has up to three SATA 6Gb/s ports capable of independent DMA operation. The SATA controller supports Intel® Rapid Storage Technology, providing both AHCI and integrated RAID functionality.

# 3.9 PCI Express Interface

The VPX3020 is compatible with the VPX ANSI/VITA 46.0-2007 standard and is equipped with an onboard PCIe Switch (PEX8725) to configure the PCIe bus and support the following configurations:

 Station 0 Downstream Ports: 2 x4
 Station 1 Downstream Port: 1 x4

The VPX3020 supports 1 x8 or 2 x4 PCIe bus to the XMC module.

# 3.10 Intel ® Gigibit Ethernet Controller I350

On the VPX-3020, the Intel® Ethernet Controller I350 offers one port 1000BASE-T and two ports 1000BASE-BX implementations using integrated PHYs.

# 3.11 Graphics

The VPX3020 provides one DisplayPort consisting of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal. The DisplayPort supports VESA DisplayPort 1.2 specifications.

# 3.12 GPIO Expander PCA9554

The VPX3020 offers 4x GPIO pins which are configurable as input or output signals, 3.3V tolerant, and SCI (GPE) and IOAPIC interrupt capable.

# 3.13 UART NCT5104

The NCT5104 is a LPC to UART IC, which supports 4 high-speed serial communication ports (UART). Each UART includes a 128-byte send/receive FIFO, a programmable baud rate generator, complete modem-control capability, and a processor interrupt system. The UART supports legacy speeds up to 115.2K bps as well as even higher baud rates of 230K, 460K, or 921K bps to support higher speed modems.

In addition to UART, the NCT5104D provides flexible I/O control functions through a set of general purpose I/O (GPIO) ports. These GPIO ports may serve as simple I/O ports or may be individually configured to provide alternative functions. The NCT5104D supports port 80 decode on the LPC bus and could output the signal via SOUTC. It also supports LED control.

# 3.14 TPM

The Infineon SLB 9665 TPM 2.0 is a fully standard compliant TPM based on the latest Trusted Computing Group (TCG) specification 2.0 and features Low Pin Count (LPC) interface.

# 3.15 XMC Site

The VPX3020 Series supports one XMC site for rear I/O expansion. The XMC site provides a x8 PCI Express Gen 3.0 lane. Jn2 rear XMC I/O connector is compliant to VITA 46.9, X8d+X12d.

# 4 VPX3020 Board Interfaces

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the VPX3020.

# 4.1 VPX3020 Board Layout

![DDR4 ECC Memory\nChipset\nXMC\nJ15\nGbE\nCPU\nPCIe Switch\nXMC\nJ16\nSATA Card\nConnector\nSuper IO\nP0\nP1\nP2](.vpx3020-50m-00050-1000-10/3e88b2b3c704c3b83ff7e571d8557a291f1622bd2d19552864c6952db80d0987.jpg)

Figure 4-1: VPX3020 Top Side Layout

![DDR4 ECC Memory\nTPM\nBMC\nBIOS1 SPI ROM\nBIOS2 SPI ROM\nIPMC](.vpx3020-50m-00050-1000-10/04f948f74c7e02c9e11033d5a1b4b0a3dc00b0d924ccd3eff1f324342d857e54.jpg)

Figure 4-2: VPX3020 Bottom Side Layout

# 4.2 VPX3020 Mechanical Dimensions

Conduction-Cooled Version
![This image displays a technical line drawing of a rectangular device, shown in two views. The top view presents a side profile with a vertical dimension labeled `(20.18)`. The larger, lower view shows the front face of the device, featuring a horizontal width dimension of `(160)` and a vertical height dimension of `(99.85)`. The face includes mounting screw locations (circles with crosses) along the top and bottom edges, as well as a vertical strip of small rectangles on the right side. At the bottom center, the text reads 'Dimensions in mm'.](.vpx3020-50m-00050-1000-10/4f7d2f9638ed35d61948360e966c5b61fffac77c3860ab5a57311e6cd50a48fa.jpg)
Figure 4-3: VPX3020 Conduction-Cooled Mechanical Dimensions

Air-Cooled Version
![The image is a technical engineering drawing of a rectangular mechanical component, likely a heatsink, displayed in three orthographic projections with dimensions labeled in millimeters.\n\n**Views and Dimensions:**\n*   **Top View (Top):** Displays the top profile of the object. On the right side, vertical dimensions measure the height of this view: `( 5.15 )` and `( 14.70 )`.\n*   **Front View (Center):** The largest view shows the front face with vertical fins, mounting holes, a connector, and a bracket.\n    *   Horizontal dimension at the bottom: `160`\n    *   Vertical dimension on the right: `99.85`\n*   **Left View (Left):** Shows the side profile.\n    *   Horizontal dimension at the top left: `21.29`\n\n**Text:**\n*   Centered at the bottom: 'Dimensions in mm'](.vpx3020-50m-00050-1000-10/659b6cf2b84da7ae09d50d111251bfc179109229c8522f2986392e91e8bb331a.jpg)
Figure 4-4: VPX3020 Air-Cooled Mechanical Dimensions

# 4.3 VPX3020 Connector Pin Assignments

XMC Connectors
![F1\nF19\nA1\nA19](.vpx3020-50m-00050-1000-10/c115eb61bc2f6ef92e97c3db7ffcc0c8462359101f950e1daef507b1854eed40.jpg)

JN15 Connector Pin Definition (Primary)

<table><tr><td>Pin</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>PET0p0</td><td>PET0n0</td><td>3.3V</td><td>PET0p1</td><td>PET0n1</td><td>VPWR</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>TRST#</td><td>GND</td><td>GND</td><td>RESET#</td></tr><tr><td>3</td><td>PET0p2</td><td>PET0n2</td><td>3.3V</td><td>PET0p3</td><td>PET0n3</td><td>VPWR</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>TCK</td><td>GND</td><td>GND</td><td>PULL UP</td></tr><tr><td>5</td><td>PET0p4</td><td>PET0n4</td><td>3.3V</td><td>PET0p5</td><td>PET0n5</td><td>VPWR</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>TMS</td><td>GND</td><td>GND</td><td>12V_AUX</td></tr><tr><td>7</td><td>PET0p6</td><td>PET0n6</td><td>3.3V</td><td>PET0p7</td><td>PET0n7</td><td>VPWR</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>TDI</td><td>GND</td><td>GND</td><td>-12V_AUX</td></tr><tr><td>9</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>NC</td><td>VPWR</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>TDO</td><td>GND</td><td>GND</td><td>GA0</td></tr><tr><td>11</td><td>PER0p0</td><td>PER0n0</td><td>MBIST#</td><td>PER0p1</td><td>PER0n1</td><td>VPWR</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>GA1</td><td>GND</td><td>GND</td><td>PRSNT#</td></tr><tr><td>13</td><td>PER0p2</td><td>PER0n2</td><td>3.3V_AUX</td><td>PER0p3</td><td>PER0n3</td><td>VPWR</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>GA2</td><td>GND</td><td>GND</td><td>MSDA</td></tr><tr><td>15</td><td>PER0p4</td><td>PER0n4</td><td>NC</td><td>PER0p5</td><td>PER0n5</td><td>VPWR</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>XMC_NVMRO</td><td>GND</td><td>GND</td><td>MSCL</td></tr><tr><td>17</td><td>PER0p6</td><td>PER0n6</td><td>NC</td><td>PER0p7</td><td>PER0n7</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>19</td><td>REF_CLK+</td><td>REF_CLK-</td><td>NC</td><td>WAKE#</td><td>NC</td><td>NC</td></tr></table>

![The image shows a white document icon with faint horizontal lines. A large, bold red checkmark is centered on the page.](.vpx3020-50m-00050-1000-10/fc94426312218f093406aefc813d8f2865dbbfd7d99b6ff1bb12ac6788844349.jpg)
NOTE:

The signal definitions of the primary XMC connector (J15) are presented relative to the XMC Mezzanine card.

J16 Connector Pin Definition (X8d+X12d)

<table><tr><td>Pin</td><td>A</td><td>B</td><td>C</td><td>D</td><td>E</td><td>F</td></tr><tr><td>1</td><td>XMC_A1+</td><td>XMC_B1-</td><td>NC</td><td>XMC_D1+</td><td>XMC_E1-</td><td>NC</td></tr><tr><td>2</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>3</td><td>XMC_A3+</td><td>XMC_B3-</td><td>NC</td><td>XMC_D3+</td><td>XMC_E3-</td><td>NC</td></tr><tr><td>4</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>5</td><td>XMC_A5+</td><td>XMC_B5-</td><td>NC</td><td>XMC_D5+</td><td>XMC_E5-</td><td>NC</td></tr><tr><td>6</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>7</td><td>XMC_A7+</td><td>XMC_B7-</td><td>NC</td><td>XMC_D7+</td><td>XMC_E7-</td><td>NC</td></tr><tr><td>8</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>9</td><td>XMC_A9+</td><td>XMC_B9-</td><td>NC</td><td>XMC_D9+</td><td>XMC_E9-</td><td>NC</td></tr><tr><td>10</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>11</td><td>XMC_A11+</td><td>XMC_B11-</td><td>NC</td><td>XMC_D11+</td><td>XMC_E11-</td><td>NC</td></tr><tr><td>12</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>13</td><td>XMC_A13+</td><td>XMC_B13-</td><td>NC</td><td>XMC_D13+</td><td>XMC_E13-</td><td>NC</td></tr><tr><td>14</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>15</td><td>XMC_A15+</td><td>XMC_B15-</td><td>NC</td><td>XMC_D15+</td><td>XMC_E15-</td><td>NC</td></tr><tr><td>16</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>17</td><td>XMC_A17+</td><td>XMC_B17-</td><td>NC</td><td>XMC_D17+</td><td>XMC_E17-</td><td>NC</td></tr><tr><td>18</td><td>GND</td><td>GND</td><td>NC</td><td>GND</td><td>GND</td><td>NC</td></tr><tr><td>19</td><td>XMC_A19+</td><td>XMC_B19-</td><td>NC</td><td>XMC_D19+</td><td>XMC_E19-</td><td>NC</td></tr></table>

# VPX Connectors

P0 Connector

<table><tr><td>Pin</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>12V</td><td>12V</td><td>12V</td><td>NC</td><td>3.3V</td><td>3.3V</td><td>3.3V</td></tr><tr><td>2</td><td>12V</td><td>12V</td><td>12V</td><td>NC</td><td>3.3V</td><td>3.3V</td><td>3.3V</td></tr><tr><td>3</td><td>5V</td><td>5V</td><td>5V</td><td>NC</td><td>5V</td><td>5V</td><td>5V</td></tr><tr><td>4</td><td>IPM1_CLK</td><td>IPM1_DAT</td><td>GND</td><td>N12V_AUX</td><td>GND</td><td>SYSRESET#</td><td>NVMRO</td></tr><tr><td>5</td><td>GAP</td><td>GA4</td><td>GND</td><td>3.3V_AUX</td><td>GND</td><td>IPM2_CLK</td><td>IPM2_DAT</td></tr><tr><td>6</td><td>GA3</td><td>GA2</td><td>GND</td><td>P12V_AUX</td><td>GND</td><td>GA1</td><td>GA0</td></tr><tr><td>7</td><td>IPMB_JTCK</td><td>GND</td><td>IPMB_JTDO</td><td>IPMB_JTDI</td><td>GND</td><td>IPMB_JTMS</td><td>IPMB_JTRST-L</td></tr><tr><td>8</td><td>GND</td><td>REF_CLK-</td><td>REF_CLK+</td><td>GND</td><td>H_CLK_P0_100M_N/RES_BUS-</td><td>H_CLK_P0_100M_P/RES_BUS+</td><td>GND</td></tr></table>

P1 Connector

<table><tr><td>Pin</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>GDISC1#</td><td>GND</td><td>L0-TX-</td><td>L0-TX+</td><td>GND</td><td>L0-RX-</td><td>L0-RX+</td></tr><tr><td>2</td><td>GND</td><td>L1-TX-</td><td>L1-TX+</td><td>GND</td><td>L1-RX-</td><td>L1-RX+</td><td>GND</td></tr><tr><td>3</td><td>P1_VBAT</td><td>GND</td><td>L2-TX-</td><td>L2-TX+</td><td>GND</td><td>L2-RX-</td><td>L2-RX+</td></tr><tr><td>4</td><td>GND</td><td>L3-TX-</td><td>L3-TX+</td><td>GND</td><td>L3-RX-</td><td>L3-RX+</td><td>GND</td></tr><tr><td>5</td><td>SYSCON#</td><td>GND</td><td>L4-TX-</td><td>L4-TX+</td><td>GND</td><td>L4-RX-</td><td>L4-RX+</td></tr><tr><td>6</td><td>GND</td><td>L5-TX-</td><td>L5-TX+</td><td>GND</td><td>L5-RX-</td><td>L5-RX+</td><td>GND</td></tr><tr><td>7</td><td>NC</td><td>GND</td><td>L6-TX-</td><td>L6-TX+</td><td>GND</td><td>L6-RX-</td><td>L6-RX+</td></tr><tr><td>8</td><td>GND</td><td>L7-TX-</td><td>L7-TX+</td><td>GND</td><td>L7-RX-</td><td>L7-RX+</td><td>GND</td></tr><tr><td>9</td><td>RTM_PWROK</td><td>GND</td><td>L8-TX-</td><td>L8-TX+</td><td>GND</td><td>L8-RX-</td><td>L8-RX+</td></tr><tr><td>10</td><td>GND</td><td>L9-TX-</td><td>L9-TX+</td><td>GND</td><td>L9-RX-</td><td>L9-RX+</td><td>GND</td></tr><tr><td>11</td><td>NC</td><td>GND</td><td>L10-TX-</td><td>L10-TX+</td><td>GND</td><td>L10-RX-</td><td>L10-RX+</td></tr><tr><td>12</td><td>GND</td><td>L11-TX-</td><td>L11-TX+</td><td>GND</td><td>L11-RX-</td><td>L11-RX+</td><td>GND</td></tr><tr><td>13</td><td>GPIO0</td><td>GND</td><td>ETH-T01B-</td><td>ETH-T01B+</td><td>GND</td><td>ETH-T01A-</td><td>ETH-T01A+</td></tr><tr><td>14</td><td>GND</td><td>ETH-T01D-</td><td>ETH-T01D+</td><td>GND</td><td>ETH-T-01C-</td><td>ETH-T01C+</td><td>GND</td></tr><tr><td>15</td><td>GPIO1/MASKABLE RESET</td><td>GND</td><td>BX-TX1-</td><td>BX-TX1+</td><td>GND</td><td>BX-RX1-</td><td>BX-RX1+</td></tr><tr><td>16</td><td>GND</td><td>BX-TX0-</td><td>BX-TX0+</td><td>GND</td><td>BX-RX0-</td><td>BX-RX0+</td><td>GND</td></tr></table>

# Signal Types:

1. PCIe Station 0: 2x PCIe x4 (L0-xx - L3-xx, L4-xx - L7-xx)
2. PCIe Station 1: 1x PCIe x4 (L8-xx - L11-xx)
3. 1000BASE-T: ETH-xx
4. 1000BASE-BX: BX-xx

P2 Connector

<table><tr><td>Pin</td><td>G</td><td>F</td><td>E</td><td>D</td><td>C</td><td>B</td><td>A</td></tr><tr><td>1</td><td>COM1_TXD $^{1}$ COM1_TX+ $^{2}$ </td><td>GND</td><td>DP_L1-</td><td>DP_L1+</td><td>GND</td><td>DP_L0-</td><td>DP_L0+</td></tr><tr><td>2</td><td>GND</td><td>DP_L3-</td><td>DP_L3+</td><td>GND</td><td>DP_L2-</td><td>DP_L2+</td><td>GND</td></tr><tr><td>3</td><td>COM1_RXD $^{1}$ COM1_RX+ $^{2}$ </td><td>GND</td><td>DP_CFG</td><td>DP_HPD</td><td>GND</td><td>DP_AUX-</td><td>DP_AUX+</td></tr><tr><td>4</td><td>GND</td><td>SATA3_TX-</td><td>SATA3_TX+</td><td>GND</td><td>SATA3_RX-</td><td>SATA3_RX+</td><td>GND</td></tr><tr><td>5</td><td>COM1_CTS# $^{1}$ COM1_RX- $^{2}$ </td><td>GND</td><td>USB3.0_3_TX-</td><td>USB3.0_3_TX+</td><td>GND</td><td>USB3.0_3_RX-</td><td>USB3.0_3_RX+</td></tr><tr><td>6</td><td>GND</td><td>P3V3_DP</td><td>P5V_USB1</td><td>GND</td><td>USB2.0_3_D-</td><td>USB2.0_3_D+</td><td>GND</td></tr><tr><td>7</td><td>COM1_RTS# $^{1}$ COM1_TX- $^{2}$ </td><td>GND</td><td>J16-A1</td><td>J16-B1</td><td>GND</td><td>J16-D1</td><td>J16-E1</td></tr><tr><td>8</td><td>GND</td><td>J16-A3</td><td>J16-B3</td><td>GND</td><td>J16-D3</td><td>J16-E3</td><td>GND</td></tr><tr><td>9</td><td>COM2_TXD $^{1}$ COM2_TX- $^{2}$ COM2_DATA- $^{3}$ </td><td>GND</td><td>J16-A11/PCIE1_TX0-</td><td>J16-B11/PCIE1_TX0+</td><td>GND</td><td>J16-D11/PCIE1_RX0-</td><td>J16-E11/PCIE1_RX0+</td></tr><tr><td>10</td><td>GND</td><td>J16-A13/PCIE1_TX1-</td><td>J16-B13/PCIE1_TX1+</td><td>GND</td><td>J16-D13/PCIE1_RX1-</td><td>J16-E13/PCIE1_RX1+</td><td>GND</td></tr><tr><td>11</td><td>COM2_RXD $^{1}$ COM2_RX+ $^{2}$ </td><td>GND</td><td>J16-A5/PCIE1_TX2-</td><td>J16-B5/PCIE1_TX2+</td><td>GND</td><td>J16-D5/PCIE1_RX2-</td><td>J16-E5/PCIE1_RX2+</td></tr><tr><td>12</td><td>GND</td><td>J16-A7/PCIE1_TX3-</td><td>J16-B7/PCIE1_TX3+</td><td>GND</td><td>J16-D7/PCIE1_RX3-</td><td>J16-E7/PCIE1_RX3+</td><td>GND</td></tr><tr><td>13</td><td>COM2_RTS# $^{1}$ COM2_TX- $^{2}$ COM2_DATA+ $^{3}$ </td><td>GND</td><td>J16-A9/PCIE2_TX0-</td><td>J16-B9/PCIE2_TX0+</td><td>GND</td><td>J16-D9/PCIE2_RX0-</td><td>J16-E9/PCIE2_RX0+</td></tr><tr><td>14</td><td>GND</td><td>J16-A15/PCIE2_TX1-</td><td>J16-B15/PCIE2_TX1+</td><td>GND</td><td>J16-D15/PCIE2_RX1-</td><td>J16-E15/PCIE2_RX1+</td><td>GND</td></tr><tr><td>15</td><td>COM2_CTS# $^{1}$ COM2_RX- $^{2}$ </td><td>GND</td><td>J16-A17/PCIE2_TX2-</td><td>J16-B17/PCIE2_TX2+</td><td>GND</td><td>J16-D17/PCIE2_RX2-</td><td>J16-E17/PCIE2_RX2+</td></tr><tr><td>16</td><td>GND</td><td>J16-A19/PCIE2_TX3-</td><td>J16-B19/PCIE2_TX3+</td><td>GND</td><td>J16-D19/PCIE2_RX3-</td><td>J16-E19/PCIE2_RX3+</td><td>GND</td></tr></table>

1RS-232; 2RS-422, 2RS-485

# Signal Types:

1. Display Port: DP\_xx
2. USB 3.0: USB3.0\_xx
3. USB 2.0: USB2.0\_xx
4. XMC x8d+x12d (XMC SKU): J16-xx
5. PCIe x4 (PCIe SKU): PCIE2\_xx

# 4.4 Status LEDs

![Reset Button\nSATA LED\nBIOS Select LED\nPower LED\nReset LED](.vpx3020-50m-00050-1000-10/b8d09ae0a3e38a106124a432dcca9aa4d9e4d875e6641eb05a43cdb4b1ec2e7d.jpg)

Figure 4-5: VPX3020 Front View

# Reset Button

Press this button to perform a hard system reset.

LEDs

<table><tr><td>Description</td><td>Indication</td></tr><tr><td>Power LED</td><td>Green: On when blade is receiving power</td></tr><tr><td>SATA LED</td><td>Yellow: Blinks when SATA is active</td></tr><tr><td>Reset LED</td><td>Lights for 1 seconds after system reset</td></tr><tr><td rowspan="3">BIOS Select LED</td><td>Green: BIOS1 working properly</td></tr><tr><td>Orange: BIOS2 working properly</td></tr><tr><td>Off: BIOS1 and BIOS2 failure</td></tr></table>

This page intentionally left blank.

# 5 VPX-R3020 RTM

This chapter illustrates the board layout, connector pin assignments, and jumper settings to familiarize users with the VPX-R3020 RTM.

5.1 Connector Allocation

<table><tr><td>Function</td><td>Rear</td><td>Top</td><td>RPx</td><td>Connector Type</td></tr><tr><td>DisplayPort</td><td>1</td><td>—</td><td>RP1</td><td>DisplayPort connector</td></tr><tr><td>2x SerDes-1000BASE-BX</td><td>—</td><td>1</td><td>RP1</td><td>InfiniBand 4X Latch vertical connector</td></tr><tr><td>1000BASE-T</td><td>—</td><td>2</td><td>RP1</td><td>Vertical RJ45 connector</td></tr><tr><td>SATA</td><td>—</td><td>2</td><td>RP1</td><td>7 Pin SATA connector</td></tr><tr><td>USB 3.0/2.0 (Front)</td><td>1</td><td></td><td>RP2</td><td>Type-A connector</td></tr><tr><td>COM0 (RS232/422)</td><td>—</td><td>1</td><td>RP1</td><td>DB-9 connector</td></tr><tr><td>COM2 (RS-232/422/485)</td><td>—</td><td>1</td><td>RP2</td><td>2x5 pin header</td></tr><tr><td>GPIO, 2-bit</td><td>—</td><td>1</td><td>RP1</td><td>2x3 pin header</td></tr><tr><td>JTAG</td><td>—</td><td>1</td><td>RP0</td><td>2x5 pin header</td></tr><tr><td>Reset button</td><td>—</td><td>1</td><td>RP0</td><td>Push button</td></tr><tr><td>IPMB</td><td>—</td><td>1</td><td>RP0</td><td>Wafer ML 1x5P D 1.25</td></tr><tr><td>Power Terminals</td><td>—</td><td>4</td><td>RP0</td><td>12V, 5V, 3.3V, GND</td></tr></table>

5.2 VPX-R3020 Block Diagram
![The diagram displays three primary blocks labeled **RP0**, **RP1**, and **RP2**, along with their associated connections:\n\n**RP0**\n*   VS1(DC12V)\n*   VS2(DC3V)\n*   VS3(DC5V)\n*   NVMRO, SYSRESET#\n*   JTAG\n*   SMBus\n\n**RP1**\n*   PCIe x8 3.0 ↔ PCIe x8\n*   PCIE x4 3.0 ↔ 2x PCIE x4\n*   1000BASE-BX ↔ 2x 1000BASE-BX port (SERDES optional)\n*   1000BASE-T ↔ 1x 1000BASE-T port\n*   USB 3.0/USB 2.0 ↔ 1x USB 3.0/USB 2.0 port\n*   RS-232/422 ↔ 1x RS-232/422 port\n*   GPIO 0-1 ↔ 2x GPIO port\n\n**RP2**\n*   RS-232/422/485 ↔ 1x RS-232/422/485 port\n*   PCIe x4 3.0 ↔ PCIe x4 slot\n*   PCIe x4 3.0 ↔ PCIe x4 slot](.vpx3020-50m-00050-1000-10/9fbce942c8a4c449103b0d833f9f69a2628981500ead38e734e8dbcbccb1b293.jpg)

Figure 5-1: VPX-R3020 RTM Functional Block Diagram

# 5.3 VPX-R3020 RTM Board Layout

![Board-to-Board Connector\nJTAG\nCOM2 Header\nRP0\nGPIO Header\nCOM1 DB-9\nIPMB Connector\nRP1\nDisplayPort\nSATA Connector\nRP2\nUSB Port\n1000BASE-T\n12V 5V GND 3.3V 1000BASE-BX Connector](.vpx3020-50m-00050-1000-10/a9e05ae2641bfe71fe5d599e31c4a83fa054a65b566950ec258e0d2724bd9707.jpg)

Figure 5-2: VPX-R3020 RTM Board Layout

# 5.4 VPX-R3020 RTM Connector Pin Assignments

# Rear I/O Connectors

DisplayPort Connector

<table><tr><td>Pin #</td><td>Signal</td><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>CN_DP0_P</td><td>2</td><td>Ground</td></tr><tr><td>3</td><td>CN_DP0_N</td><td>4</td><td>CN_DP1_P</td></tr><tr><td>5</td><td>Ground</td><td>6</td><td>CN_DP1_N</td></tr><tr><td>7</td><td>CN_DP2_P</td><td>8</td><td>Ground</td></tr><tr><td>9</td><td>CN_DP2_N</td><td>10</td><td>CN_DP3_P</td></tr><tr><td>11</td><td>Ground</td><td>12</td><td>CN_DP3_N</td></tr><tr><td>13</td><td>CN_CAD-L</td><td>14</td><td>CN_CEC</td></tr><tr><td>15</td><td>CN_AUX_P</td><td>16</td><td>Ground</td></tr><tr><td>17</td><td>CN_AUX_N</td><td>18</td><td>DDP_HPD</td></tr><tr><td>19</td><td>Ground</td><td>20</td><td>P3V3</td></tr></table>

![1\n2\n19\n20](.vpx3020-50m-00050-1000-10/db68e549bfec7ad3a106d7082ccc106859174b343dc992a2cb98a462aa6c37b9.jpg)

USB 3.0 Connectors

<table><tr><td>Pin #</td><td>Signal Name</td></tr><tr><td>1</td><td>USB3.0_P5VA</td></tr><tr><td>2</td><td>USB2_CMAN</td></tr><tr><td>3</td><td>USB2_CMAP</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>USB3A_CMRXN</td></tr><tr><td>6</td><td>USB3A_CMRXP</td></tr><tr><td>7</td><td>GND</td></tr><tr><td>8</td><td>USB3A_CMTXN</td></tr><tr><td>9</td><td>USB3A_CMTXP</td></tr></table>

![1\n2\n3\n4\n5\n6\n7\n8\n9](.vpx3020-50m-00050-1000-10/1182d39f26f40ee24aa31d62a850f21194c1b8d31f143f2f1252aef5639bc36b.jpg)

COM1 Connector (DB-9)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422</td></tr><tr><td>1</td><td>NC</td><td>—</td></tr><tr><td>2</td><td>COM1_RXD</td><td>COM1_RX+</td></tr><tr><td>3</td><td>COM1_TXD</td><td>COM1_TX+</td></tr><tr><td>4</td><td>NC</td><td>—</td></tr><tr><td>5</td><td>GND</td><td>GND</td></tr><tr><td>6</td><td>NC</td><td>—</td></tr><tr><td>7</td><td>COM1_RTS#</td><td>COM1_TX-</td></tr><tr><td>8</td><td>COM1_CTS#</td><td>COM1_RX-</td></tr><tr><td>9</td><td>NC</td><td>—</td></tr></table>

![6\n1\n5](.vpx3020-50m-00050-1000-10/449cfa15ad97303ea22583505fa816f54c781c3cbcc26cb57daffbdee863736f.jpg)

![The image shows a white document icon with a folded top-right corner and faint horizontal lines, overlaid with a large red checkmark.](.vpx3020-50m-00050-1000-10/29deb6f64d568578923d6fb5dab105b9d7f6d62110da8b1c2cd27a8067ce7de7.jpg)
NOTE:

COM1 mode by BIOS setting.

# Onboard Connectors

2x SerDes-1000BASE-BX Connector

<table><tr><td>Pin</td><td>Signal</td><td>Pin</td><td>Signal</td></tr><tr><td>S1</td><td>SER0_P</td><td>S14</td><td>SET1_P</td></tr><tr><td>S2</td><td>SER0_N</td><td>S15</td><td>SET0_N</td></tr><tr><td>S3</td><td>SER1_P</td><td>S16</td><td>SET0_P</td></tr><tr><td>S4</td><td>SER1_N</td><td>G1</td><td>GND</td></tr><tr><td>S5</td><td>NC</td><td>G2</td><td>GND</td></tr><tr><td>S6</td><td>NC</td><td>G3</td><td>GND</td></tr><tr><td>S7</td><td>NC</td><td>G4</td><td>GND</td></tr><tr><td>S8</td><td>NC</td><td>G5</td><td>GND</td></tr><tr><td>S9</td><td>NC</td><td>G6</td><td>GND</td></tr><tr><td>S10</td><td>NC</td><td>G7</td><td>GND</td></tr><tr><td>S11</td><td>NC</td><td>G8</td><td>GND</td></tr><tr><td>S12</td><td>NC</td><td>G9</td><td>GND</td></tr><tr><td>S13</td><td>SET1_N</td><td></td><td></td></tr></table>

![12±0.2\n9±0.15\nS16\nG9\nS15\nMagnetic/Inductors\n13.28±0.15\n25.7±0.25\n17.05±0.15\n0.75±0.05\nGround contact\nS1\nEMIC\nG1\nS2](.vpx3020-50m-00050-1000-10/7dbc139edcf67966bf7d397765ded809e38bc84ab47473f2d82bdac41c8e444e.jpg)

1000BASE-T (RJ-45)

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>MX0+</td></tr><tr><td>2</td><td>MX0-</td></tr><tr><td>3</td><td>MX1+</td></tr><tr><td>4</td><td>MX2+</td></tr><tr><td>5</td><td>MX2-</td></tr><tr><td>6</td><td>MX1-</td></tr><tr><td>7</td><td>MX3+</td></tr><tr><td>8</td><td>MX3-</td></tr></table>

![The image displays a schematic diagram of a connector, resembling a modular phone jack or similar plug, enclosed within a square border. Two black lines extend downward from the bottom corners of the central connector shape. The left line points to the number **8**, and the right line points to the number **1**.](.vpx3020-50m-00050-1000-10/c139c4d57d6a89c7be7bcefdf1e69addb66a160008c94a5bc0205d0b01469ebd.jpg)

RS-232/422/485 Header (COM2)

<table><tr><td>Pin #</td><td>RS-232</td><td>RS-422/485 full duplex</td><td>RS-485 half duplex</td></tr><tr><td>1</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>2</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>3</td><td>COM2_RXD</td><td>COM2_RX+</td><td>NC</td></tr><tr><td>4</td><td>COM2_RTS#</td><td>COM2_TX+</td><td>COM2_DATA+</td></tr><tr><td>5</td><td>COM2_TXD</td><td>COM2_TX-</td><td>COM2_DATA-</td></tr><tr><td>6</td><td>COM2_CTS#</td><td>COM2_RX-</td><td>NC</td></tr><tr><td>7</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>8</td><td>NC</td><td>NC</td><td>NC</td></tr><tr><td>9</td><td>GND</td><td>GND</td><td>GND</td></tr><tr><td>10</td><td>NC</td><td>NC</td><td>NC</td></tr></table>

![1\n□ □\n□ □\n□ □\n□ □\n□ □\n9\n□ □\n2\n10](.vpx3020-50m-00050-1000-10/d0a542357774268defbfc17f0e012c3755d98e3aeef46911b357618c653481d2.jpg)

![The image shows a white document icon with a folded top-left corner. Faint horizontal lines appear across the page, simulating text. A large, thick red checkmark is superimposed over the center of the document.](.vpx3020-50m-00050-1000-10/70b5d8e36bc95777067361337dab3a6a1f687305fd5740bdbe30857686b45e67.jpg)
NOTE:

COM2 mode by BIOS setting.

JTAG Header

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TCK</td></tr><tr><td>3</td><td>NC</td></tr><tr><td>4</td><td>TDO</td></tr><tr><td>5</td><td>+3.3V</td></tr><tr><td>6</td><td>TMS</td></tr><tr><td>7</td><td>TRST</td></tr><tr><td>8</td><td>+3.3V</td></tr><tr><td>9</td><td>GND</td></tr><tr><td>10</td><td>TDI</td></tr></table>

![2\n1](.vpx3020-50m-00050-1000-10/fde6008efc217d191b2f4294c83d469495895c3422b8d0204b84e0c5bcf8afd9.jpg)

# SATA Connectors

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GND</td></tr><tr><td>2</td><td>TXP</td></tr><tr><td>3</td><td>TXN</td></tr><tr><td>4</td><td>GND</td></tr><tr><td>5</td><td>RXN</td></tr><tr><td>6</td><td>RXP</td></tr><tr><td>7</td><td>GND</td></tr></table>

![1\n2\n3\n4\n5\n6\n7](.vpx3020-50m-00050-1000-10/77a734009f9c415e1c1a0130039bdecbe6d414def7306babbe056ec587e8bd6d.jpg)

# IPMB Connector

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>IPMB_SDA</td></tr><tr><td>2</td><td>GND</td></tr><tr><td>3</td><td>IPMB_SCL</td></tr><tr><td>4</td><td>+5V</td></tr><tr><td>5</td><td>+5V</td></tr></table>

![5\n4\n3\n2\n1](.vpx3020-50m-00050-1000-10/cefde3ff8c37368687478ca5773cf2a9a781a5e876bb369f383ea880a224c264.jpg)

# GPIO Header

<table><tr><td>Pin #</td><td>Signal</td></tr><tr><td>1</td><td>GPIO0</td></tr><tr><td>2</td><td>GPIO1</td></tr><tr><td>3</td><td>NC</td></tr><tr><td>4</td><td>NC</td></tr><tr><td>5</td><td>NC</td></tr><tr><td>6</td><td>NC</td></tr></table>

![The image features the number 2 on the left and the number 1 on the right. Between them is a vertical stack of three identical shapes. Each shape is a rounded rectangle containing two small squares arranged side-by-side.](.vpx3020-50m-00050-1000-10/2114cd6b219a78e9df52f7540e13232b8507f4721f72a45aa36aa6457cf4b4be.jpg)

# 6 Getting Started

This chapter describes the installation of the following components to the VPX3020 and rear transition modules:

 VPX Blade installation to chassis
 RTM installation to chassis

# 6.1 Installing the VPX3020 to the Chassis

These instructions are for reference only. Refer to the user guide that comes with the chassis for more information.

1. Be sure to select the system slot to install the blade. The system power may now be powered on or off.
2. Align the module's top and bottom edges to the chassis card guides, and then carefully slide the module into the chassis. A slight resistance may be felt when inserting the module. If the resistance it too strong, check if there are wedge lock screwed or if the board's connector pins are not properly aligned with connectors on the backplane. Then push the board until it is completely flush with the chassis.
3. Ensure the module in place, and then screw the wedge lock on the module

# 6.2 Installing the VPX-R3020 to the Chassis

The installation and removal procedures for a RTM are the same as those for VPX boards. Because they are shorter than front boards, pay careful attention when inserting or removing RTMs.

Refer to previous sections for peripheral connectivity of all I/O ports on the RTM. When installing the VPX3020 Series and related RTMs, make sure the RTM is the correct matching model.

# 6.3 Driver Installation

The VPX3020 drivers are available from the ADLINK website (www.adlinktech.com). ADLINK provides validated drivers for Windows 7. We recommend using the drivers provided on the ADLINK website to ensure compatibility. VxWorks BSPs can also be downloaded from the VPX3020 product page.

Detailed driver info TBD.

# 7 Utilities

# 7.1 Watchdog Timer

This section describes the operation of the VPX3020’s watchdog timer (WDT). The primary function of the WDT is to monitor the VPX3020's operation and to reset the system if a software application fails to function as programmed. The following WDT functions may be controlled using a software application:

 enabling and disabling
 set and get current configuration
 reloading timeout value

The VPX3020 custom WDT circuit is implemented using the IPMC and operated by IPMI commands.

# Watchdog Timer IPMI Commands

The following section describes the IPMI commands for controlling watchdog timer (WDT) functions. For more details about IPMI commands, please refer to the IPMI specification: “Intelligent Platform Management Interface Specification Second Generation $V 2 . 0 ^ { \prime \prime }$ .

WDT Command Table

<table><tr><td>Command</td><td>NetFn Code</td><td>Cmd Code</td></tr><tr><td>Reset Watchdog Timer</td><td>App (06h)</td><td>22h</td></tr><tr><td>Set Watchdog Timer</td><td>App (06h)</td><td>24h</td></tr><tr><td>Get Watchdog Timer</td><td>App (06h)</td><td>25h</td></tr></table>

The WDT IPMI commands allow the user to set the countdown period and reload the timeout value periodically to keep it from resetting the system. If the timer countdown value is not reloaded, the watchdog resets the system hardware after its counter reaches zero.

# Reset Watchdog Timer

This command is used to reload the WDT.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>18h</td><td>NetFn/LUN</td></tr><tr><td>1</td><td>22h</td><td>Defined command</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# Set Watchdog Timer:

This command is used to set the parameters of the WDT.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="4">Request</td><td>0</td><td>18h</td><td>NetFn/LUN</td></tr><tr><td>1</td><td>24h</td><td>Defined command</td></tr><tr><td>2</td><td>[7] - 1b = don't log[6] - 1b = don't stop timer[5:3] - reserved[2:0] - timer use000b = reserved001b = BIOS FRB2010b = BIOS/POST011b = OS Load100b = SMS/OS101b = OEM110b -111b = reserved</td><td>Timer Use</td></tr><tr><td>3</td><td>[7] - reserved[6:4] - pre-timeout interrupt000b = none001b = SMI (optional)010b = NMI / Diagnostic Interrupt (optional)011b = Messaging Interrupt100b,111b = reserved[3] - reserved[2:0] - timeout action000b = no action001b = Hard Reset010b = Power Down011b = Power Cycle100b,111b = reserved</td><td>Timer Actions</td></tr><tr><td rowspan="4">Request</td><td>4</td><td>1h~ffh ('1h' based.)</td><td>Pre-timeout interval in seconds.</td></tr><tr><td>5</td><td>[7] - reserved[6] - reserved[5] - OEM[4] - SMS/OS[3] - OS Load[2] - BIOS/POST[1] - BIOS FRB2[0] - reserved0b = leave alone1b = clear timer use expiration bit</td><td>Timer Use Expiration flags clear</td></tr><tr><td>6</td><td>00h~ffh, LS byte (100 ms/count)</td><td>Initial countdown value</td></tr><tr><td>7</td><td>00h~ffh, MS byte (100 ms/count)</td><td>Initial countdown value</td></tr><tr><td>Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr></table>

# Get Watchdog Timer

This command is used to get the current configuration in WDT.

<table><tr><td>Action</td><td>Byte</td><td>Value</td><td>Description</td></tr><tr><td rowspan="2">Request</td><td>0</td><td>18h</td><td>NetFn/LUN</td></tr><tr><td>1</td><td>25h</td><td>Defined command</td></tr><tr><td rowspan="2">Response</td><td>0</td><td>Complete Code</td><td>00h means OK</td></tr><tr><td>1</td><td>[7] - 1b = don't log[6] - 1b = don't stop timer[5:3] - reserved[2:0] - timer use000b = reserved001b = BIOS FRB2010b = BIOS/POST011b = OS Load100b = SMS/OS101b = OEM110b -111b = reserved</td><td>Timer Use</td></tr><tr><td rowspan="7">Response</td><td>2</td><td>[7] - reserved[6:4] - pre-timeout interrupt000b = none001b = SMI (optional)010b = NMI / Diagnostic Interrupt (optional)011b = Messaging Interrupt100b,111b = reserved[3] - reserved[2:0] - timeout action000b = no action001b = Hard Reset010b = Power Down011b = Power Cycle100b,111b = reserved</td><td>Timer Actions</td></tr><tr><td>3</td><td>1h~ffh (‘1h’ based.)</td><td>Pre-timeout interval in seconds.</td></tr><tr><td>4</td><td>[7] - reserved[6] - reserved[5] - OEM[4] - SMS/OS[3] - OS Load[2] - BIOS/POST[1] - BIOS FRB2[0] - reserved0b = leave alone1b = clear timer use expiration bit</td><td>Timer Use Expiration flags clear</td></tr><tr><td>5</td><td>00h~ffh, LS byte (100 ms/count)</td><td>Initial countdown value</td></tr><tr><td>6</td><td>00h~ffh, MS byte (100 ms/count)</td><td>Initial countdown value</td></tr><tr><td>7</td><td>00h~ffh, LS byte (100 ms/count)</td><td>Present countdown value</td></tr><tr><td>8</td><td>00h~ffh, MS byte (100 ms/count)</td><td>Present countdown value</td></tr></table>

# Example of WDT Process

The sample program written in C shown below offers an interactive way to test the Watchdog Timer under DOS.

# Configure WDT Parameters

```txt
0x40 : Don't stop timer.
0x01 : Hard Reset.
0x01 : Pre-timeout interval in 1 second.
0x08 : Timer Use Expiration flags clear by OS Load.
0x50 : 80 count. 100ms * 80 = 8000ms = 8 seconds.
```

```json
[18 00 24 40 01 01 08 50 00]
```

# Reset WDT

```json
[18 00 22]
```

![The image shows a white document icon with the top right corner folded. Faint grey horizontal lines appear on the lower portion of the page, and a large, bold red checkmark is superimposed over the center of the document.](.vpx3020-50m-00050-1000-10/0ba41e75eb253e8770ccd14c60f9042afe63f2cac744048b3091114ef033c7d1.jpg)
NOTE:

After setting a new configuration, the Reset WDT command must be sent. Then the WDT will be activated.

This page intentionally left blank.

# 8 BIOS Setup

The following chapter describes basic navigation for the AMIBIOS®8 BIOS setup utility.

# 8.1 Starting the BIOS

To enter the setup screen, follow these steps:

1. Power on the motherboard
2. Press the &lt; Delete &gt; key on your keyboard when you see the following text prompt: &lt; Press DEL to run Setup &gt;
3. After you press the &lt; Delete &gt; key, the main BIOS setup menu displays. You can access the other setup screens from the main BIOS setup menu.

![The image displays a white document icon with a folded top-right corner and a black outline. Inside, there are several horizontal black lines. A large, bold red checkmark is superimposed over the center of the document.](.vpx3020-50m-00050-1000-10/96dc06f976c405a148b84172473a0a04da9b3a97235b35bc1fc84ed1e39a72da.jpg)
NOTE:

In most cases, the &lt; Delete &gt; key is used to invoke the setup screen. There are several cases that use other keys, such as &lt; F1 &gt;, &lt; F2 &gt;, and so on.

# Setup Menu

The main BIOS setup menu is the first screen that you can navigate. Each main BIOS setup menu option is described in this user’s guide.

The Main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed” options cannot be configured, “Blue” options can be.

The right frame displays the key legend. Above the key legend is an area reserved for a text message. When an option is selected in the left frame, it is highlighted in white. Often a text message will accompany it.

# Navigation

The BIOS setup/utility uses a key-based navigation system called hot keys. Most of the BIOS setup utility hot keys can be used at any time during the setup navigation process.

![**Labeled Blocks:**\n*   BIOS Setup Utility\n*   Screens\n*   Left and Right Keys to Select a Setup Screen\n*   Screen 1\n*   Screen 2\n*   Screen 3\n*   Screen 4\n*   Screen 5\n*   Items\n*   Tab Key to Select Fields\n*   ± To Change Field Values\n*   Fields\n*   Up and Down Keys to Select a Setup Item\n\n**Connections:**\n*   A downward arrow connects 'BIOS Setup Utility' to 'Screens'.\n*   A dotted downward arrow connects 'Left and Right Keys to Select a Setup Screen' to the row of screens below.\n*   Double-headed horizontal arrows connect 'Screen 1', 'Screen 2', 'Screen 3', 'Screen 4', and 'Screen 5' in a sequence.\n*   A downward arrow connects 'Screens' to 'Items'.\n*   A dotted arrow connects 'Tab Key to Select Fields' to the top row of boxes containing '±'.\n*   A dotted arrow connects '± To Change Field Values' to the top row of boxes containing '±'.\n*   Double-headed horizontal arrows connect the three boxes containing '±' in the top row of the bottom section.\n*   A downward arrow connects 'Items' to the top row of boxes containing '±'.\n*   A downward arrow and an upward arrow are situated between the top and bottom rows of '±' boxes.\n*   Double-headed horizontal arrows connect the three boxes containing '±' in the bottom row.\n*   A bracket labeled 'Fields' points to the left side of the bottom section (encompassing both rows of '±' boxes).\n*   A dotted arrow connects 'Up and Down Keys to Select a Setup Item' to the upward arrow.](.vpx3020-50m-00050-1000-10/8149905501f6df63989891b72dc432eac3254f92fddd43adedf812f993703743.jpg)

![The image displays a white sheet of paper with a folded upper-right corner and faint horizontal grey lines representing text. A large, thick red checkmark is drawn diagonally across the center of the document.](.vpx3020-50m-00050-1000-10/8e01bb4d2a7b4201e052f49feec665b69826390b1c6ef5f794c2161923363f24.jpg)
NOTE:

There is a hot key legend located in the right frame on most setup screens.

![The image displays two black horizontal arrows pointing inward toward each other. The arrow on the left points to the right, and the arrow on the right points to the left. Their arrowheads are positioned close together in the center.](.vpx3020-50m-00050-1000-10/e7bb32992eebbedfb7a16834ef486b5036ad62a82ed547491308b0b977e961c8.jpg)

Left/Right. The Left and Right &lt; Arrow &gt; keys allow you to select a setup screen. For example: Main screen, Advanced screen, Chipset screen, and so on.

![The image displays two black arrows arranged horizontally. The arrow on the left points upward, while the arrow on the right points downward.](.vpx3020-50m-00050-1000-10/712a5b7e662d4a18b8b205dafbf8608afb10ba251f4c6571bc7216c81ed9caaa.jpg)

Up/Down The Up and Down &lt; Arrow &gt; keys allow you to select a setup item or sub-screen.

![The image displays a black plus sign (+) followed by a space and a black minus sign (-).](.vpx3020-50m-00050-1000-10/e5760baa4439ab3f320326fc631cd227f8d9108ac7cfd869c331746e393e57df.jpg)

Plus/Minus The Plus and Minus &lt; Arrow &gt; keys allow you to change the field value of a particular setup item. For example: Date and Time.

![The image displays the word 'Tab' in a bold, black, sans-serif typeface centered on a white background.](.vpx3020-50m-00050-1000-10/36fa6996f61d450f36633ff3aa17a19522e42d991911e0b9ae2110d6cbfc2c0f.jpg)

The &lt; Tab &gt; key allows you to select setup fields.

![The image displays the capital letters 'ESC' in a bold, black, sans-serif font against a white background. A vertical black line is visible to the immediate left of the letter 'E'.](.vpx3020-50m-00050-1000-10/91ff7e10076e98f8fa8641ff21c8f7b9ba612a7be43d84744c561086435daed6.jpg)

The &lt; Esc &gt; key allows you to discard any changes you have made and exit the Setup. Press the &lt; Esc &gt; key to exit the setup without saving your changes. Press the &lt; Enter &gt; key to discard changes and exit. You can also use the &lt; Arrow &gt; key to select Cancel and then press the &lt; Enter &gt; key to abort this function and return to the previous screen.

# 8.2 Main Setup Menu

When you first enter the Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The Main BIOS Setup menu is shown below.

<table><tr><td>Main</td><td>Advanced</td><td>Server Mgmt</td><td>Chipset</td><td>Security</td><td>Boot</td><td>Save &amp; Exit</td></tr><tr><td>- BIOS Information- System Information- Board Information- System Date- System Time</td><td>- CPU ▶Configuration- Power ▶Management- USB ▶Configuration- CSM ▶Configuration- Super IO ▶Configuration- COM Port Configuration▶- Serial Console Redirection ▶- Trusted ▶Computing- VPX3020 ▶Configuration- Network Stack Configuration ▶</td><td>- BMC Information</td><td>- PCIe Scan Delay- System Agent (SA) ▶Configuration- PCI-IO ▶Configuraiton</td><td>- Password ▶Description- Secure Boot Menu ▶- HDD Security Configuration ▶</td><td>- Boot ▶Configuration</td><td>- Save Changes and Exit- Save options- Boot Override</td></tr></table>

![The image displays a graphic of a white sheet of paper with horizontal grey lines, resembling a document or checklist. A large, bold red checkmark is superimposed over the center of the paper, slanting upwards from left to right. The top left corner of the paper is slightly curved. There is no text present in the image.](.vpx3020-50m-00050-1000-10/a6587130a9024e209d5872fa1764d6d17d757efbae43bbc3c6905a2170abdc3f.jpg)
NOTE:

► indicates a submenu Gray text indicates info only

# 8.2.1 Main Setup

BIOS Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BIOS Vendor</td><td>Info only</td><td>BIOS Vendor</td></tr><tr><td>BIOS Version</td><td>Info only</td><td>Display BIOS version</td></tr><tr><td>Build Date</td><td>Info only</td><td>Display BIOS build Date</td></tr><tr><td>MCR Version</td><td>Info only</td><td>Display Memory Reference Code</td></tr><tr><td>GOP Version</td><td>Info only</td><td>Display GOP version</td></tr><tr><td>ME FW Version</td><td>Info only</td><td>Display ME Firmware version</td></tr><tr><td>SPI ROM Order</td><td>Info only</td><td>Display Bootup BIOS ROM Number</td></tr></table>

System Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Project Version</td><td>Info only</td><td>Display ADLINK project name</td></tr><tr><td>CPU Board Version</td><td>Info only</td><td>Display CPU board version</td></tr><tr><td>CPU Board String</td><td>Info only</td><td>Display the CPU model name</td></tr><tr><td>CPU Stepping</td><td>Info only</td><td>Display CPU Stepping.</td></tr><tr><td>GT Info</td><td>Info only</td><td>Display GT info of Intel Graphics.</td></tr><tr><td>CPU Frequency</td><td>Info only</td><td>Display CPU frequency</td></tr><tr><td>Total Memory</td><td>Info only</td><td>Display installed memory size.</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency</td></tr><tr><td>PCH SKU</td><td>Info only</td><td>Display chipset brand name</td></tr><tr><td>PCH Stepping</td><td>Info only</td><td>Display PCH Stepping.</td></tr></table>

Board Information

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Serial Number</td><td>Info only</td><td>Display board serial number</td></tr><tr><td>Manufacturing Date</td><td>Info only</td><td>Display manufacturing date</td></tr></table>

# 8.3 Advanced

This menu contains the settings for most of the user interfaces in the system.

8.3.1 CPU Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Type</td><td>Info only</td><td>Manufacturer, model, speed</td></tr><tr><td>Package</td><td>Info only</td><td>Display CPU package</td></tr><tr><td>CPU Stepping</td><td>Info only</td><td>Display CPU stepping</td></tr><tr><td>Number of Processors</td><td>Info only</td><td>Display number of processors</td></tr><tr><td>ID</td><td>Info only</td><td>Display CPU ID</td></tr><tr><td>Microcode Revision</td><td>Info only</td><td>Display Microcode Patch.</td></tr><tr><td>CPU Speed</td><td>Info only</td><td>Display CPU Speed.</td></tr><tr><td>L1 Data Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L1 Code Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L2 Cache</td><td>Info only</td><td>Display cache info.</td></tr><tr><td>L3 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>L4 Cache</td><td>Inf o only</td><td>Display cache info.</td></tr><tr><td>VMX</td><td>Info only</td><td>Display Intel VMX Technology support or not</td></tr><tr><td>Intel SMX Technology</td><td>Info only</td><td>Display Intel SMX Technology support or not.</td></tr><tr><td>CPU Flex Ratio</td><td>Disabled Enabled</td><td>Enable/Disable CPU Flex Ratio Programming</td></tr><tr><td>Boot performance mode</td><td>Max Battery Max Non-Turbo Performance Trubo Performance</td><td>Select the performance state that the BIOS will set starting from reset vector.</td></tr><tr><td>Hyper-threading</td><td>Disabled Enabled</td><td>Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only one thread per enabled core is enabled.</td></tr><tr><td>Intel(R) SpeedStep(TM)</td><td>Disabled Enabled</td><td>Allows more than two frequency ranges to be supported.</td></tr><tr><td>Intel(R) Speed Shift Technology</td><td>Disabled Enabled</td><td>Enable/Disable Intel® Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states.</td></tr><tr><td>Turbo Mode</td><td>DisabledEnabled</td><td>Enable/Disable turbo mode.</td></tr><tr><td>Configurable TDP Boot Mode</td><td>NominalDeactivate</td><td>Configure TDP Mode as Nominal/Down/Disabled. Disabled option will set MSR to Nominal and MMIO to Zero.</td></tr><tr><td>Platform PL1 Enable</td><td>DisabledEnabled</td><td>Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given</td></tr><tr><td>C States</td><td>DisabledEnabled</td><td>Enable/Disable CPU Power Management. Allow CPU to go to C states when it's not 100% utilized.</td></tr><tr><td>Package C State limit</td><td>AutoCPU DefaultC10C9C8C7SC7C6C3C2C0/C1</td><td>Package C State limit</td></tr><tr><td>Active Processor Cores</td><td>All123</td><td>Number of cores to enable in each processor package.</td></tr><tr><td>VT-d</td><td>DisabledEnabled</td><td>VT-d capability</td></tr></table>

8.3.2 Power Management

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Enable ACPI Auto</td><td>DisabledEnabled</td><td>Enables or Disables BIOS ACPI Auto Configuration.</td></tr><tr><td>Enable Hibernation</td><td>DisabledEnabled</td><td>Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This option may not be effective with some operating systems.</td></tr><tr><td>ACPI Sleep State</td><td>Suspend Disabled S3 (Suspend to RAM)</td><td>Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.</td></tr></table>

# 8.3.3 USB Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>XHCI Disable Compliance Mode</td><td>Disabled Enabled</td><td>Option to enable Compliance Mode. Default is to disable Compliance Mode. Change to enabled for Compliance Mode testing.</td></tr><tr><td>XDCI Support</td><td>Disabled Enabled</td><td>Enable/Disable XDCI (USB OTG Device)</td></tr><tr><td>USB Port Disable Override</td><td>Disabled Select Per-Pin</td><td>Selectively Enable/Disable the corresponding USB port from reporting a Device Connection to the controller.</td></tr></table>

# 8.3.4 CSM Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>CSM Support</td><td>EnabledDisable</td><td>This option controls if CSM will be launched.</td></tr><tr><td>CSM16 Module Version</td><td>Info only</td><td></td></tr><tr><td>GateA20 Active</td><td>Upon RequestAlways</td><td>Upon Request: GA20 can be disabled using BIOS services. Always: do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.</td></tr><tr><td>Boot Option filter</td><td>UEFI and LegacyLegacy onlyUEFI only</td><td>This option controls what devices system can to boot.</td></tr><tr><td>Option ROM execution</td><td>Info only</td><td></td></tr><tr><td>Network</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and Legacy PXE OpROM.</td></tr><tr><td>Storage</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and Legacy Storage OpROM.</td></tr><tr><td>Video</td><td>Do not launchUEFI onlyLegacy only</td><td>Controls the execution of UEFI and Legacy Video OpROM.</td></tr><tr><td>Other PCI devices</td><td>Do not launchUEFILegacy OpROM</td><td>For PCI devices other than Network, Mass storage or Video defines which OpROM to launch.</td></tr></table>

# 8.3.5 Super IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>NCT5104D Super IO Configuration</td><td>Info only</td><td></td></tr><tr><td>Serial Port 1(COM3)Configuration Serial PortDevice SettingsChange Settings</td><td>EnabledDisabledIO=3F8h;IRQ=4AutoIO=3F8h;IRQ=4IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 2(COM1)Configuration Serial PortDevice SettingsChange Settings</td><td>EnabledDisabledIO=2F8h;IRQ=5AutoIO=2F8h;IRQ=3IO=3F8h;IRQ=3,4,5,6,7,9,10,11,12IO=2F8h;IRQ=3,4,5,6,7,9,10,11,12IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4.5,6,7,9,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 3(COM4)Configuration Serial PortDevice SettingsChange Settings</td><td>EnabledDisabledIO=3E8h;IRQ=3AutoIO=3E8h;IRQ=7IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12IO=220h;IRQ=3,4,5,6,7,9,10,11,12IO=228h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr><tr><td>Serial Port 4(COM2)Configuration Serial PortDevice SettingsChange Settings</td><td>EnabledDisabledIO=2E8h;IRQ=10AutoIO=2E8h;IRQ=7IO=3E8h;IRQ=3,4,5,6,7,9,10,11,12IO=2E8h;IRQ=3,4,5,6,7,9,10,11,12IO=220h;IRQ=3,4,5,6,7,9,10,11,12IO=228h;IRQ=3,4,5,6,7,9,10,11,12</td><td>Enable/Disable Serial Port (COM).Fixed configuration of serial port.Select an optimal setting for Super IO device.</td></tr></table>

# 8.3.6 COM Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM Port Speed</td><td>LegacyHigh-Speed(500K)</td><td>Select COM Port Speed as legacy or High-Speed (500K)</td></tr><tr><td>COM1 Port Standard</td><td>RS-232RS-422 TM MasterRS-422 TM SlaveRS-422 (Non-TM)</td><td>Select Serial Port Standard of COM1</td></tr><tr><td>COM2 Port Standard</td><td>RS-232RS-422 TM MasterRS-422 TM SlaveRS-422 (Non-TM)RS-485 TMRS-485 (Non-TM)</td><td>Select Serial Port Standard of COM2</td></tr></table>

# 8.3.7 Serial Console Redirection

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>COM1</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM2</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM3</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr><tr><td>COM4</td><td colspan="2">Info only</td></tr><tr><td>Console Redirection</td><td>Enabled Disabled</td><td>Console Redirection Enable or Disable.</td></tr><tr><td>Console Redirection Settings</td><td>Submenu</td><td></td></tr></table>

Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Console Redirection Settings</td><td colspan="2">Info only</td></tr><tr><td>Terminal Type</td><td>VT100VT100+VT-UTF8ANSI</td><td>Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.</td></tr><tr><td>Bits per second</td><td>9600192003840057600115200</td><td>Selects serial port transmission speed.</td></tr><tr><td>Data Bits</td><td>78</td><td>Select Data Bits.</td></tr><tr><td>Parity</td><td>NoneEvenOddMarkSpace</td><td>Select Parity.</td></tr><tr><td>Stop Bits</td><td>12</td><td>Select number of stop bits.</td></tr><tr><td>Flow Control</td><td>NoneHardware RTS/CTS</td><td>Select flow control.</td></tr><tr><td>VT-UTF8 Combo Key Support</td><td>DisabledEnable</td><td>Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.</td></tr><tr><td>Recorder Mode</td><td>DisabledEnable</td><td>With this mode enabled only text will be sent. This is to capture Terminal data.</td></tr><tr><td>Resolution 100x31</td><td>DisabledEnable</td><td>Enables or disables extended terminal resolution</td></tr><tr><td>Putty KeyPad</td><td>VT100LINUXXTERMR6SCOESCNVT400</td><td>Select FunctionKey and KeyPad on Putty.</td></tr></table>

Legacy Console Redirection Settings

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Legacy Serial Redirection Port</td><td>COM0COM1COM2COM3</td><td>Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages.</td></tr><tr><td>Legacy OS Redirection</td><td>80x2480x25</td><td>On Legacy OS, the Number of Rows and Columns supported redirection</td></tr><tr><td>Redirection After BIOS Post</td><td>Always EnabledBootLoader</td><td>The Settings specify if BootLoader is selected than Legacy console redirection is disabled before booting to Legacy OS. Default value is Always Enable which means Legaacy console Redirection is enabled for Legacy OS.</td></tr></table>

8.3.8 Trusted Computing

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Security Device</td><td>DisabledEnabled</td><td>Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not e available.</td></tr></table>

8.3.9 VPX3020 Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GPIO Configuration</td><td colspan="2">Submenu</td></tr><tr><td>System Reset Bi-direction</td><td>Disabled Enabled</td><td>Switch to Enable/Disable Bi-direction System Reset from IPMC</td></tr><tr><td>XMC Bifurcation</td><td>1x82x4</td><td>Select bifurcation for XMC</td></tr><tr><td>PCIe Station 0</td><td>4x22x41x8</td><td>Select PCIe Station 0 bifurcation</td></tr><tr><td>PCIe Station 1</td><td>2x21x4</td><td>Select PCIe Station 1 bifurcation</td></tr><tr><td>PCIe Speed</td><td>Gen1Gen2Gen3</td><td>Configure PCIe Switch link speed</td></tr></table>

GPIO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>GDISC1#_R</td><td>OutputInput</td><td>Select Configuration of GPIO GDISC1#_R</td></tr><tr><td>GPIO Status</td><td>HighLow</td><td></td></tr><tr><td>GPIO0_R</td><td>OutputInput</td><td>Select Configuration of GPIO GPIO0_R</td></tr><tr><td>GPIO Status</td><td>HighLow</td><td></td></tr><tr><td>GPIO1_R</td><td>OutputInput</td><td>Select Configuration of GPIO GPIO1_R</td></tr><tr><td>GPIO Status</td><td>HighLow</td><td></td></tr></table>

8.3.10 Network Stack Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Network Stack</td><td>Info only</td><td></td></tr><tr><td>Network Stack</td><td>Enabled Disabled</td><td>Enable/Disable UEFI network stack.</td></tr><tr><td>Network Stack Options</td><td>Info only</td><td></td></tr><tr><td>Ipv4 PXE Support</td><td>Enabled Disabled</td><td>Enable/Disable lpv4 PXE Support</td></tr><tr><td>Ipv4 HTTP Support</td><td>Enabled Disabled</td><td>Enable/Disable lpv4 HTTP Support</td></tr><tr><td>Ipv6 PXE Support</td><td>Enabled Disabled</td><td>Enable/Disable lpv6 PXE Support</td></tr><tr><td>Ipv6 HTTP Support</td><td>Enabled Disabled</td><td>Enable/Disable lpv6 HTTP Support</td></tr><tr><td>IPSEC Certificate</td><td>Enabled Disabled</td><td>Enable/Disable IPSEC Certificate</td></tr></table>

# 8.4 Server Mgmt

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>BMC Self Test Status</td><td>Info only</td><td>Display BMC Self Test Status</td></tr><tr><td>BMC Device ID</td><td>Info only</td><td>Display BMC Device ID</td></tr><tr><td>BMC Device Revision</td><td>Info only</td><td>Display BMC Device Revision</td></tr><tr><td>BMC Firmware Revision</td><td>Info only</td><td>Display BMC Firmware Revision</td></tr><tr><td>IPMI Version</td><td>Info only</td><td>Display IPMI Version</td></tr><tr><td>BMC Interface(s)</td><td>Info only</td><td>Display BMC Interface(s)</td></tr><tr><td>BMC Support</td><td>EnabledDisabled</td><td>Enable/Disable interfaces to communicate with BMC</td></tr></table>

# 8.5 Chipset

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCIe Scan Delay</td><td>0</td><td>System delay before PCIe scan. Unit is second and maximum value is 60 seconds.</td></tr><tr><td>System Agent (SA) Configuration</td><td>Submenu</td><td></td></tr><tr><td>PCI-IO Configuration</td><td>Submenu</td><td></td></tr></table>

# 8.5.1 System Agent (SA) Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SA PCIe Code Version</td><td>Info only</td><td>Display SA PCIe code version</td></tr><tr><td>Memory Configuraiton</td><td>Submenu</td><td></td></tr><tr><td>Graphics Configuration</td><td>Submenu</td><td></td></tr><tr><td>PEG Port Configuration</td><td>Submenu</td><td></td></tr></table>

Memory Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Memory RC Version</td><td>Info only</td><td>Display memory RC version</td></tr><tr><td>Memory Frequency</td><td>Info only</td><td>Display memory frequency</td></tr><tr><td>Memory Voltage</td><td>Info only</td><td>Display memory voltage</td></tr><tr><td>Memory Timings (tCL-tRCD-tRP-tRAS)</td><td>Info only</td><td>Display memory timings</td></tr><tr><td>Channel 0 Slot 0</td><td>Info only</td><td>Display size, number of ranks, manufacturer</td></tr><tr><td>Channel 1 Slot 0</td><td>Info only</td><td>Display size, number of ranks, manufacturer</td></tr><tr><td>Maximum Memory Frequency</td><td>Auto106712001333140016001800186720002133220024002666</td><td>Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk, i.e. divide by 133 or 100</td></tr><tr><td>Max TOLUD</td><td>Dynamic1 GB1.25 GB1.5 GB1.75 GB2 GB2.25 GB2.5 GB2.75 GB3 GB3.25 GB3.5 GB</td><td>Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic controller.</td></tr></table>

Graphics Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Skip Scanning of External Gfx Card</td><td>DisabledEnabled</td><td>If Enable, it will not scan for External Gfx Card on PEG and PCH PCIE Ports</td></tr><tr><td>Primary Display</td><td>AutoIGFXPEGPCISG</td><td>Select which of IGFX/PEG/PCI Graphics device should be Primary Display or select SG for switchable Gfx.</td></tr><tr><td>Select PCIE Card</td><td>AutoElk Creek 4PEG Eval</td><td>Select the card used on the platformAuto: Skip GPIO based Power Enable to dGPUElk Creek 4: DGPU Power Enable = ActiveLowPEG Eval: DGPU Power</td></tr><tr><td>Internal Graphics</td><td>AutoDisabledEnabled</td><td>Keep IGFX enabled based on the setup options.</td></tr><tr><td>GTT Size</td><td>2MB4MB8MB</td><td>Select the GTT Size</td></tr><tr><td>Aperture Size</td><td>128MB256MB512MB1024MB2048MB</td><td>Select the Aperture SizeNote: Above 4GB MMIO BIOS assignment is automatically enabled when selecting 2048MB aperture. To use this feature, please disable CSM support.</td></tr><tr><td>DVTM Pre-Allocated</td><td>4M8M16M32M64M</td><td>Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory Size used by the Internal Graphics Device.</td></tr><tr><td>DVMT Total Gfx Mem</td><td>128M256MMAX</td><td>Select DVMT5.0 Total Graphc Memory Size used by the Internal Graphics Device.</td></tr></table>

PEG Port Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PEG 0:1:0</td><td>Info only</td><td></td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable or Disable the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:0 Max Speed</td></tr><tr><td>PEG0 Slot Power Limit Value</td><td>75</td><td>Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255</td></tr><tr><td>PEG0 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEG0 Physical Slot Number</td><td>1</td><td>Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191</td></tr><tr><td>PEG0 Max Payload Size</td><td>Auto128256 TLP</td><td>Select PEG0 Max Payload Size; Choose Auto(Default Device Capability) or force to 128/256 Bytes.</td></tr><tr><td>PEG 0:1:1</td><td>Info only</td><td></td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable or Disable the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:1 Max Speed</td></tr><tr><td>PEG1 Slot Power Limit Value</td><td>75</td><td>Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255</td></tr><tr><td>PEG1 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEG1 Physical Slot Number</td><td>2</td><td>Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191</td></tr><tr><td>PEG 0:1:2</td><td>Info only</td><td></td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable or Disable the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:2 Max Speed</td></tr><tr><td>PEG2 Slot Power Limit Value</td><td>75</td><td>Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255</td></tr><tr><td>PEG2 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEG2 Physical Slot Number</td><td>3</td><td>Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191</td></tr><tr><td>PEG 0:6:0</td><td>Info only</td><td></td></tr><tr><td>Enable Root Port</td><td>DisabledEnabledAuto</td><td>Enable or Disable the Root Port</td></tr><tr><td>Max Link Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PEG 0:1:2 Max Speed</td></tr><tr><td>PEG3 Slot Power Limit Value</td><td>75</td><td>Sets the upper limit on power supplied by slot. Power limit (in Watts) is calculated by multiplying this value by the Slot Power Limit Scale. Values 0-255</td></tr><tr><td>PEG3 Slot Power Limit Scale</td><td>1.0x0.1x0.01x0.001x</td><td>Select the scale used for the Slot Power Limit Value.</td></tr><tr><td>PEG3 Physical Slot Number</td><td>3</td><td>Set the physical slot number attached to this Port. The number has to be globally unique within the chassis. Values 0-8191</td></tr><tr><td>Gen3 RxCTLE Control</td><td>Submenu</td><td></td></tr><tr><td>PCIe Rx CEM Test Mode</td><td>DisabledEnabled</td><td>Enable/Disable PEG Rx CEM Loopback Mode</td></tr><tr><td>PCIe Spread Spectrum</td><td>DisabledEnabled</td><td>Allows disabling Spread Spectrum Clocking for compliance testing</td></tr></table>

PEG Port Configuration > Gen3 RxCTLE Control

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Bundle0</td><td>0</td><td>Gen3 RxCTLE setting for Bundle0</td></tr><tr><td>Bundle1</td><td>0</td><td>Gen3 RxCTLE setting for Bundle1</td></tr><tr><td>Bundle3</td><td>0</td><td>Gen3 RxCTLE setting for Bundle3</td></tr><tr><td>Bundle4</td><td>0</td><td>Gen3 RxCTLE setting for Bundle4</td></tr><tr><td>Bundle5</td><td>0</td><td>Gen3 RxCTLE setting for Bundle5</td></tr><tr><td>Bundle6</td><td>0</td><td>Gen3 RxCTLE setting for Bundle6</td></tr><tr><td>Bundle7</td><td>0</td><td>Gen3 RxCTLE setting for Bundle7</td></tr><tr><td>PEG10 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG0 RxCTLE adaptive behavior</td></tr><tr><td>PEG11 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG1 RxCTLE adaptive behavior</td></tr><tr><td>PEG11 RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides PEG2 RxCTLE adaptive behavior</td></tr><tr><td>DMI RxCTLE Override</td><td>Disabled Enabled</td><td>When Enabled, it overrides DMI RxCTLE adaptive behavior</td></tr></table>

8.5.2 PCH-IO Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Configuration</td><td>Submenu</td><td></td></tr><tr><td>SATA And RST Configuration</td><td>Submenu</td><td></td></tr><tr><td>Serial IRQ Mode</td><td>Continuous</td><td>Configure Serial IRQ Mode.</td></tr><tr><td>High Precision Timer</td><td>EnabledDisabled</td><td>Enable or Disable the High Precision Event Timer.</td></tr><tr><td></td><td></td><td></td></tr></table>

PCI Express Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Clock Gating</td><td>EnabledDisabled</td><td>PCI Express Clock Gating Enable/Disable for each root port.</td></tr><tr><td>DMI Link ASPM Control</td><td>DisableL0sL1L0sL1Auto</td><td>The control of Active State Power Management of the DMI Link.</td></tr><tr><td>PCIE Port assigned to LAN</td><td>Disabled</td><td>Fixed</td></tr><tr><td>Compliance Test Mode</td><td>DisabledEnabled</td><td>Enable when using Compliance Load Board</td></tr><tr><td>PCIe-USB Glitch W/A</td><td>DisabledEnable</td><td>PCIe-USB Glitch W/A for bad USB device(s) connected behind PCIE/PEG Port.</td></tr><tr><td>PCIe function swap</td><td>DisabledEnabled</td><td>When Disabled, prevents PCIE rootport function swap. If any function other than  $0^{th}$  is enabled,  $0^{th}$  will become visible.</td></tr><tr><td>PCI Express Root Port5</td><td>Submenu</td><td></td></tr><tr><td>PCI Express Root Port21</td><td>Submenu</td><td></td></tr></table>

PCI Express Configuration > PCI Express Root Port x

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>PCI Express Root Port_x</td><td>EnabledDisabled</td><td>PCI Express Clock Gating Enable/Disable for each root port.</td></tr><tr><td>Disable Gen2 PII Shutdown and L1 Controller Power gating</td><td>DisabledEnabled</td><td>When Enabled, disables Gen2 PLL Shutdown and L1 Controller power gating, Enable this option if using Titan Ridge A0/Alpine Ridge thunderbolt controller.</td></tr><tr><td>Connection Type</td><td>Slot</td><td></td></tr><tr><td>ASPM 0</td><td>DisabledL0sL1L0sL1Auto</td><td>Set the ASPM Level: Force L0s – Force all links to L0s State AUTO – BIOS auto configureDISABLE – Disables ASPM</td></tr><tr><td>L1 Substates</td><td>DisablesL1.1L1.1 &amp; L1.2</td><td>PCI Express L1 Substates settings.</td></tr><tr><td>Gen3 Eq Phase3 Method</td><td>HardwareStatic Coeff.</td><td>PCIe Gen3 Equalization Phase 3 Method</td></tr><tr><td>UPTP</td><td>5</td><td>Upstream Port Transmitter Preset</td></tr><tr><td>DPTP</td><td>7</td><td>Downstream Port Transmitter Preset</td></tr><tr><td>ACS</td><td>DisabledEnabled</td><td>Enable/Disable Access Control Services Extended Capability</td></tr><tr><td>PTM</td><td>DisabledEnabled</td><td>Enable/Disable Precision Time Measurement</td></tr><tr><td>DPC</td><td>DisabledEnabled</td><td>Enable/Disable Downstream Port Containment</td></tr><tr><td>EDPC</td><td>DisabledEnabled</td><td>Enable/Disable Rootport extensions for Downstream Port containment</td></tr><tr><td>URR</td><td>DisabledEnabled</td><td>PCI Express Unsupported Request Reporting Enable/Disable</td></tr><tr><td>FER</td><td>DisabledEnabled</td><td>PCI Express Device Fatal Error Reporting Enable/Disable</td></tr><tr><td>NFER</td><td>DisabledEnabled</td><td>PCI Express Device Non-Fatal Error Reporting Enable/Disable.</td></tr><tr><td>CER</td><td>DisabledEnabled</td><td>PCI Express Device Correctable Error Reporting Enable/Disable.</td></tr><tr><td>CTO</td><td>DisabledEnabled</td><td>PCI Express Completion Timer to Enable/Disable.</td></tr><tr><td>SEFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Fatal Error Enable/Disable.</td></tr><tr><td>SENFE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Non-Fatal Error Enable/Disable</td></tr><tr><td>SECE</td><td>DisabledEnabled</td><td>Root PCI Express System Error on Correctable Error Enable/Disable.</td></tr><tr><td>PME SCI</td><td>DisabledEnabled</td><td>PCI Express PME SCI Enable/Disable.</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>PCI Express Hot Plug Enable/Disable.</td></tr><tr><td>Advanced Error Reporting</td><td>DisabledEnabled</td><td>Advanced Error Reporting Enable/Disable.</td></tr><tr><td>PCIe Speed</td><td>AutoGen1Gen2Gen3</td><td>Configure PCIe Speed</td></tr><tr><td>Transmitter Half Swing</td><td>DisabledEnabled</td><td>Transmitter Half Swing Enable/Disable</td></tr><tr><td>Detect Timeout</td><td>0</td><td>The number of milliseconds reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.</td></tr><tr><td>Extra Bus Reserved</td><td>0</td><td>Extra Bus Reserved (0-7) for bridges behind this Root Bridge.</td></tr><tr><td>Reserved Memory</td><td>10</td><td>Reserved Memory for this Root Bridge (1-20) MB</td></tr><tr><td>Reserved I/O</td><td>4</td><td>Reserved I/O (4K/8K/12K/16K/20K) Range for this Root Bridge.</td></tr><tr><td>PCH PCIe LTR Configuration</td><td>Info only</td><td></td></tr><tr><td>LTR</td><td>DisabledEnabled</td><td>PCH PCIE Latency ReportingEnable/Disable</td></tr><tr><td>Snoop Latency Override</td><td>DisabledManualAuto</td><td>Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Non Snoop Latency Override</td><td>DisabledManualAuto</td><td>Non Snoop Latency Override for PCH PCIE. Disabled: Disable override.Manual: Manually enter override values.Auto (default): Maintain default BIOS flow.</td></tr><tr><td>Force LTR Override</td><td>DisabledEnabled</td><td>Force LTR Override for PCH PCIE. Disabled: LTR override values will not be forced.Enable: LTR override values will be forced and LTR messages from the device will be ignored.</td></tr><tr><td>LTR Lock</td><td>DisabledEnabled</td><td>PCIE LTR Configuration Lock</td></tr><tr><td>Extra options</td><td>Submenu</td><td></td></tr></table>

PCI Express Root Port x > Extra options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Detect Non-Compliance</td><td>DisabledEnabled</td><td>Detect Non-Compliance PCI Express Device. If enable, it will take more time at POST time.</td></tr><tr><td>Prefetchable Memory</td><td>10</td><td>Prefetchable Memory Range for this Root Bridge</td></tr><tr><td>Reserved Memory Alignment</td><td>1</td><td>Reserved Memory Alignment (0-31 bits)</td></tr><tr><td>Prefetchable Memory Alignment</td><td>1</td><td>Prefetchable Memory Alignment (0-31 bits_</td></tr></table>

SATA and RST Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>SATA Controller(s)</td><td>EnabledDisabled</td><td>Enable/Disable SATA Deice</td></tr><tr><td>SATA Mode Selection</td><td>AHCIIntel RST Premium with Intel Optane System Acceleration</td><td>Determines how SATA Controller(s) operate.</td></tr><tr><td>SATA Test Mode</td><td>EnabledDisabeld</td><td>Test Mode Enable/Disable (Loop Back).</td></tr><tr><td>Software Feature Mask Configuration</td><td>Submenu</td><td></td></tr><tr><td>Aggressive LPM Support</td><td>DisabledEnabled</td><td>Enable PCH to aggressively enter link power state.</td></tr><tr><td>SATA Controller Speed</td><td>DefaultGen1Gen2Gen3</td><td>Indicates the maximum speed the SATA controller can support.</td></tr><tr><td>Serial ATA Port x (x=0~7)</td><td>Info only</td><td></td></tr><tr><td>Port x</td><td>DisabledEnabled</td><td>Enable or Disable SATA Port</td></tr><tr><td>Hot Plug</td><td>DisabledEnabled</td><td>Designates this port as Hot Pluggable.</td></tr><tr><td>External</td><td>DisabledEnabled</td><td>Marks this port as external.</td></tr><tr><td>Spin Up Device</td><td>DisabledEnabled</td><td>If enabled for any of ports Staggerred Spin Up will be performed and only the drives which have this option enabled will spin up at boot. Otherwise all drives spin up at boot.</td></tr><tr><td>SATA Device Type</td><td>Hard Disk DriveSolid State Drive</td><td>Identify the SATA port is connected to Solid State Drive or Hard Disk Drive</td></tr><tr><td>SATA Port x DevSlp</td><td>DisabledEnabled</td><td>Enable/Disable SATA Port x DevSlp. For DevSlp to work, both hard drive and SATA port need to support DevSlp function, otherwise an unexpected behavior ight happen.</td></tr><tr><td>DITO Configuration</td><td>DisabledEnabled</td><td>Enable/Disable DITO Configuration</td></tr><tr><td>DITO Value</td><td>Info only</td><td>Display DITO value</td></tr><tr><td>DM Value</td><td>Info only</td><td>Display DM value</td></tr></table>

SATA and RST Configuration > Software Feature Mask Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>HDD Unlock</td><td>EnabledDisabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr><tr><td>LED Locate</td><td>EnabledDisabled</td><td>If enabled, indicates that the HDD password unlock in the OS is enabled.</td></tr></table>

# 8.6 Boot

8.6.1 Boot Configuration

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Boot Configuration</td><td colspan="2">Info only</td></tr><tr><td>Setup Prompt Timeout</td><td>3</td><td>Number of seconds to wait for setup activation key. 65535(0Xfff) means indefinite waiting.</td></tr><tr><td>Bootup NumLock State</td><td>On Off</td><td>Select the keyboard Numlock state</td></tr><tr><td>Quiet Boot</td><td>Disabled Enabled</td><td>Enables or disables Quiet Boot option</td></tr><tr><td>Fast Boot</td><td>Disable Enable</td><td>Enables or disables boot with initialization of a minimal set of devices required to launch active boot option. Has no effect for BBS boot options.</td></tr><tr><td>SATA Support</td><td>Last Boot SATA Devices OnlyAll SATA Devices</td><td>If Last Boot SATA Devices only, only last boot SATA device will be available in Post. If All SATA Devices, all SATA devices will be available in OS and Post.</td></tr><tr><td>VGA Support</td><td>Auto EFI Driver</td><td>If Auto, only install Legacy OpRom with Legacy OS and logo would NOT be shown during post. EFI driver will still be installed with EFI OS.</td></tr><tr><td>USB Support</td><td>Disabled Full Initial Partial Initial</td><td>If Disabled, all USB devices will NOT be available until after OS boot. If Partial Initial, USB Mass Storage and specific USB port/device will NOT be available before OS boot. If Enabled, all USB devices will be available in OS and Post.</td></tr><tr><td>PS2 Devices Support</td><td>Disable Enable</td><td>If Disabled, PS2 device will be skipped.</td></tr><tr><td>Network Stack Driver</td><td>Disabled Enabled</td><td>If Disabled, Network Stack Driver will be skipped.</td></tr><tr><td>Redirection Support</td><td>Disabled Enabled</td><td>If Disabled, Redirection function will be disabled.</td></tr><tr><td>BIOS mode select</td><td>LEGACY UEFI</td><td>Select boot mode LEGACY/UEFI</td></tr><tr><td>Boot Configuration</td><td>Info only</td><td></td></tr><tr><td>Boot Option #1</td><td>Hard Disk</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #2</td><td>CD/DVD</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #3</td><td>USB Hard Disk</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #4</td><td>USB CD/DVD</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #5</td><td>USB Key</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #6</td><td>USB Floppy</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #7</td><td>USB Lan</td><td>Sets the system boot order</td></tr><tr><td>Boot Option #8</td><td>Network</td><td>Sets the system boot order</td></tr></table>

# 8.7 Save & Exit

# 8.7.1 Reset Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes and Reset</td><td>Save changes and reset the system.</td><td>Save Changes and Reset</td></tr><tr><td>Discard Changes and Reset</td><td>Reset the system without saving any changes.</td><td>Discard Changes and Reset</td></tr></table>

# 8.7.2 Save Options

<table><tr><td>Feature</td><td>Options</td><td>Description</td></tr><tr><td>Save Changes</td><td></td><td>Save Changes done so far to any of the setup options.</td></tr><tr><td>Discard Changes</td><td></td><td>Discard Changes done so far to any of the setup options.</td></tr><tr><td>Restore Defaults</td><td></td><td>Restore/Load Default values for all the setup options.</td></tr><tr><td>Save as User Defaults</td><td></td><td>Save the changes done so far as User Defaults.</td></tr><tr><td>Restore User Defaults</td><td></td><td>Restore the User Defaults to all the setup options.</td></tr></table>

This page intentionally left blank.

# Important Safety Instructions

For user safety, please read and follow all instructions, WARNINGS, CAUTIONS, and NOTES marked in this manual and on the associated equipment before handling/operating the equipment.

 Read these safety instructions carefully.
 Keep this user’s manual for future reference.
? Read the specifications section of this manual for detailed information on the operating environment of this equipment.
 When installing/mounting or uninstalling/removing equipment:

 Turn off power and unplug any power cords/cables.

 To avoid electrical shock and/or damage to equipment:

 Keep equipment away from water or liquid sources;
 Keep equipment away from high heat or high humidity;
 Keep equipment properly ventilated (do not block or cover ventilation openings);

 Make sure to use recommended voltage and power source settings;

 Always install and operate equipment near an easily accessible electrical socket-outlet;

 Secure the power cord (do not place any object on/over the power cord);

 Only install/attach and operate equipment on stable surfaces and/or recommended mountings; and,

 If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.

 Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.

A Lithium-type battery may be provided for uninterrupted, backup or emergency power.

![The image displays a warning symbol consisting of a red triangle with a white exclamation point in its center. Below the triangle is the text 'WARNING:' in black, uppercase letters. The background is white.](.vpx3020-50m-00050-1000-10/42cc9356bdd68a721c5be8c946863c83acb0c032eee07c3b0e777caae84fd168.jpg)

Risk of explosion if battery is replaced with one of an incorrect type. Dispose of used batteries appropriately.

 Equipment must be serviced by authorized technicians when:

 The power cord or plug is damaged;
 Liquid has penetrated the equipment;
 It has been exposed to high humidity/moisture;
 It is not functioning or does not function according to the user’s manual;
 It has been dropped and/or damaged; and/or,
 It has an obvious sign of breakage.

# Getting Service

Ask an Expert: http://askanexpert.adlinktech.com

# ADLINK Technology, Inc.

No. 66, Huaya 1st Rd., Guishan Dist.,

Taoyuan City 333411, Taiwan

Tel: +886-3-216-5088

Fax: +886-3-328-5706

Email: service@adlinktech.com

# Ampro ADLINK Technology, Inc.

6450 Via Del Oro

San Jose, CA 95119-1208, USA

Tel: +1-408-360-0200

Toll Free: +1-800-966-5200 (USA only)

Fax: +1-408-600-1189

Email: info@adlinktech.com

# ADLINK Technology (China) Co., Ltd.

300 Fang Chun Rd., Zhangjiang Hi-Tech Park

Pudong New Area, Shanghai, 201203 China

Tel: +86-21-5132-8988

Fax: +86-21-5132-3588

Email: market@adlinktech.com

# ADLINK Technology GmbH

Hans-Thoma-Strasse 11

D-68163 Mannheim, Germany

Tel: +49-621-43214-0

Fax: +49-621 43214-30

Email: emea@adlinktech.com

Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you.
[🔗 Link to the original document](.vpx3020-50m-00050-1000-10/vpx3020-50m-00050-1000-10.pdf)