## Slide 1

![The slide is a presentation title card. In the top left corner is the logo **COM+HPC®**. In the top right corner is the **ADLINK** logo with the tagline **LEADING EDGE AI COMPUTING**.\n\nA large red section on the left side contains the following text in white:\n*   **COM HPC**\n*   **Introduction**\n*   **Dylan Cheng**\n\nBelow the red section is a grey bar with the text **2026 Q1**.\n\nThe right side of the slide features a close-up photograph of a computer motherboard. Overlaid on the bottom portion of this image is the text **Modular High-Performance Computing**.\n\nIn the bottom left corner, the text reads:\n**ADLINK | Leading Edge AI**\n**Computing**](.introduction-com-hpc-q1-2026-2026-02-04/slide-001.jpg)

## Slide 2

![**Header:**\nMilestones\n30 years of driving “Open Standards” in embedded computing\n\n**Timeline Entries (Top Row - Chronological):**\n*   **1998:** Built CompactPCI R&D center\n*   **2004:** Became Sponsor Member of PXISA\n*   **2006:** PICMG COM Express subcommittee releases specification\n*   **2013:** Joined VITA\n*   **2021:** Introduced COM-HPC\n*   **2023:** Created MicroRAN private 5G network solution (Next to logo: MicroRAN)\n\n**Timeline Entries (Bottom Row - Chronological):**\n*   **2003:** Intel's Modular Communications Platforms AdvancedTCA & CompactPCI Ecosystem Partner\n*   **2005:** ETX Industrial Group releases ETX 3.0\n*   **2008:** Acquired Ampro, Founding Members of PC104 Consortium\n*   **2013:** Introduced SMARC and approved by the SGet Consortium\n*   **2022:** Introduced Open Standard Modules\n*   **2024:** Launched AI GPU Server\n\n**Middle Row Logos (Left to Right):**\n*   CompactPCI\n*   AdvancedTCA\n*   PXI Systems Alliance\n*   ETX\n*   COM Express\n*   PC104\n*   VITA Open Standards, Open Markets\n*   SMARC module\n*   COM-HPC\n*   OPEN STANDARD MODULE\n*   AXE\n\n**Bottom Section:**\nStandardization Committees\n*   PICMG (Logo) Executive Member\n*   PC/104 (Logo) Executive / Founding Member\n*   SGeT STANDARDIZATION GROUP FOR EMBEDDED TECHNOLOGIES (Logo) Standard Member\n*   PXI Systems Alliance (Logo) Sponsor Member\n*   VITA Open Standards, Open Markets (Logo) Standard Member\n\n**Footer:**\nADLINK | Leading Edge AI Computing Confidential 2](.introduction-com-hpc-q1-2026-2026-02-04/slide-002.jpg)

## Slide 3

![**Title:** Embedded computing market size & forecast\n\n**List Items:**\n*   **Segment by Application** – Medical, Defense & Aerospace, Communications, Automotive & Transport, Automation and Control, Others\n*   **Segment by Type** – ARM, x86, PowerPC, Others\n*   **By Company** – Advantech, Kontron ADLINK 390M US$, Abaco, Artesyn Embedded (Advanced Energy), Curtis Wright Controls, Ennoconn, Tria (AVNET), DFI, Congatec AG, Axiomtek Co. Ltd, Portwell, Dell, Radisys, ....\n\n**Chart Labels:**\n*   US$ 52B\n*   CAGR 6%\n*   US$ 39B\n*   2024\n*   2030\n\n**Footer:**\nADLINK | Leading Edge AI Computing\nConfidential\n3](.introduction-com-hpc-q1-2026-2026-02-04/slide-003.jpg)

## Slide 4

![The slide is titled "ADLINK's Computer-on-Modules: full spectrum coverage". It is a matrix chart with "Performance" on the vertical axis (increasing upwards) and "Power" on the horizontal axis (increasing rightwards).\n\nThe chart displays various module types categorized by TDP (Thermal Design Power) ranges along the bottom axis:\n\n*   **TDP <12W:** Includes "OPEN STANDARD MODULE™", "arm", and "SMARC module".\n*   **TDP <30W:** Includes "Q S E V E N" (logo) and "type 10 Mini".\n*   **TDP <85W:** Includes "COM Express®" logo, "type 6 Compact", "type 2/6/7 Basic", and "intel.".\n*   **TDP <100W:** Includes "COM+HPC™" logo, "Mini", "Client", and "intel.".\n*   **TDP <200W:** Includes "Server", "arm", and "intel.".\n\nThe footer contains "ADLINK | Leading Edge AI Computing" on the left, "Confidential" in the center, and the page number "4" on the right.](.introduction-com-hpc-q1-2026-2026-02-04/slide-004.jpg)

## Slide 5

![This slide presents a business chart titled "ADLINK's M-shaped COM portfolio" under the sub-header "Capturing Edge AI Growth and Sustaining Revenue Stability."\n\n**Top Right Text Block:**\n"Why Should Customers Care? By optimizing silicon selection across platforms, we ensure the best balance of performance, cost, and scalability—helping customers accelerate deployment and maximize ROI"\n\n**Main Chart:**\nThe chart is an M-shaped graph with "Relative Market Growth Potential" on the vertical Y-axis and "Average Revenue Contribution" on the horizontal X-axis. It features three distinct peaks:\n\n*   **Left Peak (Pink):**\n    *   Label: "Cost Effective COM"\n    *   Description: "Optimized for High-Volume Deployments"\n    *   Examples: "IoT Gateway, Smart Sensors,"\n    *   Bottom Labels: "OPEN STANDARD MODULE," "SMARC module," "COM-E Low-end"\n    *   Arrow pointing left: "Edge Node"\n\n*   **Center Peak (Red):**\n    *   Label: "Mid-Range COM"\n    *   Description: "Reliable Solutions" / "Balanced Cost & Performance"\n    *   Examples: "Factory Automation, Medical Equipment, Retail Kiosks General Embedded Applications.."\n    *   Bottom Labels: "COM Express," "COM-E High-end"\n\n*   **Right Peak (Pink):**\n    *   Label: "High Performance COM"\n    *   Description: "Optimized for Performance and Scalability"\n    *   Examples: "Autonomous system, advance robotics, AI-powered Edge"\n    *   Bottom Label: "COM-HPC"\n    *   Arrow pointing right: "Edge Server"\n\n**Footer:**\n"ADLINK | Leading Edge AI Computing" (bottom left), "Confidential" (bottom center), and the page number "5" (bottom right).](.introduction-com-hpc-q1-2026-2026-02-04/slide-005.jpg)

## Slide 6

![**Slide Title:** Synergy for the future / Building enduring alliances with strategic ecosystem partners\n\n**Partners and Descriptions (Grid Layout):**\n\n*   **intel:** Prestige Partner\n*   **AMD:** Embedded Partner\n*   **ami:** BIOS Partner\n*   **AUO:** Strategic Partner\n*   **nvidia:** Preferred Member in NVIDIA Partner Network\n*   **arm:** Partner in Arm SystemReady, PSA Certified and PARSEC Compliance Program\n*   **AMPERE:** Technology Partner\n*   **NXP:** Gold Partner\n*   **MEDIATEK:** Powered by MediaTek Genio Partner\n*   **Qualcomm:** Member of the Qualcomm Advantage Network\n*   **COLLABORA:** Supporting Partner\n*   **linaro / ONELab:** Supporting Partner\n*   **Microsoft Azure:** Azure Certified for IoT Partner\n*   **Canonical:** Ubuntu Linux OS Partner\n*   **aws:** Devices qualified to work with AWS IoT Greengrass\n\n**Footer:** ADLINK | Leading Edge AI Computing, Confidential, 6](.introduction-com-hpc-q1-2026-2026-02-04/slide-006.jpg)

## Slide 7

![The slide presents information about the COM-HPC standard.\n\n**Header:**\n*   Top Left: Large text "COM-HPC®" with a green plus symbol between COM and HPC.\n*   Top Right: The PICMG logo (a blue hexagon with white text).\n\n**Main Text Content:**\n*   "COM-HPC is an open standard for embedded computing modules designed to deliver server-class bandwidth, power, and performance. Available in multiple sizes and configurations, COM-HPC modules are ideal for high-end IoT and edge server applications, particularly those requiring PCIe Gen5 and beyond."\n*   "The COM-HPC Module specification is hosted by PICMG. It is not freely available but may be purchased from the PICMG website"\n*   "The COM HPC Carrier design specifications can be freely downloaded at : https://www.picmg.org/resources/design-guides/"\n\n**Visuals:**\n*   On the right side, there is a 3D rendering of a green circuit board (carrier board) with a smaller module hovering above it, illustrating the form factor.\n\n**Footer:**\n*   Bottom Left: "ADLINK | Leading Edge AI Computing" (ADLINK is in red).\n*   Bottom Center: "Confidential"\n*   Bottom Right: The number "7".](.introduction-com-hpc-q1-2026-2026-02-04/slide-007.jpg)

## Slide 8

![**Title:** COM HPC sizes and feature sets\n\n**COM-HPC®/Mini**\n*   16 PCI Express Gen5/6 lanes\n*   4 graphics interfaces\n*   2x NBase-T (max 10Gb)\n*   4x USB 3.x or 2x USB 4.0, 8x USB2.0\n*   Power envelope typ. up to 40W\n*   Module size: Mini\n\n**COM-HPC®/Client**\n*   48 +1 PCI Express Gen5/6 lanes\n*   4 graphics interfaces\n*   2x 25 Gb Ethernet interfaces\n*   4x USB 4.0, 8 x USB2.0\n*   Power envelope typ. up to 100W\n*   Module size: A, B, C\n\n**COM-HPC®/Server**\n*   64 +1 PCI Express Gen5/6 lanes\n*   No graphic interfaces\n*   8x 25 Gb Ethernet interfaces\n*   2x USB 4.3 and 8x USB 2.0\n*   Power envelope typ. up to 180W\n*   Module size: D, E\n\n**Diagrams (Module Sizes):**\n*   **Mini:** 70 x 95\n*   **Size (Client A):** 120 x 95\n*   **Size (Client B):** 120 x 120\n*   **Size (Client C):** 120 x 160\n*   **Size D:** 160 x 160\n*   **Size E:** 160 x 200\n\n**Footer:**\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   8](.introduction-com-hpc-q1-2026-2026-02-04/slide-008.jpg)

## Slide 9

![The slide is titled "**A New High-speed Connector**".\n\nIn the center, three long, rectangular connector modules with rows of gold pins are displayed diagonally. Overlaid text reads "**on module**".\n\nSurrounding the image are the following specifications:\n\n**Left Side:**\n*   **HIGH-SPEED PERFORMANCE**\n    *   • PCIe® 6.0 capable\n    *   • 100 Gb (4 x 25 Gb)\n    Ethernet\n    *   • 40 Gbps\n    USB4/Thunderbolt\n    *   • 80 Gbps DisplayPort\n*   **Dimensions**\n    LxW\n    68.62 mm x 9\n    mm\n\n**Right Side:**\n*   **High density**\n    400 pins\n*   **Stacking height**\n    5mm and 10mm\n    board to board\n\n**Footer:**\nADLINK | Leading Edge AI Computing\nConfidential\n9](.introduction-com-hpc-q1-2026-2026-02-04/slide-009.jpg)

## Slide 10

![**Current specification status**\n**COM+HPC®**\n\n**Module**\n**Major changes**\n**Date**\n\n**Statement of Work**\n2018\nSponsored by ADLINK, congatec and Kontron\n\n**Module Rev 1.0**\nFeb 19, 2021\nMinor modifications to adapt for Intel Baytrail\n\n**Module Rev 1.1**\nJan 21, 2022\nadd HD Audio as alternative for SoundWire,\nadd FUSA (functional safety signals) and a 2nd 5V standby pin\n\n**Module Rev 1.2**\nOct. 3, 2023\nadded Mini formfactor and definition\n\n**Carrier Design Guide**\n**Major changes**\n**Date**\n\n**Carrier DG Rev 1.0**\nMar 17, 2021\nPreliminary version with Ethernet KR and KR4 CEI diagrams.\n\n**Carrier DG Rev 2.0**\nJan 14, 2022\nFirst version of complete COM-HPC CDG\n\n**Carrier DG Rev 2.1**\nAug 10, 2023\nMostly improvements and corrections\n\n**Carrier DG Rev 2.2**\nAdd Mini formfactor\nFeb 16, 2024\n\n**ADLINK | Leading Edge AI Computing**\n**Confidential**\n**10**](.introduction-com-hpc-q1-2026-2026-02-04/slide-010.jpg)

## Slide 11

![The slide features a split background, white on the left and light grey on the right.\n\n**Top Left:**\nServer Type\n\n**Center/Bottom:**\nCOM•HPC® (The separator is a green four-pointed star/diamond)\n\n**Footer:**\n*   **Bottom Left:** ADLINK | Leading Edge AI Computing (ADLINK is red)\n*   **Bottom Center:** Confidential\n*   **Bottom Right:** 11](.introduction-com-hpc-q1-2026-2026-02-04/slide-011.jpg)

## Slide 12

![**COM HPC Server type pin groups**\n\nCOM-HPC Server targets headless (no display) embedded servers that require large memory capacity, and high bandwidth I/O.\n\nTypical uses are in rugged servers in field environments and applications such as cell tower base stations, test & measurement, medical equipment, and defense systems.\n\n**Diagrams:**\n*   **Size D** (red text)\n    *   400-pin\n    *   160\n    *   160\n    *   SOC\n*   **Size E** (red text)\n    *   400-pin\n    *   160\n    *   200\n    *   SOC\n\n**Blue Boxes (Top Row):**\n*   ETH-KR 2x 4 25G\n*   PCIe 48x\n*   PCIe x1 target\n\n**Blue Boxes (Bottom Row):**\n*   12V 5Vsb max 200 W\n*   USB 2.0 x8\n*   ETH_KR CEI sideband\n*   USB 3.x x2\n*   eSPI x1\n*   SATA x2\n*   IPMB & PCIe x1\n*   PCIe x16\n*   NBASE-T Max 10G\n\n**Footer:**\nADLINK | Leading Edge AI Computing\nConfidential\n12](.introduction-com-hpc-q1-2026-2026-02-04/slide-012.jpg)

## Slide 13

![The slide displays a roadmap for "COM HPC" products.\n\n**Header & Legend:**\n*   **Logo:** "COM HPC"\n*   **Legend:** "In Production", "Under Design", "Under Consideration"\n\n**Main Chart:**\n*   **Y-Axis Label:** "SERVER"\n*   **Timeline (X-Axis):** "In Production", "2022", "2023", "2024", "2025", "2026"\n\n**Product Entries (Marked as "In Production"):**\n\n1.  **COM-HPC-ALT**\n    *   **Blue Box:** "Server", "200 x 160mm"\n    *   **Text:** "COM-HPC-ALT", "EXTREME RUGGED" (red stamp), "32 ~ 128 core ARM Neoverse N1 v8.2", "6x RDIMM for max 768GB DDR4", "up to 64 lanes PCI Express GEN4", "optional 4 x 10GbE Ethernet", "AMPERE." logo.\n\n2.  **COM-HPC-sIDH/sIDH**\n    *   **Blue Box:** "Server", "160 x 160mm"\n    *   **Text:** "COM-HPC-sIDH/sIDH", "EXTREME RUGGED" (red stamp), "Intel® Xeon-D® D2700 & D2800 Series", "4x RDIMM for max 512GB DDR4", "up to 48 lanes PCI Express GEN4", "8x 10GbE or 4x 25GbE Ethernet", "intel." logo.\n\n**Footer:**\n*   "In Production"\n*   "ADLINK | Leading Edge AI Computing"\n*   "Confidential"\n*   "13"\n\n**Top Right:** An image of a server motherboard.](.introduction-com-hpc-q1-2026-2026-02-04/slide-013.jpg)

## Slide 14

![Specifications\nCOM-HPC-ALT\n\n**Processor:** Ampere Altra, Arm® Neoverse™ N1 v8.2+ 64-bit CPU cores\n• M128-26 128C, 2.6GHz, 133W (usage power)\n• M96-28 96C, 2.8GHz, 132W (usage power)\n• Q80-26 80C, 2.6GHz, 112W (usage power)\n• Q64-22 64C, 2.2GHz, 87W (usage power)\n• Q32-17 32C, 1.7GHz, 40W (usage power)\n\n**Memory**\n• 6x RDIMMs based on individual memory controller, max 768 GB DDR4 at max. 3200MT/s\n\n**PCI Express:** 64 lanes Gen4\n• 8 PCIe lanes (lane 0-7), 8 PCIe lanes (lane 8-15)\n• 3x PCIe x16 lanes (lane 6-3, lane 32-47, lane 48-63)\n\n**Remote Management**\n• 1x PCIe (PCIe BMC) dedicated for connecting to carrier BMC\n• IPMB through MMC on module\n\n**Ethernet**\n• Optional 4x 10GbE (configuration dependent)\n• 1x NBASE-T (1000/100/10 MB/s)\n\n**Peripherals**\n• 4x USB 3.0/2.0, 12x GPIO, 2x I2C, 2x UART, 1x SMB, 1x GP_SPI (build option)\n\n**EDK II with Tianocore UEFI and Security :** SystemReady Server level (TPM 2.0 chip on module)\n\n**Debug Connector:** DB40-HPC access to I2C for POST code, test points, SPI, SMB, MMC\n\n**Voltage Input :** AT/ATX: 12V +/- 5%\n\n**Operation Temperature**\n• Standard 0°C to 60°C, Extended -20°C to +75°C selected SKUs\n\nProduction\nAMPERE\n\nStandard supported\nUbuntu (Ubuntu server for ARM 20.04)\nyocto PROJECT (minimal enablement)\n\nSystem Ready Server\nAlmost any standard distribution runs out of the box\nWindows\n\nVirtualization pre-test\nvmware ESXi\n\nCOM-HPC Revision 1.1\n\n[Logos]\nAmpere Altra.Max\n10Gb, 10Gb, 10Gb E, 10Gb E, 1GbE\nPCI EXPRESS 4\nSUPERspeed USB 10Gbps\nEDKII OPEN SOURCE\nIPMB OOB MGMT\nEXTREME RUGGED\narm SystemReady SR\ntianocore\n\nADLINK | Leading Edge AI Computing\nConfidential\n14](.Introduction-COM-HPC-Q1-2026-[2026-02-04]/slide_014.jpg)

## Slide 15

![**Function Diagram**\n**COM-HPC-ALT**\n\n**Production**\n\n**Left Side:**\n*   **PCIe x8 Gen4 at Lane 0-7** | 2 x4, 4 x2\n*   **PCIe x8 Gen4 at Lane 8-15** | 2 x4, 4 x2\n*   **PCIe x16 Gen4 at Lane 16-3** | 1 x16, 2 x8, 4 x4\n*   **PCIe x16 Gen4 at Lane 32-4** | 1 x16, 2 x8, 4 x4\n*   **PCIe x16 Gen4 at Lane 48-6** | 1 x16, 2 x8, 4 x4\n*   **PCIe_BMC dedicated for carrier BMC**\n*   **4x USB 3.0/2.0**\n*   **PCIe to 4x USB**\n*   **12x GPIO**\n*   **2x UART**\n*   **2x I2C**\n\n**Center Chip:**\n*   **AMPERE®**\n*   **Altra™**\n*   **Q80-28**\n*   **® 2052**\n*   **TARW32.00E-16C60807**\n*   **△ KOREA**\n*   **AC-108018502**\n\n**Top Right:**\n*   **Max. 768GB (6x 128GB)**\n*   **DDR4 RDIMM, Up to 3200MT/s**\n\n**Right Side:**\n*   **PCIe x8**\n*   **Quad 10GbE LAN**\n*   **LAN contolle r**\n*   **NBASE-T (GbE)**\n*   **SFP add-on card**\n*   **10Gb & sidebands** (Vertical text)\n\n**Bottom Area:**\n*   **MMC**\n*   **TPM**\n*   **BIOS**\n*   **SMB**\n*   **IPMB**\n*   **GP_SPI**\n*   **Boot_SP**\n*   **I**\n\n**Bottom Left:**\n*   **COM+HPC™**\n*   **Revision 1.1**\n*   **ADLINK | Leading Edge AI Computing**\n\n**Footer:**\n*   **Confidential**\n*   **15**](.introduction-com-hpc-q1-2026-2026-02-04/slide-015.jpg)

## Slide 16

![**Specifications**\n**COM-HPC-sIDH**\n\n**Production**\n\n**Processor:** Intel® Xeon-D Processor, D-2700 series, Ice Lake-D HCC\n*   Xeon® D-2796TE 20C 2.0/3.1GHz, 30MB, 118W (eTemp)\n*   Xeon® D-2775TE 16C 2.0/3.1GHz, 25MB, 100W (eTemp)\n*   Xeon® D-2752TER 12C 1.8/2.8GHz, 20MB, 77W (eTemp & TCC)\n*   Xeon® D-2733NT 8C 2.1/3.2GHz, 15MB, 80W (Intel QAT)\n*   Xeon® D-2712T 4C 1.9/3.0GHz, 15MB, 65W\n*   Other non-IOTG SKUs not listed here support by project basis\n\n**Memory**\n*   256 (4x 64) GB DDR4 max 2933MT/s 4 RDIMM sockets\n*   512 (4x 128) GB via specific LPRDIMM\n\n**PCI Express:** 48 lanes\n*   8 PCIe Gen3 (lane 0-7) (x2, x4, x8)       8 PCIe Gen3 (lane 8-15) (x2, x4, x8)\n*   16 PCIe Gen4 (lane 16-31) (x16, x8, x4)    16 PCIe Gen4 (lane 32-47) (x16, x8, x4)\n\n**Remote Management**\n*   1x PCIe (PCIe BMC) dedicated for connecting to carrier BMC\n*   IPMB through MMC on module (build option)\n\n**Ethernet**\n*   Max. 8x ETH_KR (PHY on carrier required, except KR backplane) (10G/25G per port\n*   1x NBASE-T (2.5G, 1000/100/10 MB/s) (TSN, build option)\n\n**Peripherals**\n*   4x USB 3.0/2.0, 12x GPIO, 2x I2C, 2x UART, 1x SMB, eSPI, 2xSATA, eMMC (build option)\n*   combined HSIO (USB3, PCIe 0-15, SATA, NBASE-T) bandwidth is up to 16 PCIe Gen3.0 lanes\n\n**AMI EFI BIOS and Security** (TPM 2.0 chip on module)\n**Debug Connector:** DB40-HPC access to I2C for POST code, test points, SPI, SMB, MMC\n**Voltage Input :** AT/ATX: 12V +/- 5% (specific ATX power source design on carrier required for ATX appli\n**Operation Temperature**\n*   Extended -40°C to +85°C (selected SKUs) , Standard 0°C to 60°C\n\n**Standard supported**\nWindows Server 2022\nWindows 10\nWindows 11\nyocto PROJECT\n\n**Virtualization pre-test**\nvmware ESXi\n\nintel.\nCOM+HPC\nRevision 1.1\n\nintel Xeon D\n25Gb E\nPCI Express 4\nEXTREME RUGGED\n1GbE\nSUPERSPEED USB 10Gbps\nIPMB OOB MGMT\n\nADLINK | Leading Edge AI Computing\nConfidential\n16](.introduction-com-hpc-q1-2026-2026-02-04/slide-016.jpg)

## Slide 17

![**Header**\nFunction Diagram\nCOM-HPC- sIDH\nProduction\n\n**Left Side (Connectivity)**\nPCIe x8 Gen3 at Lane 0 1x8, 2 x4, 4 x2\nPCIe x8 Gen3 at Lane 8 15 1x8, 2 x4, 4 x2\nPCIe x16 Gen4 at Lane 16- 1 x16, 2 x8, 4 x4\nPCIe x16 Gen4 at Lane 32- 1 x16, 2 x8, 4 x4\nPCIe_BMC dedicate for carrier BMC\n2x SATA 6Gb/s\n4x USB 3.0/2.0\n\n**Center (Processor)**\nintel XEON\nIntel Xeon\nD-2700 Processor\n\n**Right Side (Memory & Network)**\n256GB (4x 64GB, RDIMM)\nDDR4 DIMM (RDIMM, UDIMM etc...)\nFour individual memory channel\nUp to 2933MT/s (SOC SKU depends)\n8x ETH_KR & sideband\n(10G/25G per port)\n(SOC SKU depends)\nNBASE-T\n(Up to 2.5GbE)\n2.5 GbE\nLAN controller\nDedicated PHY add-on card\n10G SFP+, 10GBASE-T\n\n**Bottom Section (Embedded/Management)**\neSPI\nSP\nSMB\nTPM\nBIOS\nEC\neSPI\n2x I2C 2x UART\n12x GPIO\neMMC (32/64GB) (build option)\nMMC\nIPMB (build option)\nBoot_SPI\n\n**Footer**\nCOM+HPC Revision 1.1\nADLINK | Leading Edge AI Computing\nConfidential\n17](.introduction-com-hpc-q1-2026-2026-02-04/slide-017.jpg)

## Slide 18

![**Product Lifecycle**\n\n**Legend:**\n*   Promotion\n*   Maintenance\n*   Last time buy\n*   Last shipment\n\n**Categories (Y-axis):**\n*   COM-HPC-sIDHR\n*   COM-HPC-sIDH\n*   COM-HPC-ALT\n*   Selected SKU\n\n**Timeline (X-axis):**\n*   2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042\n\n**Labels:**\n*   Rev .1.0\n*   Rev .1.1\n*   Rev .1.2\n\n**Footer/Branding:**\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   18\n*   COM-HPC®](.introduction-com-hpc-q1-2026-2026-02-04/slide-018.jpg)

## Slide 19

![The slide features a vertically split background, white on the left and light grey on the right. In the top left corner, the text "Client Type" is displayed. Centered across the slide is the large logo "COM+HPC®", separated by a green four-pointed star; "COM" is in bold black font while "HPC" is in an outlined black font. At the bottom left, the text "ADLINK | Leading Edge AI" appears above the word "Computing". The bottom center contains the word "Confidential", and the bottom right corner displays the page number "19".](.introduction-com-hpc-q1-2026-2026-02-04/slide-019.jpg)

## Slide 20

![The slide is titled "COM HPC Client type pin groups".\n\nBelow the title, the text reads:\n"COM-HPC Client targets display oriented high-end embedded products that"\n\n"Typical applications include medical equipment, high-end instrumentation, industrial equipment, casino gaming equipment, ruggedized field PCs, transportation, and defense systems."\n\nTo the right of this text are three diagrams labeled "Size A", "Size B", and "Size C". Each shows a grey module layout with internal components labeled "SoC" and "SODIMM".\n*   **Size A:** Dimensions 120 (height) x 95 (width). Labeled "400-pin" at top and bottom.\n*   **Size B:** Dimensions 120 (height) x 120 (width). Labeled "400-pin" at top and bottom.\n*   **Size C:** Dimensions 120 (height) x 160 (width). Labeled "400-pin" at top and bottom.\n\nBelow the text and diagrams is a large teal block diagram illustrating pin group allocations:\n\n**Top Row:**\n*   DDI3 (DP/HDMI)\n*   USB 4.0 (x2)\n*   PCIe 32x\n*   NBASE-T (x1)\n*   MIPI CSI (x2)\n*   ETH_KR (x2)\n*   PCIe target (x1)\n\n**Bottom Row:**\n*   12V 5Vsb (max 200 W)\n*   USB 2.0 (x8)\n*   USB 4.0 (x2)\n*   Audio (I2S / SNDW)\n*   DDI1 (DP/HDMI)\n*   DDI2 (DP/HDMI)\n*   eDP / DSI (x1)\n*   IPMB & PCIe\n*   SATA (x2)\n*   PCIe x16\n*   NBASE-T (x1)\n\n**Footer:**\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   20](.introduction-com-hpc-q1-2026-2026-02-04/slide-020.jpg)

## Slide 21

![**Header & Legend:**\n*   COM +HPC®\n*   In Production\n*   Under Design\n*   Under Consideration\n\n**Y-Axis Label:**\n*   CLIENT\n\n**Timeline Items (Left to Right):**\n\n*   **2024 (Blue Box):**\n    *   Client 160 x 120mm\n    *   COM-HPC-cRLS\n    *   13th-14th Gen. Intel® Core™ (Raptor Lake-S & Refresh)\n    *   up 128GB SO-DIMM DDR5\n    *   PCIe Gen5\n    *   intel.\n\n*   **2026 (Green Box):**\n    *   Client 160 x 120mm\n    *   COM-HPC-cBLS\n    *   Intel® Core™ Processors Series (Bartlett Lake S & 12P)\n    *   up 128GB SO-DIMM (4x) DDR5\n    *   PCIe Gen5\n    *   intel.\n\n*   **Under Consideration Section (Right Side):**\n    *   Under Consideration\n    *   **Item 1 (Yellow Box):**\n        *   Client 160 x 120mm\n        *   COM-HPC-cEPX\n        *   AMD® Ryzen 9000 Series Zen\n        *   AMD\n        *   up 128GB SO-DIMM (4x) DDR5\n        *   PCIe Gen5\n    *   **Item 2 (Yellow Box):**\n        *   Client 160 x 120mm\n        *   COM-HPC-cNLS\n        *   new Gen processor with NPU (Nova Lake S)\n        *   up 128GB SO-DIMM (4x) DDR5\n        *   PCIe Gen5\n        *   intel.\n        *   AI\n\n*   **Item Below 2026 (Yellow Box):**\n    *   Client 95 x 120mm\n    *   COM-HPC-cPTL\n    *   new Gen processor with NPU (Panther Lake)\n    *   up 128GB SO-DIMM DDR5\n    *   PCIe Gen5\n    *   EXTREME RUGGED\n    *   intel.\n    *   AI\n\n**X-Axis Timeline:**\n*   In Production\n*   2024\n*   2025\n*   2026\n*   2027\n*   2028\n\n**Footer:**\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   21](.introduction-com-hpc-q1-2026-2026-02-04/slide-021.jpg)

## Slide 22

![The slide presents technical specifications for a product named "COM-HPC-cRLS".\n\n**Header:**\n*   Specifications\n*   COM-HPC-cRLS\n*   Production (Blue button)\n\n**Main Body (Left Column):**\n*   **Processor:** 13th Intel® Core Processor Raptor Lake-S\n    *   Core™ i9-13900E 8P+16E/32T 65W\n    *   Core™ i7-13700E 8P+8E/24T 65W\n    *   Core™ i5-13500E 6P+8E/20T 65W\n    *   Other 35W SKUs not listed here, please check manual\n*   **Memory**\n    *   Up to 128 (4x 32) GB DDR5 SO-DIMM at max. 4800MT/s at four SO-DIMM sockets, dual-channel\n    *   Selected CPU SKU paired with R680E support ECC (and non-ECC)\n*   **PCH:** R680E, Q670E, H610E\n*   **PCI Express:** max. 38 lanes\n    *   1 PCIe Gen5 x16 (1x16 or 2x8, lane 16-31), 1 PCIe Gen4 x4 (x4 only, lane 8-11)\n    *   6 PCIe Gen3 x1 (x4, x2, x1 config, lane 0-5)\n    *   with R680E/Q670E: 1 PCIe Gen4 x4 (lane 12-15), 1 PCIe Gen4 x4 (lane 32-35), 1 PCIe Gen4 x4 (lane 36-39) (all are x4, x2, x1 config.)\n*   **Display and Audio** (4 independent displays)\n    *   DDI 0/1/2: DP1.4a / HDMI2.0b (3840x2160@50/60Hz) / DVI\n    *   eDP x4 lanes\n    *   HD Audio\n*   **Peripherals**\n    *   2x 2.5GbE NBASE-T LAN (TS at Linux, build option, selected CPU), 2x SATA 6Gb/s\n    *   Up to 4x USB 3.2 Gen2/2.0, 4x USB 2.0. 2x UART, 12x GPIO\n    *   2x I2C, 1x SMB, 1x GP_SPI (build option), ESPI\n*   **AMI EFI BIOS and Security** (TPM 2.0 chip on module)\n*   **Debug Connector:** DB40-HPC access to I2C for POST code, test points, SPI, SMB\n*   **Voltage Input :** AT/ATX: 12V +/- 5%\n*   **Operation Temperature**\n    *   Standard 0°C to 60°C\n\n**Right Side:**\n*   Standard supported\n    *   Windows 11\n    *   Windows 10\n    *   Ubuntu\n    *   yocto PROJECT\n    *   Virtualization pre-test\n    *   vmware ESXi\n*   **Image:** A photograph of a circuit board module.\n*   **Text/Logos:**\n    *   intel.\n    *   COM-HPC® Revision 1.2\n    *   intel CORE i9\n    *   HDMI\n    *   PCI Express 5\n    *   PCI Express 4\n    *   2.5GbE\n    *   2.5GbE\n    *   SUPERspeed USB 10 Gbps\n    *   SERIAL ATA 6Gb/s\n\n**Footer:**\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   22](.introduction-com-hpc-q1-2026-2026-02-04/slide-022.jpg)

## Slide 23

![**Header:** Function Diagram COM-HPC-cRLS (Production)\n\n**Top Left (CPU Connections):**\n*   DDI 0/1/2: DP/HDMI (4K)\n*   eDP x4 lanes\n*   PEG PCIe Gen5 x16 or 2 x8 or 1 x8 + 2 x4\n*   1x PCIe Gen4 x4 (x4)\n\n**Top Right (Memory):**\n*   Max. 128GB (4x 32GB)\n*   DDR5 4800 MT/s\n\n**Left Side (Peripherals):**\n*   4x USB 3.2 Gen2 / 2.0\n*   4x USB 2.0\n*   2x SATA 6Gb/s\n*   2x LAN 2.5GbE (TSN at Linux, optional)\n\n**Right Side (PCH Connections):**\n*   6x PCIe Gen3x1 (x4, x2, x1)\n*   1x PCIe Gen4 x4 (x4, x2, x1)\n*   1x PCIe Gen4 x4 (x4, x2, x1) (R680E/Q670E)\n*   HDA High Def. Audio\n\n**Bottom Center (Control/Security):**\n*   GP_SP I\n*   eSP I\n*   EC (2x I2C 2x UART 12x GPIO)\n*   SP I\n*   BIOS\n*   TPM\n\n**Footer:**\n*   COM+HPC™ Revision 1.1\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   23](.introduction-com-hpc-q1-2026-2026-02-04/slide-023.jpg)

## Slide 24

![**Specifications**\n**COM-HPC-cBLS**\n\n**Processor:** Intel® Core Processor Series 2 (Bartlett Lake-S) (**P-core only** and Hybrid SKUs)\n*   Core™ 9 273E, 12P Cores, 2.4(5.8)GHz 65W\n*   Core™ 7 253E, 12P Cores, 2.6(5.6)GHz 65W\n*   Core™ 7 251E, 8P+16E, 2.1(5.6)GHz P Core, 1.6(4.4)GHz E Core 65W\n*   Other 35W, 45W and even 125W SKU not shown here\n\n**Memory**\n*   Up to 128 (4x 32) GB DDR5 SO-DIMM at max. 4800MT/s at four SO-DIMM sockets, dual-channel\n*   Selected CPU SKU paired with R680E support **ECC** (and non-ECC)\n\n**PCH:** R680E, Q670E, H610E\n\n**PCI Express:** max. 38 lanes\n*   1 PCIe Gen5 x16 (1x16 or 2x8, lane 16-31), 1 PCIe Gen4 x4 (x4 only, lane 8-11)\n*   6 PCIe Gen3 x1 (x4, x2, x1 config, lane 0-5)\n*   with R680E/Q670E: 1 PCIe Gen4 x4 (lane 12-15),\n*   1 PCIe Gen4 x4 (lane 32-35),1 PCIe Gen4 x4 (lane 36-39) (all are x4, x2, x1 config.)\n\n**Display and Audio** (4 independent displays)\n*   DDI 0/1/2: DP1.4a / HDMI2.0b (3840x2160@50/60Hz) / DVI\n*   eDP x4 lanes\n*   HD Audio\n\n**Peripherals**\n*   2x 2.5GbE NBASE-T LAN (TS at Linux, build option, selected CPU), 2x SATA 6Gb/s\n*   Up to 4x USB 3.2 Gen2/2.0, 4x USB 2.0. 2x UART, 12x GPIO\n*   2x I2C, 1x SMB, 1x GP_SPI (build option), ESPI\n\n**AMI EFI BIOS and Security** (TPM 2.0 chip on module)\n\n**Debug Connector:** DB40-HPC access to I2C for POST code, test points, SPI, SMB\n\n**Voltage Input :** AT/ATX: 12V +/- 5%\n\n**Operation Temperature**\n*   Standard 0°C to 60°C\n\n**Standard supported**\nWindows 11\nWindows 10\nUbuntu\nyocto PROJECT\nWindows Server 2025 (TBD)\n\n**Virtualization pre-test**\nVMware ESXi\n\n**Design**\nSample Q1\n'26\nintel.\n\nCOM+HPC\nRevision\n1.2\n\nADLINK | Leading Edge AI Computing\nConfidential\n24](.introduction-com-hpc-q1-2026-2026-02-04/slide-024.jpg)

## Slide 25

![**Specifications**\n**COM-HPC-cNLS**\n\n**Processor:** new Gen Intel® Core Ultra Processor Nova Lake-S\n*   Core™ Ultra 9 16P+32E+4LP-E 150W (2 Xe³ GPU)\n*   Core™ Ultra 9 8P+16E+4LP-E 65W (2 Xe³ GPU)\n*   Core™ Ultra 5 4P+8E+4LP-E 65W (2 Xe³ GPU)\n*   Other 65W and even 125W SKU not shown here\n\n**NPU** integrated with up to **74 TOPS**\n\n**Memory**\n*   Up to 128 (4x 32) GB DDR5 SO-DIMM at four SO-DIMM sockets, dual-channel\n*   Selected CPU SKU paired with W980E support ECC (and non-ECC)\n\n**PCH:** W980E, Q970E, B960E\n\n**PCI Express:** max. 42 lanes\n*   1 PCIe Gen5 x16 (1x16 or 2x8, lane 16-31), 1 PCIe Gen5 x8 (x8 only, lane 8-15) (from CPU)\n*   6 PCIe Gen4 x1 (x4, x2, x1 config, lane 0-5) (from PCH)\n*   with W980E: 3 PCIe Gen5 x4 (lane 32-35, lane 36-39, lane 40-43) (from PCH)\n\n**Display and Audio** (4 independent displays)\n*   DDI 0/1: DP1.4a / HDMI2.0b (3840x2160@50/60Hz) / DVI (DDI 1 enabled based on W980E PCH config.)\n*   eDP x4 lanes\n*   HD Audio (I2S, Soundwire TBC)\n\n**Peripherals**\n*   2x 2.5GbE NBASE-T LAN (TS at Linux, build option, selected CPU), 2x SATA 6Gb/s\n*   Default 1x USB4, 3x USB 3.2 Gen2/2.0 and 4x USB 2.0. 2x UART, 12x GPIO\n*   2x I2C, 1x SMB, 1x GP_SPI (build option), ESPI\n\n**AMI EFI BIOS and Security** (TPM 2.0 chip on module)\n\n**Debug Connector:** DB40-HPC access to I2C for POST code, test points, SPI, SMB\n\n**Voltage Input** : AT/ATX: 12V +/- 5%\n\n**Operation Temperature**\n*   Standard 0°C to 60°C\n\n**Right Side Elements:**\n*   Planning\n*   Very early stage info.\n*   intel.\n*   Standard supported Windows 11\n*   Ubuntu\n*   yocto PROJECT (TBC)\n*   Virtualization pre-test VMware ESXi\n*   AI\n*   COM+HPC Revision 1.2\n\n**Bottom Logos/Text:**\n*   intel CORE ULTRA Xe LPG\n*   HDMI\n*   2.5GbE (x2)\n*   PCI EXPRESS 5\n*   PCI EXPRESS 4\n*   SUPERspeed USB 10 Gbps\n*   SERIAL ATA\n*   Note: preliminary data, please get final information at Intel website\n*   ADLINK | Leading Edge AI Computing\n*   Confidential\n*   25](.introduction-com-hpc-q1-2026-2026-02-04/slide-025.jpg)

## Slide 26

![**Header & Top Right**\nDefault configuration, based on W980E PCH\nCOM-HPC-cNLS\nPlanning\nVery early stage info.\n\n**Left Column (I/Os)**\nDDI 0/1: DP/HDMI\n4K\neDP x4 lanes\nPEG PCIe Gen5 x16 or 2 x8\nPEG PCIe Gen5 x8\n1x USB4\n3x USB 3.2 Gen2 / 2.0\n4x USB 2.0\n2x SATA 6Gb/s\n2x LAN 2.5GbE\n(TSN at Linux, optional)\n2.5\nGbE\nLAN\nLAN\n\n**Right Column (Memory & PCIe)**\nMax. 128GB (4x 32GB)\nDDR5 TBC MT/s\n6x PCIe Gen4x1\n(x4, x2, x1)\n1x PCIe Gen5 x4 (x4, x2,\nx1)\n1x PCIe Gen5 x4 (x4, x2,\nx1)\n1x PCIe Gen5 x4 (x4, x2)\n\n**Bottom Section (PCH Connections)**\nGP_SP I\neSP I\nEC\n2x I2C 2x UART\n12x GPIO\nSP I\nBIOS\nTPM\nHDA\nHigh Def.\nAudio\n\n**Footer**\nCOM+HPC™\nRevision 1.2\nADLINK | Leading Edge AI Computing\nConfidential\n26](.introduction-com-hpc-q1-2026-2026-02-04/slide-026.jpg)

## Slide 27

![**Specifications**\n**COM-HPC-cEPX**\n\n**Processor:** AMD® Embedded Ryzen 9000 Series (AM5 socket) : **Zen5** x86 cores\n*   16C, 4.3 (5.7)GHz 170W\n*   12C, 3.4 (5.4)GHz 120W\n*   12C, 3.4 (5.4)GHz 65W (Headless)\n*   8C, 3.8 (5.5)GHz 65W\n*   Other SKU not shown here\n\n**Memory**\n*   Up to 128 (4x 32) GB DDR5 SO-DIMM at four SO-DIMM sockets, dual-channel\n*   Selected CPU SKU paired with specific PCH support **ECC** (and non-ECC)\n\n**PCH:** X670 or B650\n\n**PCI Express:** max. 32 lanes (TBD)\n*   1 PCIe **Gen5 x16** (1x16 or 2x8, lane 16-31) (from CPU)\n*   1 PCIe **Gen5 x4** (x4, lane 8-11), 1 PCIe Gen4 x4 (x4, lane 12-15) (from CPU)\n*   6 PCIe Gen3 x1 (x4, x2, x1 config, lane 0-5), 3 PCIe Gen4 x4 (lanes 32-35, 36-39, 40-43)\n\n**Display and Audio** (TBD independent displays)\n*   DDI 0/1: DP1.4a / HDMI2.0b (3840x2160@50/60Hz) / DVI (TBD)\n*   eDP x4 lanes\n*   HD Audio (I2S, Soundwire TBC)\n\n**Peripherals**\n*   2x 2.5GbE NBASE-T, 2x SATA 6Gb/s\n*   Up to 4x USB 3.2 Gen2/2.0, 4x USB 2.0. 2x UART, 12x GPIO\n*   2x I2C, 1x SMB, 1x GP_SPI (TBD), ESPI\n\n**AMI EFI BIOS and Security** (TPM 2.0 chip on module)\n**Debug Connector:** DB40-HPC access to I2C for POST code, test points, SPI, SMB\n**Voltage Input** : AT/ATX: 12V +/- 5%\n**Operation Temperature**\n*   Standard 0°C to 60°C\n\n**[Right Side Content]**\n**Planning**\nVery early stage info.\n\n**Standard supported**\n[Windows 11 Logo] Windows 11\n[Ubuntu Logo] Ubuntu\nAMD Logo\n\nVirtualization pre-test\nvmware ESXi\n\nCOM-HPC\nRevision 1.2\n\nAMD RYZEN Embedded\nHDMI\n2.5GbE\n2.5GbE\nPCI EXPRESS 5\nPCI EXPRESS 4\nUSB\nSERIAL ATA\n\nNote: preliminary data, please get final information at AMD website\nConfidential\n27\n\nADLINK | Leading Edge AI Computing](.Introduction-COM-HPC-Q1-2026-[2026-02-04]/slide_027.jpg)

## Slide 28

![**Title/Header:**\nDefault configuration, based on X670 PCH\nCOM-HPC-cEPX\nPlanning\nVery early stage info.\n\n**Left Column (Peripherals & Inputs):**\nDDI 0/1: DP/HDMI\n4K\neDP x4 lanes\nPEG PCIe Gen5 x16 or 2 x8\n1x PCIe Gen5 x4 (x4)\n1x PCIe Gen4 x4 (x4)\n4x USB 3.2 Gen2 / 2.0\n4x USB 2.0\n2x SATA 6Gb/s\n2x LAN 2.5GbE (TSN at Linux, optional)\n2.5 GbE\nLAN\nLAN\n\n**Right Column (Memory & Outputs):**\nMax. 128GB (4x 32GB) DDR5 TBC MT/s\n6x PCIe Gen3x1 (x4, x2, x1)\n1x PCIe Gen4 x4 (x4)\n1x PCIe Gen4 x4 (x4)\n1x PCIe Gen4 x4 (x4)\nHDA High Def. Audio\n\n**Bottom Section (Control & Management):**\nGP_SPI\neSPI\nEC\n2x I2C 2x UART 12x GPIO\nSPI\nBIOS\nTPM\n\n**Footer:**\nCOM+HPC™ Revision 1.1\nADLINK | Leading Edge AI Computing\nConfidential\n28](.introduction-com-hpc-q1-2026-2026-02-04/slide-028.jpg)

## Slide 29

![The slide features a split background, white on the left and light grey on the right.\n\n**Text elements:**\n*   **Top Left:** "Mini Type"\n*   **Center:** "COM+HPC®" (The "+" is a green four-pointed star).\n*   **Bottom Left:** "ADLINK | Leading Edge AI Computing"\n*   **Bottom Center:** "Confidential"\n*   **Bottom Right:** "29"](.introduction-com-hpc-q1-2026-2026-02-04/slide-029.jpg)

## Slide 30

![**Title:**\nCOM HPC Mini type pin groups\n\n**Description Text:**\nCOM-HPC Mini targets applications that can benefit from the cutting-edge features of COM-HPC but have smaller footprint, power, and cost constraints. It uses a smaller board size than the Client and Server Modules and only a single 400-pin connector.\n\n**Diagram (Right):**\n- Label: Mini\n- Dimensions: 70 (height) and 95 (width)\n- Internal labels: 400-pin, SOC, LPDDR (repeated four times)\n\n**Pin Groups (Bottom Row, Left to Right):**\n- 12V 5Vsb max 50W\n- Audio HAD/ I2S / SNDW\n- eDP / DSI x1\n- USB 2.0 x8\n- USB3 x2 or USB4_ 1\n- USB3 x2 or USB4_ 3\n- DDI1 DP/ HDMI\n- DDI2 DP/ HDMI\n- PCIe x16\n- PCIe targ et x1\n- NBASE- T x1\n- eSPI + CAN\n\n**Footer:**\n- ADLINK | Leading Edge AI Computing\n- Confidential\n- 30](.introduction-com-hpc-q1-2026-2026-02-04/slide-030.jpg)

## Slide 31

![This slide presents a roadmap for "COM HPC" products on a timeline from "In Production" through 2028. A legend at the top defines statuses: a blue square for "In Production," a green square for "Under Design," and a yellow square for "Under Consideration." The vertical axis is labeled "MINI," and a small image of a module is in the top right corner.\n\nTwo specific modules are detailed on the timeline:\n\n*   **COM-HPC-mMTL** (Positioned between 2024 and 2025, marked "In Production"):\n    *   Mini 95 x 70mm\n    *   Intel Core Ultra 5/7 (Meteor Lake-H/U) with NPU LPDDR5 soldered memory\n    *   Includes logos for "EXTREME RUGGED," "intel," and "AI."\n\n*   **COM-HPC-mPTL** (Positioned at 2026, marked "Under Design"):\n    *   Mini 95 x 70mm\n    *   Intel Core Ultra 5/7/9 (Panther Lake) with NPU LPDDR5 soldered memory\n    *   Includes logos for "EXTREME RUGGED," "intel," and "AI."\n\nThe footer contains "ADLINK | Leading Edge AI Computing" on the left, "Confidential" in the center, and the page number "31" on the right.](.introduction-com-hpc-q1-2026-2026-02-04/slide-031.jpg)

## Slide 32

![Specifications\nCOM-HPC-mMTL\n\nProduction\n\nProcessor: Intel® 1st Core Ultra Processor Meteor Lake-H/U\n• Core™ Ultra 7 155H 6P+8E/20T, 28W (8 Xe GPU)\n• Core™ Ultra 5 125H 4P+8E/16T, 28W (8 Xe GPU)\n• Core™ Ultra 5 125U 2P+8E/12T, 15W (4 Xe GPU)\n• Additional vPRO SKUs are not shown here, all have additional 2 Low Power E-cores\n\nNPU: integrated with up to 8.2 TOPS or 4.5 TOPS/Watt\n\nMemory\n• Up to 64 (4x 16) GB LPDDR5 non-ECC at max. 5600MT/s at dual-channel, 4 memory chip\n\nPCI Express: Gen4\n• 2 PCIex4 (x4 only, lane 8-11 & lane 12-15)\n• Up to 8 PCIex1 (x1, x2, x4 config, lane 0-3 & lane 4-7. remove NBASE-T_1, SATA_1). Default 7 PCIex1 lanes\n\nDisplay and Audio (4 independent displays)\n• DDI_0 (or USB4_2, build option), USB4_0 (or DDI_1, build option), eDP x4 lanes\n• HD Audio\n\nCamera: 2x MIPI-CSI 4lanes at two onboard FFC connector (build option, TBD)\n\nPeripherals\n• 2x 2.5GbE NBASE-T LAN (TSN at Linux, build option, TBC), up to 2x SATA 6Gb/s (remove PCIe 6/7, NBASE-T_1)\n• 2x USB 3.2 Gen2/2.0, 4x USB 2.0., 1x USB4 (USB4_1), 2x UART, 12x GPIO\n• 2x I2C, 1x SMB, ESPI\n• NVMe Gen4 SSD (build option, only for 28W SKU)\n\nAMI EFI BIOS and Security (TPM 2.0 chip on module)\nDebug Connector: DB40-HPC access to I2C for POST code, test points, SPI, SMB\nVoltage Input : AT/ATX: 8V to 20V\nOperation Temperature\n• Extended -40°C to +85°C (selected SKUs, TBC)\n• Standard 0°C to 60°C\n\nStandard supported\nWindows 11\nWindows 10\nUbuntu\nyocto PROJECT\n\nintel.\n\nCOM+HPC\nRevision 1.2\n\nintel CORE ULTRA\nXe LPG\nHDMI\n2x MIPI-CSI\nPCI EXPRESS 4\nEXTREME RUGGED\n2.5GbE\n2.5GbE\neDP\nSUPER SPEED 4.0 USB\nSERIAL ATA 6Gb/s\n\nADLINK | Leading Edge AI Computing\nConfidential\n32](.introduction-com-hpc-q1-2026-2026-02-04/slide-032.jpg)

## Slide 33

![Function Diagram\nCOM-HPC-mMTL\n\nProduction\n\nPCIe Gen4 x4 (port 8-11)\nPCIe Gen4 x4 (port 12-15)\nNVMe SSD (28W SKU only)\nDDI 0(USB4_2):\nDP/HDMI/DVI\neDP x4\nlanes\nUSB4_0(DDI_1)\nUSB4_1(USB3_3)\n2x USB 3.2/2.0\n4x USB 2.0\n\nintel\nCORE\nULTRA\n\nNVMe\nSSD\n(build option)\n4K\n\nup to 2x SATA 6Gb\n(mux with PCIe 6/7)\n\nCOM+HPC™\nRevision 1.2\n\nESPI\nEC\nSP\nI\nBIOS\nTPM\nGP_SPI\n(build option, TBC)\n2x\nUART\n12x\nGPIO\n\nMax. 64GB (4x 16GB)\nLPDDR5, non-ECC\nup to 8x PCIe Gen4 x1\n(port 0-7)\n(x4, x2, x1 config at lane 0-3)\n(x4, x2, x1 config at lane 4-7)\nPort 7 mux with SATA_0/NBAS_T_1\nPort 6 mux with SATA_1\n2x 2.5 Gb LAN\nLAN\ncontroll\ner\n2.5\nGbE\n\nHD\nA\n2x MIPI-CSI x4 lanes\n(on-board FFC connector)\n(build option) (TBC)\n\nADLINK | Leading Edge AI\nComputing\nConfidential\n33](.introduction-com-hpc-q1-2026-2026-02-04/slide-033.jpg)

## Slide 34

![**Header:**\nSpecifications\nCOM-HPC-mPTL\n\n**Top Right:**\nDesign\nSample Q2\n'26\n\n**Main Body (Left Column):**\nProcessor: Intel® new Gen Core Ultra Processor Panther Lake\n• Core™ Ultra 9 4P+8E+4LP-E, 25W (12 Xe GPU) (no PEG)\n• Core™ Ultra 9 4P+8E+4LP-E, 25W (4 Xe GPU)\n• Core™ Ultra 7 4P+8E+4LP-E, 25W (4 Xe GPU)\n• Other SKUs and even native -40 to 85 SKUs not shown here\nNPU: integrated with up to 50 TOPS\nMemory\n• Up to 64 (4x 16) GB LPDDR5 non-ECC at max. 8XXXMT/s at dual-channel, 4 memory chip\nPCI Express: Gen5 & Gen4\n• 2 PCIe Gen5 x4 (2 x4 or 1 x8, lane 8-11 & lane 12-15) (specific CPU SKU)\n• Up to 8 PCIe lanes (x1, x2, x4 at lane 0-3) (x1, x2 at lane 4-5) (x2 only at lane 6-7) (x4 at lane 4-7 option)\nDisplay and Audio (4 independent displays)\n• DDI_0 and USB4_0, USB4_1 (other DDI or USB 3.x combination is by build option)\n• eDP x4 lanes\n• HD Audio (I2S, Soundwire TBC)\nCamera: 2x MIPI-CSI 4lanes at two onboard FFC connector (build option, TBD)\nPeripherals\n• Up to 2x 2.5GbE NBASE-T Ethernet\n• Default 2x USB 3.x/2.0, 6x USB 2.0 (two of USB2.0 signals used for USB4 implementation)\n• 2x UART, 12x GPIO, 2x I2C, 1x SMB, 1x GP_SPI (build option, TBC), ESPI\n• NVMe PCIe Gen4 SSD (build option, x2 lanes default.)\nAMI EFI BIOS and Security (TPM 2.0 chip on module)\nDebug Connector: DB40-HPC access to I2C for POST code, test points, SPI, SMB\nVoltage Input : AT/ATX: 8V to 20V\nOperation Temperature\n• Extended -40°C to +85°C (selected SKUs, TBC)\n• Standard 0°C to 60°C\n\n**Middle Column (Logos & Info):**\nStandard supported\nWindows 11\nUbuntu\nyocto PROJECT (TBC)\n\n**Right Side:**\nintel\n[Image of a computer chip/module]\nAI\nCOM+HPC\nRevision\n1.2\n\n**Bottom Right Logos:**\nSeries 3 intel CORE ULTRA 9\nintel ARC GRAPHICS\nHDMI\n2.5GbE\n2.5GbE\n2x MIPI-CSI\neDP\nPCI EXPRESS 5\nPCI EXPRESS 4\nSUPER SPEED USB 4.0\nSERIAL ATA\nEXTREME RUGGED\n\n**Footer:**\nADLINK | Leading Edge AI Computing\nConfidential\n34](.Introduction-COM-HPC-Q1-2026-[2026-02-04]/slide_034.jpg)

## Slide 35

![Function Diagram\nCOM-HPC-mPTL\n\nDesign\nSample Q2\n'26\n\nPCIe Gen5 x4 (port 8-11)*\nPCIe Gen5 x4 (port 12-15)*\nNVMe SSD (specific SKU\nonly)\nDDI 0(USB4_2):\nDP/HDMI/DVI\neDP x4\nlanes\nUSB4_0(DDI_1)\nUSB4_1(USB3_3)\n2x USB 3.2/2.0\n4x USB 2.0\n\nNVMe SSD\n(build option)\n4K\n\nintel\nCORE\nULTRA\n\nMax. 64GB (4x 16GB)\nLPDDR5, non-ECC\nup to 8x PCIe Gen4 x1\n(port 0-7)\n(x4, x2, x1 config at lane 0-3)\n(x2, x1 config at lane 4-5)\n(x2 only at lane 6-7)\n\nLAN controller\n2.5\nGbE\n2x 2.5GbpD LAN\n\nHD\nA\n2x MIPI-CSI x4 lanes\n(on-board FFC connector)\n(build option) (TBC)\n\nESPI\nGP_SPI\n(build option, TBC)\n2x\nUART\n12x\nGPIO\nEC\nBIOS\nTPM\nSPI\n\nCOM+HPC\nRevision 1.2\n\nADLINK | Leading Edge AI\nComputing\n\nNote: PCIe Gen5 x4 at port 8-11, port 12-15 available for specific CPU\nSKU only\nConfidential\n35](.introduction-com-hpc-q1-2026-2026-02-04/slide-035.jpg)

## Slide 36

![The slide features a large red background with a geometric pattern of white triangles arranged in a repeating lattice.\n\nIn the bottom left corner of the red section, white text displays company information:\nADLINK Technology,\nInc. No. 66, Huaya 1st Rd., Guishan Dist.,\nTaoyuan City 33411, Taiwan\nTel: +886-3-216-5088\nFax: +886-3-328-5706\n\nIn the bottom right corner of the red section, four social media icons (Twitter, Facebook, YouTube, LinkedIn) are followed by the website address:\nwww.adlinktech.com\n\nBelow the red rectangle, on the white background, is the text:\nADLINK | Leading Edge AI\nComputing](.introduction-com-hpc-q1-2026-2026-02-04/slide-036.jpg)

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